Per the BSA specification, PCI_MM_04 requires systems to support 32-bit programming of 32-bit BARs on applicable endpoints, regardless of whether the BAR is prefetchable or non-prefetchable.
However, the current PCI_MM_04 test appears to check whether certain Type-1 PCIe devices expose a non-prefetchable 32-bit memory type, so this does not seem to fully validate the BSA requirement RPCI_MM_04.
Specifically, the current test does not appear to verify all applicable endpoints with Type-0 headers. Instead, it:
- Scans only RCiEP/RCEC/iEP-related entries.
- Allows only Type-1 header devices.
- Checks the memory type of Type-1 PCIe devices, rather than validating 32-bit endpoint BARs.
It is also unclear why the test reports failure when a Type-1 PCIe device is not a 32-bit memory type. If there are no applicable endpoints with 32-bit BARs, the test may need to report WARNING and ask users to manually review the rule, rather than reporting failure based only on Type-1 BAR/memory type.
It seems that the test should be updated to at least check the following:
- Whether applicable endpoints with 32-bit BARs are present.
- Whether those 32-bit BARs can actually be programmed.
- Whether the assigned PCI memory address is below 4GB.
- Whether PE physical address space below 4GB is reserved for 32-bit BARs.
- Whether CPU-side accesses to the programmed BAR work correctly after assignment. This may require exerciser.
The following is the rule statements in the BSA spec for reference:
- RPCI_MM_04 Systems compliant to this specification must support 32-bit programming of 32-bit BARs on such endpoints. This can be achieved in two ways:
- Method 1: PE physical address space can be reserved below 4GB, whilst maintaining a one-to-one mapping between PE physical address space and 32-bit BAR memory address space.
- Method 2: It is also possible to use a fixed offset translation scheme that creates a fixed offset indirection between PE physical address space, and PCI memory. This allows a window in PE physical address space that is above 4GB to be mirrored in PCI memory space below 4GB. This requires support in the PHB. Furthermore, firmware must program the PHB with the fixed offset, and to supply this information to the OS [4].
- Caution should be used with fixed offset translation schemes. Some devices might have software compatibility issues with accessing 64-bit addresses.
Cc @chetan-rathore @gowthamsiddarthd @anncheng-arm
Per the BSA specification, PCI_MM_04 requires systems to support 32-bit programming of 32-bit BARs on applicable endpoints, regardless of whether the BAR is prefetchable or non-prefetchable.
However, the current PCI_MM_04 test appears to check whether certain Type-1 PCIe devices expose a non-prefetchable 32-bit memory type, so this does not seem to fully validate the BSA requirement RPCI_MM_04.
Specifically, the current test does not appear to verify all applicable endpoints with Type-0 headers. Instead, it:
It is also unclear why the test reports failure when a Type-1 PCIe device is not a 32-bit memory type. If there are no applicable endpoints with 32-bit BARs, the test may need to report WARNING and ask users to manually review the rule, rather than reporting failure based only on Type-1 BAR/memory type.
It seems that the test should be updated to at least check the following:
The following is the rule statements in the BSA spec for reference:
Cc @chetan-rathore @gowthamsiddarthd @anncheng-arm