I have analyzed the implementation in src/core/diffusion/euler_grid.cc.
While the current code effectively utilizes OpenMP and SIMD directives, the 7-point stencil computations(specifically within the diffusion kernel) remain memory-bound on standard CPU architectures due to repeated data access patterns.
As BioDynaMo simulations scale to larger grid resolutions, this diffusion step consumes a significant portion of the total simulation time. Furthermore, purely software-based execution presents challenges for Green Computing goals regarding energy efficiency per simulation step.
I propose exploring an FPGA-based hardware backend for the EulerGrid diffusion solvers using AMD Vitis HLS
This approach leverages a Dataflow Architecture to overcome the Von Neumann memory bottleneck:
- Line Buffering: Unlike CPU caches, FPGAs can implement custom on-chip buffering (Window Buffers) to maximize data reuse for Stencil operations, drastically reducing off-chip memory access.
- Pipelining: We can target an Initiation Interval (II) of 1, processing one voxel per clock cycle.
- Energy Efficiency: Offloading these dense loop computations to FPGA logic significantly improves performance-per-watt compared to standard HPC nodes.
Feasibility Analysis (Preliminary Benchmarks)
To validate this proposal, I prototyped a C-Simulation of the 3D Stencil Kernel (64x64x64 grid partition) targeting a Xilinx Zynq UltraScale+ (ZU9EG) platform using Vitis HLS.
Initial Comparison Results (Per Step):
CPU (Optimized C++ / Standard x86_64 Core): ~5.67 ms
FPGA (Vitis HLS Synthesis): ~2.91 ms (@ 300 MHz, II=1)
Note: This is a preliminary synthesis report. Even without full memory hierarchy optimization, it demonstrates a ~1.95x speedup potential with deterministic latency and lower energy footprint.
I am a Software Engineering student researching hardware acceleration for scientific computing.
Would the maintainers be open to a PR or a discussion regarding an optional FPGA backend for the Euler diffusion solver?The proposed backend would be strictly optional, gated behind a build flag, and would not affect the default CPU execution path.
I have analyzed the implementation in
src/core/diffusion/euler_grid.cc.While the current code effectively utilizes OpenMP and SIMD directives, the 7-point stencil computations(specifically within the diffusion kernel) remain memory-bound on standard CPU architectures due to repeated data access patterns.
As BioDynaMo simulations scale to larger grid resolutions, this diffusion step consumes a significant portion of the total simulation time. Furthermore, purely software-based execution presents challenges for Green Computing goals regarding energy efficiency per simulation step.
I propose exploring an FPGA-based hardware backend for the
EulerGriddiffusion solvers using AMD Vitis HLSThis approach leverages a Dataflow Architecture to overcome the Von Neumann memory bottleneck:
Feasibility Analysis (Preliminary Benchmarks)
To validate this proposal, I prototyped a C-Simulation of the 3D Stencil Kernel (64x64x64 grid partition) targeting a Xilinx Zynq UltraScale+ (ZU9EG) platform using Vitis HLS.
Initial Comparison Results (Per Step):
CPU (Optimized C++ / Standard x86_64 Core): ~5.67 ms
FPGA (Vitis HLS Synthesis): ~2.91 ms (@ 300 MHz, II=1)
Note: This is a preliminary synthesis report. Even without full memory hierarchy optimization, it demonstrates a ~1.95x speedup potential with deterministic latency and lower energy footprint.
I am a Software Engineering student researching hardware acceleration for scientific computing.
Would the maintainers be open to a PR or a discussion regarding an optional FPGA backend for the Euler diffusion solver?The proposed backend would be strictly optional, gated behind a build flag, and would not affect the default CPU execution path.