From 0bb1ca24d1c8c5052f315f72eed72564e823f4ca Mon Sep 17 00:00:00 2001 From: felipebpl Date: Sun, 5 Jun 2022 20:55:35 -0300 Subject: [PATCH 01/23] adicionando pasta inicial --- .../ACC_EXAMPLE1/.vs/ACC_EXAMPLE1/v14/.atsuo | Bin 0 -> 18944 bytes .../ACC/ACC_EXAMPLE1/ACC_EXAMPLE1.atsln | 22 + .../ACC_EXAMPLE1.componentinfo.xml | 4 + .../ACC_EXAMPLE1/ACC_EXAMPLE1.cproj | 1263 +++ .../src/ASF/common/boards/board.h | 453 ++ .../src/ASF/common/services/clock/genclk.h | 189 + .../src/ASF/common/services/clock/osc.h | 175 + .../src/ASF/common/services/clock/pll.h | 331 + .../ASF/common/services/clock/same70/genclk.h | 320 + .../ASF/common/services/clock/same70/osc.h | 237 + .../ASF/common/services/clock/same70/pll.h | 259 + .../ASF/common/services/clock/same70/sysclk.c | 258 + .../ASF/common/services/clock/same70/sysclk.h | 463 ++ .../src/ASF/common/services/clock/sysclk.h | 184 + .../src/ASF/common/services/gpio/gpio.h | 76 + .../common/services/gpio/sam_gpio/sam_gpio.h | 73 + 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Format Version 11.00 +VisualStudioVersion = 14.0.23107.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "ACC_EXAMPLE1", "ACC_EXAMPLE1\ACC_EXAMPLE1.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|ARM = Debug|ARM + Release|ARM = Release|ARM + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/ACC_EXAMPLE1.componentinfo.xml b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/ACC_EXAMPLE1.componentinfo.xml new file mode 100644 index 00000000..e2757552 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/ACC_EXAMPLE1.componentinfo.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/ACC_EXAMPLE1.cproj b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/ACC_EXAMPLE1.cproj new file mode 100644 index 00000000..7cee73e2 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/ACC_EXAMPLE1.cproj @@ -0,0 +1,1263 @@ + + + + 2.0 + 7.0 + com.Atmel.ARMGCC.C + dce6c7e3-ee26-4d79-826b-08594b9ad897 + ATSAME70Q21B + same70 + Executable + C + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + ACC_EXAMPLE1 + ACC_EXAMPLE1 + ACC_EXAMPLE1 + Native + true + false + true + true + + + true + + 2 + 0 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + True + True + True + True + True + + + NDEBUG + __SAME70Q21B__ + BOARD=SAME70_XPLAINED + scanf=iscanf + ARM_MATH_CM7=true + printf=iprintf + + + + + ../src/ASF/sam/drivers/acc + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/sam/drivers/afec + ../src/ASF/common/services/sleepmgr + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/dacc + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/same70_xplained + ../src/ASF/sam/boards + ../src/ASF/common/boards + ../src/ASF/common/services/ioport + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src + ../src/config + + + Optimize for size (-Os) + -fdata-sections + True + True + -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=fpv5-sp-d16 + + + libarm_cortexM7lfsp_math_softfp + libm + + + + + ../src/ASF/thirdparty/CMSIS/Lib/GCC + + + True + -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam/utils/linker_scripts/same70/same70q21/gcc/flash.ld + + + ../src/ASF/sam/drivers/acc + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/sam/drivers/afec + ../src/ASF/common/services/sleepmgr + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/dacc + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/same70_xplained + ../src/ASF/sam/boards + ../src/ASF/common/boards + ../src/ASF/common/services/ioport + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src + ../src/config + + + -DARM_MATH_CM7=true -DBOARD=SAME70_XPLAINED -D__SAME70Q21B__ -Dprintf=iprintf -Dscanf=iscanf + + + ../src/ASF/sam/drivers/acc + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/sam/drivers/afec + ../src/ASF/common/services/sleepmgr + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/dacc + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/same70_xplained + ../src/ASF/sam/boards + ../src/ASF/common/boards + ../src/ASF/common/services/ioport + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src + ../src/config + + + + + + + + + True + True + True + True + True + + + DEBUG + __SAME70Q21B__ + BOARD=SAME70_XPLAINED + scanf=iscanf + ARM_MATH_CM7=true + printf=iprintf + + + + + ../src/ASF/sam/drivers/acc + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/sam/drivers/afec + ../src/ASF/common/services/sleepmgr + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/dacc + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/same70_xplained + ../src/ASF/sam/boards + ../src/ASF/common/boards + ../src/ASF/common/services/ioport + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src + ../src/config + + + Optimize (-O1) + -fdata-sections + True + Maximum (-g3) + True + -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=fpv5-sp-d16 + + + libarm_cortexM7lfsp_math_softfp + libm + + + + + ../src/ASF/thirdparty/CMSIS/Lib/GCC + + + True + -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam/utils/linker_scripts/same70/same70q21/gcc/flash.ld + + + ../src/ASF/sam/drivers/acc + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/sam/drivers/afec + ../src/ASF/common/services/sleepmgr + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/dacc + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/same70_xplained + ../src/ASF/sam/boards + ../src/ASF/common/boards + ../src/ASF/common/services/ioport + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src + ../src/config + + + Default (-g) + -DARM_MATH_CM7=true -DBOARD=SAME70_XPLAINED -D__SAME70Q21B__ -Dprintf=iprintf -Dscanf=iscanf + + + ../src/ASF/sam/drivers/acc + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/sam/drivers/afec + ../src/ASF/common/services/sleepmgr + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/dacc + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/same70_xplained + ../src/ASF/sam/boards + ../src/ASF/common/boards + ../src/ASF/common/services/ioport + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src + ../src/config + + + Default (-Wa,-g) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + \ No newline at end of file diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/boards/board.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/boards/board.h new file mode 100644 index 00000000..f6b0c32e --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/boards/board.h @@ -0,0 +1,453 @@ +/** + * \file + * + * \brief Standard board header file. + * + * This file includes the appropriate board header file according to the + * defined board (parameter BOARD). + * + * Copyright (c) 2009-2020 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/** + * \defgroup group_common_boards Generic board support + * + * The generic board support module includes board-specific definitions + * and function prototypes, such as the board initialization function. + * + * \{ + */ + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/*! \name Base Boards + */ +//! @{ +#define EVK1100 1 //!< AT32UC3A EVK1100 board. +#define EVK1101 2 //!< AT32UC3B EVK1101 board. +#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board. +#define EVK1104 4 //!< AT32UC3A3 EVK1104 board. +#define EVK1105 5 //!< AT32UC3A EVK1105 board. +#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board. +#define UC3L_EK 7 //!< AT32UC3L-EK board. +#define XPLAIN 8 //!< ATxmega128A1 Xplain board. +#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board. +#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board. +#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board. +#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board. +#define STK600_RCUC3D 16 //!< STK600 RCUC3D board. +#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board. +#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board. +#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board. +#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board. +#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board. +#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board. +#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board. +#define STK600_RC044X 24 //!< STK600 with RC044X routing card board. +#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board. +#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board. +#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board. +#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board. +#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board. +#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards. +#define RZ600 31 //!< AT32UC3A RZ600 MCU board. +#define SAM3S_EK 32 //!< SAM3S-EK board. +#define SAM3U_EK 33 //!< SAM3U-EK board. +#define SAM3X_EK 34 //!< SAM3X-EK board. +#define SAM3N_EK 35 //!< SAM3N-EK board. +#define SAM3S_EK2 36 //!< SAM3S-EK2 board. +#define SAM4S_EK 37 //!< SAM4S-EK board. +#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board. +#define STK600_MEGA 39 //!< STK600 MEGA board. +#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board. +#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board. +#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board. +#define ARDUINO_DUE_X 43 //!< Arduino Due/X board. +#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board. +#define SAM4L_EK 45 //!< SAM4L-EK board. +#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board. +#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board. +#define STK600_RC032X 48 //!< STK600 with RC032X routing card board. +#define SAM4S_EK2 49 //!< SAM4S-EK2 board. +#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board. +#define SAM4E_EK 51 //!< SAM4E-EK board. +#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board. +#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board. +#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board. +#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit. +#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit. +#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit. +#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board. +#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board. +#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board. +#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board. +#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board. +#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB. +#define SAM4C_EK 64 //!< SAM4C-EK board. +#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board. +#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board. +#define SAM4CP16BMB 67 //!< SAM4CP16BMB board. +#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board. +#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board. +#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board. +#define SAM4CMP_DB 71 //!< SAM4CMP demo board. +#define SAM4CMS_DB 72 //!< SAM4CMS demo board. +#define ATPL230AMB 73 //!< ATPL230AMB board. +#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board. +#define SAMG55_XPLAINED_PRO 75 //!< SAMG55 Xplained Pro board. +#define SAML21_XPLAINED_PRO 76 //!< SAM L21 Xplained Pro board. +#define SAMD10_XPLAINED_MINI 77 //!< SAM D10 Xplained Mini board. +#define SAMDA1_XPLAINED_PRO 78 //!< SAM DA1 Xplained Pro board. +#define SAMW25_XPLAINED_PRO 79 //!< SAMW25 Xplained Pro board. +#define SAMC21_XPLAINED_PRO 80 //!< SAM C21 Xplained Pro board. +#define SAMV71_XPLAINED_ULTRA 81 //!< SAMV71 Xplained Ultra board. +#define ATMEGA328P_XPLAINED_MINI 82 //!< ATMEGA328P Xplained MINI board. +#define ATMEGA328PB_XPLAINED_MINI 83 //!< ATMEGA328PB Xplained MINI board. +#define SAMB11_XPLAINED_PRO 84 //!< SAM B11 Xplained Pro board. +#define SAME70_XPLAINED 85 //!< SAME70 Xplained board. +#define SAML22_XPLAINED_PRO 86 //!< SAM L22 Xplained Pro board. +#define SAML22_XPLAINED_PRO_B 87 //!< SAM L22 Xplained Pro board. +#define SAMR21ZLL_EK 88 //!< SAMR21ZLL-EK board. +#define ATMEGA168PB_XPLAINED_MINI 89 //!< ATMEGA168PB Xplained MINI board. +#define ATMEGA324PB_XPLAINED_PRO 90 //!< ATMEGA324PB Xplained Pro board. +#define SAMB11ZR_XPLAINED_PRO 92 //!< SAM B11 ZR Xplained Pro board. +#define SAMR30_XPLAINED_PRO 93 //!< SAM R30 Xplained Pro board. +#define SAMHA1G16A_XPLAINED_PRO 94 //!< SAM HA1G16A Xplained Pro board. +#define SAMR34_XPLAINED_PRO 95 //!< SAM R34 Xplained Pro board. +#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices. +#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family. +#define USER_BOARD 99 //!< User-reserved board (if any). +#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader). +#define SAMB11ZR_SENSOR_TAG 101 //!< SAMB11ZR sensor tag board +#define SAMR30_MODULE_XPLAINED_PRO 102 //!< SAM R30 Module Xplained Pro board. +#define SAMR21G18_MODULE 103 //!< SAMR21G18-MR210UA Module. +#define SAMR21B18_MODULE 104 //!< SAMR21B18-MZ210PA Module. +#define WLR089_XPLAINED_PRO 105 //!< WLR089_XPLAINED_PRO board. +//! @} + +/*! \name Extension Boards + */ +//! @{ +#define EXT1102 1 //!< AT32UC3B EXT1102 board +#define MC300 2 //!< AT32UC3 MC300 board +#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1 +#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2 +#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board +#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board +#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A" +#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600 +#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600 +#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600 +#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard +#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board +#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any). +//! @} + +#if BOARD == EVK1100 +# include "evk1100/evk1100.h" +#elif BOARD == EVK1101 +# include "evk1101/evk1101.h" +#elif BOARD == UC3C_EK +# include "uc3c_ek/uc3c_ek.h" +#elif BOARD == EVK1104 +# include "evk1104/evk1104.h" +#elif BOARD == EVK1105 +# include "evk1105/evk1105.h" +#elif BOARD == STK600_RCUC3L0 +# include "stk600/rcuc3l0/stk600_rcuc3l0.h" +#elif BOARD == UC3L_EK +# include "uc3l_ek/uc3l_ek.h" +#elif BOARD == STK600_RCUC3L4 +# include "stk600/rcuc3l4/stk600_rcuc3l4.h" +#elif BOARD == XPLAIN +# include "xplain/xplain.h" +#elif BOARD == STK600_MEGA + /*No header-file to include*/ +#elif BOARD == STK600_MEGA_RF +# include "stk600.h" +#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO +# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h" +#elif BOARD == ATMEGA256RFR2_ZIGBIT +# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h" +#elif BOARD == STK600_RC032X +# include "stk600/rc032x/stk600_rc032x.h" +#elif BOARD == STK600_RC044X +# include "stk600/rc044x/stk600_rc044x.h" +#elif BOARD == STK600_RC064X +# include "stk600/rc064x/stk600_rc064x.h" +#elif BOARD == STK600_RC100X +# include "stk600/rc100x/stk600_rc100x.h" +#elif BOARD == UC3_A3_XPLAINED +# include "uc3_a3_xplained/uc3_a3_xplained.h" +#elif BOARD == UC3_L0_XPLAINED +# include "uc3_l0_xplained/uc3_l0_xplained.h" +#elif BOARD == STK600_RCUC3B0 +# include "stk600/rcuc3b0/stk600_rcuc3b0.h" +#elif BOARD == STK600_RCUC3D +# include "stk600/rcuc3d/stk600_rcuc3d.h" +#elif BOARD == STK600_RCUC3C0 +# include "stk600/rcuc3c0/stk600_rcuc3c0.h" +#elif BOARD == SAMG53_XPLAINED_PRO +# include "samg53_xplained_pro/samg53_xplained_pro.h" +#elif BOARD == SAMG55_XPLAINED_PRO +# include "samg55_xplained_pro/samg55_xplained_pro.h" +#elif BOARD == XMEGA_B1_XPLAINED +# include "xmega_b1_xplained/xmega_b1_xplained.h" +#elif BOARD == STK600_RC064X_LCDX +# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h" +#elif BOARD == STK600_RC100X_LCDX +# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h" +#elif BOARD == XMEGA_A1_XPLAINED +# include "xmega_a1_xplained/xmega_a1_xplained.h" +#elif BOARD == XMEGA_A1U_XPLAINED_PRO +# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h" +#elif BOARD == UC3_L0_XPLAINED_BC +# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h" +#elif BOARD == SAM3S_EK +# include "sam3s_ek/sam3s_ek.h" +# include "system_sam3s.h" +#elif BOARD == SAM3S_EK2 +# include "sam3s_ek2/sam3s_ek2.h" +# include "system_sam3sd8.h" +#elif BOARD == SAM3U_EK +# include "sam3u_ek/sam3u_ek.h" +# include "system_sam3u.h" +#elif BOARD == SAM3X_EK +# include "sam3x_ek/sam3x_ek.h" +# include "system_sam3x.h" +#elif BOARD == SAM3N_EK +# include "sam3n_ek/sam3n_ek.h" +# include "system_sam3n.h" +#elif BOARD == SAM4S_EK +# include "sam4s_ek/sam4s_ek.h" +# include "system_sam4s.h" +#elif BOARD == SAM4S_WPIR_RD +# include "sam4s_wpir_rd/sam4s_wpir_rd.h" +# include "system_sam4s.h" +#elif BOARD == SAM4S_XPLAINED +# include "sam4s_xplained/sam4s_xplained.h" +# include "system_sam4s.h" +#elif BOARD == SAM4S_EK2 +# include "sam4s_ek2/sam4s_ek2.h" +# include "system_sam4s.h" +#elif BOARD == MEGA_1284P_XPLAINED + /*No header-file to include*/ +#elif BOARD == ARDUINO_DUE_X +# include "arduino_due_x/arduino_due_x.h" +# include "system_sam3x.h" +#elif BOARD == SAM4L_EK +# include "sam4l_ek/sam4l_ek.h" +#elif BOARD == SAM4E_EK +# include "sam4e_ek/sam4e_ek.h" +#elif BOARD == SAMD20_XPLAINED_PRO +# include "samd20_xplained_pro/samd20_xplained_pro.h" +#elif BOARD == SAMD21_XPLAINED_PRO +# include "samd21_xplained_pro/samd21_xplained_pro.h" +#elif BOARD == SAMR21_XPLAINED_PRO +# include "samr21_xplained_pro/samr21_xplained_pro.h" +#elif BOARD == SAMR30_XPLAINED_PRO && defined(__SAMR30G18A__) +# include "samr30_xplained_pro/samr30_xplained_pro.h" +#elif BOARD == SAMR30_MODULE_XPLAINED_PRO && defined(__SAMR30E18A__) +# include "samr30_module_xplained_pro/samr30_module_xplained_pro.h" +#elif BOARD == SAMR21ZLL_EK +# include "samr21zll_ek/samr21zll_ek.h" +#elif BOARD == SAMD11_XPLAINED_PRO +# include "samd11_xplained_pro/samd11_xplained_pro.h" +#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__) +# include "saml21_xplained_pro/saml21_xplained_pro.h" +#elif BOARD == SAML22_XPLAINED_PRO +# include "saml22_xplained_pro/saml22_xplained_pro.h" +#elif BOARD == SAML22_XPLAINED_PRO_B +# include "saml22_xplained_pro_b/saml22_xplained_pro_b.h" +#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__) +# include "saml21_xplained_pro_b/saml21_xplained_pro.h" +#elif BOARD == SAMD10_XPLAINED_MINI +# include "samd10_xplained_mini/samd10_xplained_mini.h" +#elif BOARD == SAMDA1_XPLAINED_PRO +# include "samda1_xplained_pro/samda1_xplained_pro.h" +#elif BOARD == SAMHA1G16A_XPLAINED_PRO +# include "samha1g16a_xplained_pro/samha1g16a_xplained_pro.h" +#elif BOARD == SAMC21_XPLAINED_PRO +# include "samc21_xplained_pro/samc21_xplained_pro.h" +#elif BOARD == SAM4N_XPLAINED_PRO +# include "sam4n_xplained_pro/sam4n_xplained_pro.h" +#elif BOARD == SAMW25_XPLAINED_PRO +# include "samw25_xplained_pro/samw25_xplained_pro.h" +#elif BOARD == SAMV71_XPLAINED_ULTRA +# include "samv71_xplained_ultra/samv71_xplained_ultra.h" +#elif BOARD == MEGA1284P_XPLAINED_BC +# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h" +#elif BOARD == UC3_L0_QT600 +# include "uc3_l0_qt600/uc3_l0_qt600.h" +#elif BOARD == XMEGA_A3BU_XPLAINED +# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h" +#elif BOARD == XMEGA_E5_XPLAINED +# include "xmega_e5_xplained/xmega_e5_xplained.h" +#elif BOARD == UC3B_BOARD_CONTROLLER +# include "uc3b_board_controller/uc3b_board_controller.h" +#elif BOARD == RZ600 +# include "rz600/rz600.h" +#elif BOARD == STK600_RCUC3A0 +# include "stk600/rcuc3a0/stk600_rcuc3a0.h" +#elif BOARD == ATXMEGA128A1_QT600 +# include "atxmega128a1_qt600/atxmega128a1_qt600.h" +#elif BOARD == STK600_RCUC3L3 +# include "stk600/rcuc3l3/stk600_rcuc3l3.h" +#elif BOARD == SAM4S_XPLAINED_PRO +# include "sam4s_xplained_pro/sam4s_xplained_pro.h" +#elif BOARD == SAM4L_XPLAINED_PRO +# include "sam4l_xplained_pro/sam4l_xplained_pro.h" +#elif BOARD == SAM4L8_XPLAINED_PRO +# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h" +#elif BOARD == SAM4C_EK +# include "sam4c_ek/sam4c_ek.h" +#elif BOARD == SAM4CMP_DB +# include "sam4cmp_db/sam4cmp_db.h" +#elif BOARD == SAM4CMS_DB +# include "sam4cms_db/sam4cms_db.h" +#elif BOARD == SAM4CP16BMB +# include "sam4cp16bmb/sam4cp16bmb.h" +#elif BOARD == ATPL230AMB +# include "atpl230amb/atpl230amb.h" +#elif BOARD == XMEGA_C3_XPLAINED +# include "xmega_c3_xplained/xmega_c3_xplained.h" +#elif BOARD == XMEGA_RF233_ZIGBIT +# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h" +#elif BOARD == XMEGA_A3_REB_CBB +# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h" +#elif BOARD == ATMEGARFX_RCB +# include "atmegarfx_rcb/atmegarfx_rcb.h" +#elif BOARD == RCB256RFR2_XPRO +# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h" +#elif BOARD == XMEGA_RF212B_ZIGBIT +# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h" +#elif BOARD == SAM4E_XPLAINED_PRO +# include "sam4e_xplained_pro/sam4e_xplained_pro.h" +#elif BOARD == ATMEGA328P_XPLAINED_MINI +# include "atmega328p_xplained_mini/atmega328p_xplained_mini.h" +#elif BOARD == ATMEGA328PB_XPLAINED_MINI +# include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h" +#elif BOARD == SAMB11_XPLAINED_PRO +# include "samb11_xplained_pro/samb11_xplained_pro.h" +#elif BOARD == SAME70_XPLAINED +# include "same70_xplained/same70_xplained.h" +#elif BOARD == ATMEGA168PB_XPLAINED_MINI +# include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h" +#elif BOARD == ATMEGA324PB_XPLAINED_PRO +# include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h" +#elif BOARD == SAMB11ZR_XPLAINED_PRO +# include "samb11zr_xplained_pro/samb11zr_xplained_pro.h" +#elif BOARD == SIMULATOR_XMEGA_A1 +# include "simulator/xmega_a1/simulator_xmega_a1.h" +#elif BOARD == AVR_SIMULATOR_UC3 +# include "avr_simulator_uc3/avr_simulator_uc3.h" +#elif BOARD == SAMR21G18_MODULE +# include "samr21g18_module/samr21g18_module.h" +#elif BOARD == SAMR21B18_MODULE +# include "samr21b18_module/samr21b18_module.h" +#elif BOARD == SAMR34_XPLAINED_PRO && defined(__SAMR34J18B__) +# include "samr34_xplained_pro/samr34_xplained_pro.h" +#elif BOARD == WLR089_XPLAINED_PRO && defined(__WLR089U0__) +# include "wlr089_xplained_pro/wlr089_xplained_pro.h" +#elif BOARD == USER_BOARD +// User-reserved area: #include the header file of your board here (if any). +# include "user_board.h" +#elif BOARD == DUMMY_BOARD +# include "dummy/dummy_board.h" +#elif BOARD == SAMB11ZR_SENSOR_TAG +# include "samb11zr_sensor_tag/samb11zr_sensor_tag.h" +#else +# error No known Atmel board defined +#endif + +#if (defined EXT_BOARD) +# if EXT_BOARD == MC300 +# include "mc300/mc300.h" +# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \ + (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \ + (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \ + (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \ + (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \ + (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD) +# include "sensors_xplained/sensors_xplained.h" +# elif EXT_BOARD == RZ600_AT86RF231 +# include "at86rf231/at86rf231.h" +# elif EXT_BOARD == RZ600_AT86RF230B +# include "at86rf230b/at86rf230b.h" +# elif EXT_BOARD == RZ600_AT86RF212 +# include "at86rf212/at86rf212.h" +# elif EXT_BOARD == SECURITY_XPLAINED +# include "security_xplained.h" +# elif EXT_BOARD == USER_EXT_BOARD + // User-reserved area: #include the header file of your extension board here + // (if any). +# endif +#endif + + +#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__)) +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +/*! \brief This function initializes the board target resources + * + * This function should be called to ensure proper initialization of the target + * board hardware connected to the part. + */ +extern void board_init(void); + +#endif // #ifdef __AVR32_ABI_COMPILER__ +#else +/*! \brief This function initializes the board target resources + * + * This function should be called to ensure proper initialization of the target + * board hardware connected to the part. + */ +extern void board_init(void); +#endif + + +#ifdef __cplusplus +} +#endif + +/** + * \} + */ + +#endif // _BOARD_H_ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/genclk.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/genclk.h new file mode 100644 index 00000000..882a577a --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/genclk.h @@ -0,0 +1,189 @@ +/** + * \file + * + * \brief Generic clock management + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef CLK_GENCLK_H_INCLUDED +#define CLK_GENCLK_H_INCLUDED + +#include "parts.h" + +#if SAM3S +# include "sam3s/genclk.h" +#elif SAM3U +# include "sam3u/genclk.h" +#elif SAM3N +# include "sam3n/genclk.h" +#elif SAM3XA +# include "sam3x/genclk.h" +#elif SAM4S +# include "sam4s/genclk.h" +#elif SAM4L +# include "sam4l/genclk.h" +#elif SAM4E +# include "sam4e/genclk.h" +#elif SAM4N +# include "sam4n/genclk.h" +#elif SAM4C +# include "sam4c/genclk.h" +#elif SAM4CM +# include "sam4cm/genclk.h" +#elif SAM4CP +# include "sam4cp/genclk.h" +#elif SAMG +# include "samg/genclk.h" +#elif SAMV71 +# include "samv71/genclk.h" +#elif SAMV70 +# include "samv70/genclk.h" +#elif SAME70 +# include "same70/genclk.h" +#elif SAMS70 +# include "sams70/genclk.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/genclk.h" +#elif UC3A3 +# include "uc3a3_a4/genclk.h" +#elif UC3B +# include "uc3b0_b1/genclk.h" +#elif UC3C +# include "uc3c/genclk.h" +#elif UC3D +# include "uc3d/genclk.h" +#elif UC3L +# include "uc3l/genclk.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup genclk_group Generic Clock Management + * + * Generic clocks are configurable clocks which run outside the system + * clock domain. They are often connected to peripherals which have an + * asynchronous component running independently of the bus clock, e.g. + * USB controllers, low-power timers and RTCs, etc. + * + * Note that not all platforms have support for generic clocks; on such + * platforms, this API will not be available. + * + * @{ + */ + +/** + * \def GENCLK_DIV_MAX + * \brief Maximum divider supported by the generic clock implementation + */ +/** + * \enum genclk_source + * \brief Generic clock source ID + * + * Each generic clock may be generated from a different clock source. + * These are the available alternatives provided by the chip. + */ + +//! \name Generic clock configuration +//@{ +/** + * \struct genclk_config + * \brief Hardware representation of a set of generic clock parameters + */ +/** + * \fn void genclk_config_defaults(struct genclk_config *cfg, + * unsigned int id) + * \brief Initialize \a cfg to the default configuration for the clock + * identified by \a id. + */ +/** + * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id) + * \brief Read the currently active configuration of the clock + * identified by \a id into \a cfg. + */ +/** + * \fn void genclk_config_write(const struct genclk_config *cfg, + * unsigned int id) + * \brief Activate the configuration \a cfg on the clock identified by + * \a id. + */ +/** + * \fn void genclk_config_set_source(struct genclk_config *cfg, + * enum genclk_source src) + * \brief Select a new source clock \a src in configuration \a cfg. + */ +/** + * \fn void genclk_config_set_divider(struct genclk_config *cfg, + * unsigned int divider) + * \brief Set a new \a divider in configuration \a cfg. + */ +/** + * \fn void genclk_enable_source(enum genclk_source src) + * \brief Enable the source clock \a src used by a generic clock. + */ + //@} + +//! \name Enabling and disabling Generic Clocks +//@{ +/** + * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id) + * \brief Activate the configuration \a cfg on the clock identified by + * \a id and enable it. + */ +/** + * \fn void genclk_disable(unsigned int id) + * \brief Disable the generic clock identified by \a id. + */ +//@} + +/** + * \brief Enable the configuration defined by \a src and \a divider + * for the generic clock identified by \a id. + * + * \param id The ID of the generic clock. + * \param src The source clock of the generic clock. + * \param divider The divider used to generate the generic clock. + */ +static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider) +{ + struct genclk_config gcfg; + + genclk_config_defaults(&gcfg, id); + genclk_enable_source(src); + genclk_config_set_source(&gcfg, src); + genclk_config_set_divider(&gcfg, divider); + genclk_enable(&gcfg, id); +} + +//! @} + +#endif /* CLK_GENCLK_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/osc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/osc.h new file mode 100644 index 00000000..1547e065 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/osc.h @@ -0,0 +1,175 @@ +/** + * \file + * + * \brief Oscillator management + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef OSC_H_INCLUDED +#define OSC_H_INCLUDED + +#include "parts.h" +#include "conf_clock.h" + +#if SAM3S +# include "sam3s/osc.h" +#elif SAM3XA +# include "sam3x/osc.h" +#elif SAM3U +# include "sam3u/osc.h" +#elif SAM3N +# include "sam3n/osc.h" +#elif SAM4S +# include "sam4s/osc.h" +#elif SAM4E +# include "sam4e/osc.h" +#elif SAM4C +# include "sam4c/osc.h" +#elif SAM4CM +# include "sam4cm/osc.h" +#elif SAM4CP +# include "sam4cp/osc.h" +#elif SAM4L +# include "sam4l/osc.h" +#elif SAM4N +# include "sam4n/osc.h" +#elif SAMG +# include "samg/osc.h" +#elif SAMV71 +# include "samv71/osc.h" +#elif SAMV70 +# include "samv70/osc.h" +#elif SAME70 +# include "same70/osc.h" +#elif SAMS70 +# include "sams70/osc.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/osc.h" +#elif UC3A3 +# include "uc3a3_a4/osc.h" +#elif UC3B +# include "uc3b0_b1/osc.h" +#elif UC3C +# include "uc3c/osc.h" +#elif UC3D +# include "uc3d/osc.h" +#elif UC3L +# include "uc3l/osc.h" +#elif XMEGA +# include "xmega/osc.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup osc_group Oscillator Management + * + * This group contains functions and definitions related to configuring + * and enabling/disabling on-chip oscillators. Internal RC-oscillators, + * external crystal oscillators and external clock generators are + * supported by this module. What all of these have in common is that + * they swing at a fixed, nominal frequency which is normally not + * adjustable. + * + * \par Example: Enabling an oscillator + * + * The following example demonstrates how to enable the external + * oscillator on XMEGA A and wait for it to be ready to use. The + * oscillator identifiers are platform-specific, so while the same + * procedure is used on all platforms, the parameter to osc_enable() + * will be different from device to device. + * \code + osc_enable(OSC_ID_XOSC); + osc_wait_ready(OSC_ID_XOSC); \endcode + * + * \section osc_group_board Board-specific Definitions + * If external oscillators are used, the board code must provide the + * following definitions for each of those: + * - \b BOARD__HZ: The nominal frequency of the oscillator. + * - \b BOARD__STARTUP_US: The startup time of the + * oscillator in microseconds. + * - \b BOARD__TYPE: The type of oscillator connected, i.e. + * whether it's a crystal or external clock, and sometimes what kind + * of crystal it is. The meaning of this value is platform-specific. + * + * @{ + */ + +//! \name Oscillator Management +//@{ +/** + * \fn void osc_enable(uint8_t id) + * \brief Enable oscillator \a id + * + * The startup time and mode value is automatically determined based on + * definitions in the board code. + */ +/** + * \fn void osc_disable(uint8_t id) + * \brief Disable oscillator \a id + */ +/** + * \fn osc_is_ready(uint8_t id) + * \brief Determine whether oscillator \a id is ready. + * \retval true Oscillator \a id is running and ready to use as a clock + * source. + * \retval false Oscillator \a id is not running. + */ +/** + * \fn uint32_t osc_get_rate(uint8_t id) + * \brief Return the frequency of oscillator \a id in Hz + */ + +#ifndef __ASSEMBLY__ + +/** + * \brief Wait until the oscillator identified by \a id is ready + * + * This function will busy-wait for the oscillator identified by \a id + * to become stable and ready to use as a clock source. + * + * \param id A number identifying the oscillator to wait for. + */ +static inline void osc_wait_ready(uint8_t id) +{ + while (!osc_is_ready(id)) { + /* Do nothing */ + } +} + +#endif /* __ASSEMBLY__ */ + +//@} + +//! @} + +#endif /* OSC_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/pll.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/pll.h new file mode 100644 index 00000000..0a223742 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/pll.h @@ -0,0 +1,331 @@ +/** + * \file + * + * \brief PLL management + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef CLK_PLL_H_INCLUDED +#define CLK_PLL_H_INCLUDED + +#include "parts.h" +#include "conf_clock.h" + +#if SAM3S +# include "sam3s/pll.h" +#elif SAM3XA +# include "sam3x/pll.h" +#elif SAM3U +# include "sam3u/pll.h" +#elif SAM3N +# include "sam3n/pll.h" +#elif SAM4S +# include "sam4s/pll.h" +#elif SAM4E +# include "sam4e/pll.h" +#elif SAM4C +# include "sam4c/pll.h" +#elif SAM4CM +# include "sam4cm/pll.h" +#elif SAM4CP +# include "sam4cp/pll.h" +#elif SAM4L +# include "sam4l/pll.h" +#elif SAM4N +# include "sam4n/pll.h" +#elif SAMG +# include "samg/pll.h" +#elif SAMV71 +# include "samv71/pll.h" +#elif SAMV70 +# include "samv70/pll.h" +#elif SAME70 +# include "same70/pll.h" +#elif SAMS70 +# include "sams70/pll.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/pll.h" +#elif UC3A3 +# include "uc3a3_a4/pll.h" +#elif UC3B +# include "uc3b0_b1/pll.h" +#elif UC3C +# include "uc3c/pll.h" +#elif UC3D +# include "uc3d/pll.h" +#elif (UC3L0128 || UC3L0256 || UC3L3_L4) +# include "uc3l/pll.h" +#elif XMEGA +# include "xmega/pll.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup pll_group PLL Management + * + * This group contains functions and definitions related to configuring + * and enabling/disabling on-chip PLLs. A PLL will take an input signal + * (the \em source), optionally divide the frequency by a configurable + * \em divider, and then multiply the frequency by a configurable \em + * multiplier. + * + * Some devices don't support input dividers; specifying any other + * divisor than 1 on these devices will result in an assertion failure. + * Other devices may have various restrictions to the frequency range of + * the input and output signals. + * + * \par Example: Setting up PLL0 with default parameters + * + * The following example shows how to configure and enable PLL0 using + * the default parameters specified using the configuration symbols + * listed above. + * \code + pll_enable_config_defaults(0); \endcode + * + * To configure, enable PLL0 using the default parameters and to disable + * a specific feature like Wide Bandwidth Mode (a UC3A3-specific + * PLL option.), you can use this initialization process. + * \code + struct pll_config pllcfg; + if (pll_is_locked(pll_id)) { + return; // Pll already running + } + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); \endcode + * + * When the last function call returns, PLL0 is ready to be used as the + * main system clock source. + * + * \section pll_group_config Configuration Symbols + * + * Each PLL has a set of default parameters determined by the following + * configuration symbols in the application's configuration file: + * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the + * input of PLL \a n. Must be one of the values defined by the + * #pll_source enum. + * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL + * \a n. + * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n. + * + * These configuration symbols determine the result of calling + * pll_config_defaults() and pll_get_default_rate(). + * + * @{ + */ + +//! \name Chip-specific PLL characteristics +//@{ +/** + * \def PLL_MAX_STARTUP_CYCLES + * \brief Maximum PLL startup time in number of slow clock cycles + */ +/** + * \def NR_PLLS + * \brief Number of on-chip PLLs + */ + +/** + * \def PLL_MIN_HZ + * \brief Minimum frequency that the PLL can generate + */ +/** + * \def PLL_MAX_HZ + * \brief Maximum frequency that the PLL can generate + */ +/** + * \def PLL_NR_OPTIONS + * \brief Number of PLL option bits + */ +//@} + +/** + * \enum pll_source + * \brief PLL clock source + */ + +//! \name PLL configuration +//@{ + +/** + * \struct pll_config + * \brief Hardware-specific representation of PLL configuration. + * + * This structure contains one or more device-specific values + * representing the current PLL configuration. The contents of this + * structure is typically different from platform to platform, and the + * user should not access any fields except through the PLL + * configuration API. + */ + +/** + * \fn void pll_config_init(struct pll_config *cfg, + * enum pll_source src, unsigned int div, unsigned int mul) + * \brief Initialize PLL configuration from standard parameters. + * + * \note This function may be defined inline because it is assumed to be + * called very few times, and usually with constant parameters. Inlining + * it will in such cases reduce the code size significantly. + * + * \param cfg The PLL configuration to be initialized. + * \param src The oscillator to be used as input to the PLL. + * \param div PLL input divider. + * \param mul PLL loop divider (i.e. multiplier). + * + * \return A configuration which will make the PLL run at + * (\a mul / \a div) times the frequency of \a src + */ +/** + * \def pll_config_defaults(cfg, pll_id) + * \brief Initialize PLL configuration using default parameters. + * + * After this function returns, \a cfg will contain a configuration + * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) + * times the frequency of CONFIG_PLLx_SOURCE. + * + * \param cfg The PLL configuration to be initialized. + * \param pll_id Use defaults for this PLL. + */ +/** + * \def pll_get_default_rate(pll_id) + * \brief Get the default rate in Hz of \a pll_id + */ +/** + * \fn void pll_config_set_option(struct pll_config *cfg, + * unsigned int option) + * \brief Set the PLL option bit \a option in the configuration \a cfg. + * + * \param cfg The PLL configuration to be changed. + * \param option The PLL option bit to be set. + */ +/** + * \fn void pll_config_clear_option(struct pll_config *cfg, + * unsigned int option) + * \brief Clear the PLL option bit \a option in the configuration \a cfg. + * + * \param cfg The PLL configuration to be changed. + * \param option The PLL option bit to be cleared. + */ +/** + * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id) + * \brief Read the currently active configuration of \a pll_id. + * + * \param cfg The configuration object into which to store the currently + * active configuration. + * \param pll_id The ID of the PLL to be accessed. + */ +/** + * \fn void pll_config_write(const struct pll_config *cfg, + * unsigned int pll_id) + * \brief Activate the configuration \a cfg on \a pll_id + * + * \param cfg The configuration object representing the PLL + * configuration to be activated. + * \param pll_id The ID of the PLL to be updated. + */ + +//@} + +//! \name Interaction with the PLL hardware +//@{ +/** + * \fn void pll_enable(const struct pll_config *cfg, + * unsigned int pll_id) + * \brief Activate the configuration \a cfg and enable PLL \a pll_id. + * + * \param cfg The PLL configuration to be activated. + * \param pll_id The ID of the PLL to be enabled. + */ +/** + * \fn void pll_disable(unsigned int pll_id) + * \brief Disable the PLL identified by \a pll_id. + * + * After this function is called, the PLL identified by \a pll_id will + * be disabled. The PLL configuration stored in hardware may be affected + * by this, so if the caller needs to restore the same configuration + * later, it should either do a pll_config_read() before disabling the + * PLL, or remember the last configuration written to the PLL. + * + * \param pll_id The ID of the PLL to be disabled. + */ +/** + * \fn bool pll_is_locked(unsigned int pll_id) + * \brief Determine whether the PLL is locked or not. + * + * \param pll_id The ID of the PLL to check. + * + * \retval true The PLL is locked and ready to use as a clock source + * \retval false The PLL is not yet locked, or has not been enabled. + */ +/** + * \fn void pll_enable_source(enum pll_source src) + * \brief Enable the source of the pll. + * The source is enabled, if the source is not already running. + * + * \param src The ID of the PLL source to enable. + */ +/** + * \fn void pll_enable_config_defaults(unsigned int pll_id) + * \brief Enable the pll with the default configuration. + * PLL is enabled, if the PLL is not already locked. + * + * \param pll_id The ID of the PLL to enable. + */ + +/** + * \brief Wait for PLL \a pll_id to become locked + * + * \todo Use a timeout to avoid waiting forever and hanging the system + * + * \param pll_id The ID of the PLL to wait for. + * + * \retval STATUS_OK The PLL is now locked. + * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked. + */ +static inline int pll_wait_for_lock(unsigned int pll_id) +{ + Assert(pll_id < NR_PLLS); + + while (!pll_is_locked(pll_id)) { + /* Do nothing */ + } + + return 0; +} + +//@} +//! @} + +#endif /* CLK_PLL_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/genclk.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/genclk.h new file mode 100644 index 00000000..0739a1de --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/genclk.h @@ -0,0 +1,320 @@ +/** + * \file + * + * \brief Chip-specific generic clock management. + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CHIP_GENCLK_H_INCLUDED +#define CHIP_GENCLK_H_INCLUDED + +#include +#include +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup genclk_group + * @{ + */ + +//! \name Programmable Clock Identifiers (PCK) +//@{ +#define GENCLK_PCK_0 0 //!< PCK0 ID +#define GENCLK_PCK_1 1 //!< PCK1 ID +#define GENCLK_PCK_2 2 //!< PCK2 ID +//@} + +//! \name Programmable Clock Sources (PCK) +//@{ + +enum genclk_source { + GENCLK_PCK_SRC_SLCK_RC = 0,//!< Internal 32kHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_SLCK_XTAL = 1,//!< External 32kHz crystal oscillator as PCK source clock + GENCLK_PCK_SRC_SLCK_BYPASS = 2,//!< External 32kHz bypass oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_4M_RC = 3,//!< Internal 4MHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_8M_RC = 4,//!< Internal 8MHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_12M_RC = 5,//!< Internal 12MHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_XTAL = 6,//!< External crystal oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_BYPASS = 7,//!< External bypass oscillator as PCK source clock + GENCLK_PCK_SRC_PLLACK = 8,//!< Use PLLACK as PCK source clock + GENCLK_PCK_SRC_MCK = 9,//!< Use Master Clk as PCK source clock +}; + +//@} + +//! \name Programmable Clock Prescalers (PCK) +//@{ + +enum genclk_divider { + GENCLK_PCK_PRES_1 = PMC_PCK_PRES(0), //!< Set PCK clock prescaler to 1 + GENCLK_PCK_PRES_2 = PMC_PCK_PRES(1), //!< Set PCK clock prescaler to 2 + GENCLK_PCK_PRES_4 = PMC_PCK_PRES(2), //!< Set PCK clock prescaler to 4 + GENCLK_PCK_PRES_8 = PMC_PCK_PRES(3), //!< Set PCK clock prescaler to 8 + GENCLK_PCK_PRES_16 = PMC_PCK_PRES(4), //!< Set PCK clock prescaler to 16 + GENCLK_PCK_PRES_32 = PMC_PCK_PRES(5), //!< Set PCK clock prescaler to 32 + GENCLK_PCK_PRES_64 = PMC_PCK_PRES(6), //!< Set PCK clock prescaler to 64 +}; + +//@} + +struct genclk_config { + uint32_t ctrl; +}; + +static inline void genclk_config_defaults(struct genclk_config *p_cfg, + uint32_t ul_id) +{ + ul_id = ul_id; + p_cfg->ctrl = 0; +} + +static inline void genclk_config_read(struct genclk_config *p_cfg, + uint32_t ul_id) +{ + p_cfg->ctrl = PMC->PMC_PCK[ul_id]; +} + +static inline void genclk_config_write(const struct genclk_config *p_cfg, + uint32_t ul_id) +{ + PMC->PMC_PCK[ul_id] = p_cfg->ctrl; +} + +//! \name Programmable Clock Source and Prescaler configuration +//@{ + +static inline void genclk_config_set_source(struct genclk_config *p_cfg, + enum genclk_source e_src) +{ + p_cfg->ctrl &= (~PMC_PCK_CSS_Msk); + + switch (e_src) { + case GENCLK_PCK_SRC_SLCK_RC: + case GENCLK_PCK_SRC_SLCK_XTAL: + case GENCLK_PCK_SRC_SLCK_BYPASS: + p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK); + break; + + case GENCLK_PCK_SRC_MAINCK_4M_RC: + case GENCLK_PCK_SRC_MAINCK_8M_RC: + case GENCLK_PCK_SRC_MAINCK_12M_RC: + case GENCLK_PCK_SRC_MAINCK_XTAL: + case GENCLK_PCK_SRC_MAINCK_BYPASS: + p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK); + break; + + case GENCLK_PCK_SRC_PLLACK: + p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK); + break; + + case GENCLK_PCK_SRC_MCK: + p_cfg->ctrl |= (PMC_PCK_CSS_MCK); + break; + + default: + break; + } +} + +static inline void genclk_config_set_divider(struct genclk_config *p_cfg, + uint32_t e_divider) +{ + p_cfg->ctrl &= ~PMC_PCK_PRES_Msk; + p_cfg->ctrl |= e_divider; +} + +//@} + +static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id) +{ + PMC->PMC_PCK[ul_id] = p_cfg->ctrl; + pmc_enable_pck(ul_id); +} + +static inline void genclk_disable(uint32_t ul_id) +{ + pmc_disable_pck(ul_id); +} + +static inline void genclk_enable_source(enum genclk_source e_src) +{ + switch (e_src) { + case GENCLK_PCK_SRC_SLCK_RC: + if (!osc_is_ready(OSC_SLCK_32K_RC)) { + osc_enable(OSC_SLCK_32K_RC); + osc_wait_ready(OSC_SLCK_32K_RC); + } + break; + + case GENCLK_PCK_SRC_SLCK_XTAL: + if (!osc_is_ready(OSC_SLCK_32K_XTAL)) { + osc_enable(OSC_SLCK_32K_XTAL); + osc_wait_ready(OSC_SLCK_32K_XTAL); + } + break; + + case GENCLK_PCK_SRC_SLCK_BYPASS: + if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) { + osc_enable(OSC_SLCK_32K_BYPASS); + osc_wait_ready(OSC_SLCK_32K_BYPASS); + } + break; + + case GENCLK_PCK_SRC_MAINCK_4M_RC: + if (!osc_is_ready(OSC_MAINCK_4M_RC)) { + osc_enable(OSC_MAINCK_4M_RC); + osc_wait_ready(OSC_MAINCK_4M_RC); + } + break; + + case GENCLK_PCK_SRC_MAINCK_8M_RC: + if (!osc_is_ready(OSC_MAINCK_8M_RC)) { + osc_enable(OSC_MAINCK_8M_RC); + osc_wait_ready(OSC_MAINCK_8M_RC); + } + break; + + case GENCLK_PCK_SRC_MAINCK_12M_RC: + if (!osc_is_ready(OSC_MAINCK_12M_RC)) { + osc_enable(OSC_MAINCK_12M_RC); + osc_wait_ready(OSC_MAINCK_12M_RC); + } + break; + + case GENCLK_PCK_SRC_MAINCK_XTAL: + if (!osc_is_ready(OSC_MAINCK_XTAL)) { + osc_enable(OSC_MAINCK_XTAL); + osc_wait_ready(OSC_MAINCK_XTAL); + } + break; + + case GENCLK_PCK_SRC_MAINCK_BYPASS: + if (!osc_is_ready(OSC_MAINCK_BYPASS)) { + osc_enable(OSC_MAINCK_BYPASS); + osc_wait_ready(OSC_MAINCK_BYPASS); + } + break; + +#ifdef CONFIG_PLL0_SOURCE + case GENCLK_PCK_SRC_PLLACK: + pll_enable_config_defaults(0); + break; +#endif + + case GENCLK_PCK_SRC_MCK: + break; + + default: + Assert(false); + break; + } +} + +//! \name Retrieves the current rate in Hz of the Programmable Clock Source +//@{ +static inline uint32_t genclk_get_frequency_hz(uint32_t ul_id) +{ + uint32_t pck_source,clock_config; + uint32_t pck_freq = 0; + pck_source = (PMC->PMC_PCK[ul_id] & PMC_PCK_CSS_Msk) >> PMC_PCK_CSS_Pos; + switch(pck_source) + { + case PMC_PCK_CSS_SLOW_CLK: + if (pmc_get_slck_config()) + pck_freq = OSC_SLCK_32K_RC_HZ; + else + pck_freq = OSC_SLCK_32K_XTAL_HZ; + break; + case PMC_PCK_CSS_MAIN_CLK: + case PMC_PCK_CSS_PLLA_CLK: + clock_config = pmc_get_mainck_config(); + if (clock_config & CKGR_MOR_MOSCSEL) + { + switch(clock_config & CKGR_MOR_MOSCRCF_Msk) + { + case CKGR_MOR_MOSCRCF_4_MHz: + pck_freq = OSC_MAINCK_4M_RC_HZ; + break; + case CKGR_MOR_MOSCRCF_8_MHz: + pck_freq = OSC_MAINCK_8M_RC_HZ; + break; + case CKGR_MOR_MOSCRCF_12_MHz: + pck_freq = OSC_MAINCK_12M_RC_HZ; + break; + } + } + else + { + pck_freq = OSC_MAINCK_XTAL_HZ; + } + + if (pck_source == PMC_PCK_CSS_PLLA_CLK) + { + clock_config = pmc_get_pllack_config(); + if ((clock_config & CKGR_PLLAR_DIVA_Msk) == 0) + return 0; + pck_freq *= ((((clock_config & CKGR_PLLAR_MULA_Msk)>>CKGR_PLLAR_MULA_Pos) + 1)/(clock_config & CKGR_PLLAR_DIVA_Msk)); + } + break; + case PMC_PCK_CSS_UPLL_CLK: + pck_freq = pmc_get_upllckdiv_config() ? PLL_UPLL_HZ/2: PLL_UPLL_HZ; + break; + case PMC_PCK_CSS_MCK: + pck_freq = sysclk_get_main_hz(); + break; + default: + break; + } + pck_freq /= ((PMC->PMC_PCK[ul_id] & PMC_PCK_PRES_Msk) >> PMC_PCK_PRES_Pos)+1; + return pck_freq; +} +//! @} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_GENCLK_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/osc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/osc.h new file mode 100644 index 00000000..fe98a2cb --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/osc.h @@ -0,0 +1,237 @@ +/** + * \file + * + * \brief Chip-specific oscillator management functions. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CHIP_OSC_H_INCLUDED +#define CHIP_OSC_H_INCLUDED + +#include "board.h" +#include "pmc.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/* + * Below BOARD_XXX macros are related to the specific board, and + * should be defined by the board code, otherwise default value are used. + */ +#if !defined(BOARD_FREQ_SLCK_XTAL) +# warning The board slow clock xtal frequency has not been defined. +# define BOARD_FREQ_SLCK_XTAL (32768UL) +#endif + +#if !defined(BOARD_FREQ_SLCK_BYPASS) +# warning The board slow clock bypass frequency has not been defined. +# define BOARD_FREQ_SLCK_BYPASS (32768UL) +#endif + +#if !defined(BOARD_FREQ_MAINCK_XTAL) +# warning The board main clock xtal frequency has not been defined. +# define BOARD_FREQ_MAINCK_XTAL (12000000UL) +#endif + +#if !defined(BOARD_FREQ_MAINCK_BYPASS) +# warning The board main clock bypass frequency has not been defined. +# define BOARD_FREQ_MAINCK_BYPASS (12000000UL) +#endif + +#if !defined(BOARD_OSC_STARTUP_US) +# warning The board main clock xtal startup time has not been defined. +# define BOARD_OSC_STARTUP_US (15625UL) +#endif + +/** + * \weakgroup osc_group + * @{ + */ + +//! \name Oscillator identifiers +//@{ +#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator. +#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator. +#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator. +#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator. +#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator. +#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator. +#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator. +#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator. +//@} + +//! \name Oscillator clock speed in hertz +//@{ +#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator. +#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator. +#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator. +#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator. +#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator. +#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator. +#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator. +#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator. +//@} + +static inline void osc_enable(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + break; + + case OSC_SLCK_32K_XTAL: + pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); + break; + + case OSC_SLCK_32K_BYPASS: + pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS); + break; + + + case OSC_MAINCK_4M_RC: + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + break; + + case OSC_MAINCK_8M_RC: + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); + break; + + case OSC_MAINCK_12M_RC: + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + break; + + + case OSC_MAINCK_XTAL: + pmc_switch_mainck_to_xtal(PMC_OSC_XTAL, + pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, + OSC_SLCK_32K_RC_HZ)); + break; + + case OSC_MAINCK_BYPASS: + pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS, + pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, + OSC_SLCK_32K_RC_HZ)); + break; + } +} + +static inline void osc_disable(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + case OSC_SLCK_32K_XTAL: + case OSC_SLCK_32K_BYPASS: + break; + + case OSC_MAINCK_4M_RC: + case OSC_MAINCK_8M_RC: + case OSC_MAINCK_12M_RC: + pmc_osc_disable_fastrc(); + break; + + case OSC_MAINCK_XTAL: + pmc_osc_disable_xtal(PMC_OSC_XTAL); + break; + + case OSC_MAINCK_BYPASS: + pmc_osc_disable_xtal(PMC_OSC_BYPASS); + break; + } +} + +static inline bool osc_is_ready(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + return 1; + + case OSC_SLCK_32K_XTAL: + case OSC_SLCK_32K_BYPASS: + return pmc_osc_is_ready_32kxtal(); + + case OSC_MAINCK_4M_RC: + case OSC_MAINCK_8M_RC: + case OSC_MAINCK_12M_RC: + case OSC_MAINCK_XTAL: + case OSC_MAINCK_BYPASS: + return pmc_osc_is_ready_mainck(); + } + + return 0; +} + +static inline uint32_t osc_get_rate(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + return OSC_SLCK_32K_RC_HZ; + + case OSC_SLCK_32K_XTAL: + return BOARD_FREQ_SLCK_XTAL; + + case OSC_SLCK_32K_BYPASS: + return BOARD_FREQ_SLCK_BYPASS; + + case OSC_MAINCK_4M_RC: + return OSC_MAINCK_4M_RC_HZ; + + case OSC_MAINCK_8M_RC: + return OSC_MAINCK_8M_RC_HZ; + + case OSC_MAINCK_12M_RC: + return OSC_MAINCK_12M_RC_HZ; + + case OSC_MAINCK_XTAL: + return BOARD_FREQ_MAINCK_XTAL; + + case OSC_MAINCK_BYPASS: + return BOARD_FREQ_MAINCK_BYPASS; + } + + return 0; +} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_OSC_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/pll.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/pll.h new file mode 100644 index 00000000..e7c732e6 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/pll.h @@ -0,0 +1,259 @@ +/** + * \file + * + * \brief Chip-specific PLL definitions. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CHIP_PLL_H_INCLUDED +#define CHIP_PLL_H_INCLUDED + +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup pll_group + * @{ + */ + +#define PLL_OUTPUT_MIN_HZ 160000000 +#define PLL_OUTPUT_MAX_HZ 500000000 + +#define PLL_INPUT_MIN_HZ 3000000 +#define PLL_INPUT_MAX_HZ 32000000 + +#define NR_PLLS 2 +#define PLLA_ID 0 +#define UPLL_ID 1 //!< USB UTMI PLL. + +#define PLL_UPLL_HZ 480000000 + +#define PLL_COUNT 0x3fU + +enum pll_source { + PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, //!< Internal 4MHz RC oscillator. + PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, //!< Internal 8MHz RC oscillator. + PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, //!< Internal 12MHz RC oscillator. + PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, //!< External crystal oscillator. + PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, //!< External bypass oscillator. + PLL_NR_SOURCES, //!< Number of PLL sources. +}; + +struct pll_config { + uint32_t ctrl; +}; + +#define pll_get_default_rate(pll_id) \ + ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \ + * CONFIG_PLL##pll_id##_MUL) \ + / CONFIG_PLL##pll_id##_DIV) + +/* Force UTMI PLL parameters (Hardware defined) */ +#ifdef CONFIG_PLL1_SOURCE +# undef CONFIG_PLL1_SOURCE +#endif +#ifdef CONFIG_PLL1_MUL +# undef CONFIG_PLL1_MUL +#endif +#ifdef CONFIG_PLL1_DIV +# undef CONFIG_PLL1_DIV +#endif +#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL +#define CONFIG_PLL1_MUL 0 +#define CONFIG_PLL1_DIV 0 + +/** + * \note The SAMV71 PLL hardware interprets mul as mul+1. For readability the + * hardware mul+1 is hidden in this implementation. Use mul as mul effective + * value. + */ +static inline void pll_config_init(struct pll_config *p_cfg, + enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul) +{ + uint32_t vco_hz; + + Assert(e_src < PLL_NR_SOURCES); + + if (ul_div == 0 && ul_mul == 0) { /* Must only be true for UTMI PLL */ + p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT); + } else { /* PLLA */ + /* Calculate internal VCO frequency */ + vco_hz = osc_get_rate(e_src) / ul_div; + Assert(vco_hz >= PLL_INPUT_MIN_HZ); + Assert(vco_hz <= PLL_INPUT_MAX_HZ); + + vco_hz *= ul_mul; + Assert(vco_hz >= PLL_OUTPUT_MIN_HZ); + Assert(vco_hz <= PLL_OUTPUT_MAX_HZ); + + /* PMC hardware will automatically make it mul+1 */ + p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_DIVA(ul_div) \ + | CKGR_PLLAR_PLLACOUNT(PLL_COUNT); + } +} + +#define pll_config_defaults(cfg, pll_id) \ + pll_config_init(cfg, \ + CONFIG_PLL##pll_id##_SOURCE, \ + CONFIG_PLL##pll_id##_DIV, \ + CONFIG_PLL##pll_id##_MUL) + +static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + p_cfg->ctrl = PMC->CKGR_PLLAR; + } else { + p_cfg->ctrl = PMC->CKGR_UCKR; + } +} + +static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + pmc_disable_pllack(); // Always stop PLL first! + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl; + } else { + PMC->CKGR_UCKR = p_cfg->ctrl; + } +} + +static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + pmc_disable_pllack(); // Always stop PLL first! + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl; + } else { + PMC->CKGR_UCKR = p_cfg->ctrl | CKGR_UCKR_UPLLEN; + } +} + +/** + * \note This will only disable the selected PLL, not the underlying oscillator (mainck). + */ +static inline void pll_disable(uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + pmc_disable_pllack(); + } else { + PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; + } +} + +static inline uint32_t pll_is_locked(uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + return pmc_is_locked_pllack(); + } else { + return pmc_is_locked_upll(); + } +} + +static inline void pll_enable_source(enum pll_source e_src) +{ + switch (e_src) { + case PLL_SRC_MAINCK_4M_RC: + case PLL_SRC_MAINCK_8M_RC: + case PLL_SRC_MAINCK_12M_RC: + case PLL_SRC_MAINCK_XTAL: + case PLL_SRC_MAINCK_BYPASS: + osc_enable(e_src); + osc_wait_ready(e_src); + break; + + default: + Assert(false); + break; + } +} + +static inline void pll_enable_config_defaults(unsigned int ul_pll_id) +{ + struct pll_config pllcfg; + + if (pll_is_locked(ul_pll_id)) { + return; // Pll already running + } + switch (ul_pll_id) { +#ifdef CONFIG_PLL0_SOURCE + case 0: + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_init(&pllcfg, + CONFIG_PLL0_SOURCE, + CONFIG_PLL0_DIV, + CONFIG_PLL0_MUL); + break; +#endif +#ifdef CONFIG_PLL1_SOURCE + case 1: + pll_enable_source(CONFIG_PLL1_SOURCE); + pll_config_init(&pllcfg, + CONFIG_PLL1_SOURCE, + CONFIG_PLL1_DIV, + CONFIG_PLL1_MUL); + break; +#endif + default: + Assert(false); + break; + } + pll_enable(&pllcfg, ul_pll_id); + while (!pll_is_locked(ul_pll_id)); +} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_PLL_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/sysclk.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/sysclk.c new file mode 100644 index 00000000..5a5dc015 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/sysclk.c @@ -0,0 +1,258 @@ +/** + * \file + * + * \brief Chip-specific system clock management functions. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup sysclk_group + * @{ + */ + +#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) +/** + * \brief boolean signalling that the sysclk_init is done. + */ +uint32_t sysclk_initialized = 0; +#endif + +/** + * \brief Set system clock prescaler configuration + * + * This function will change the system clock prescaler configuration to + * match the parameters. + * + * \note The parameters to this function are device-specific. + * + * \param ul_pres The CPU clock will be divided by \f$2^{mck\_pres}\f$ + */ +void sysclk_set_prescalers(uint32_t ul_pres) +{ + pmc_mck_set_prescaler(ul_pres); + SystemCoreClockUpdate(); +} + +/** + * \brief Change the source of the main system clock. + * + * \param ul_src The new system clock source. Must be one of the constants + * from the System Clock Sources section. + */ +void sysclk_set_source(uint32_t ul_src) +{ + switch (ul_src) { + case SYSCLK_SRC_SLCK_RC: + case SYSCLK_SRC_SLCK_XTAL: + case SYSCLK_SRC_SLCK_BYPASS: + pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK); + break; + + case SYSCLK_SRC_MAINCK_4M_RC: + case SYSCLK_SRC_MAINCK_8M_RC: + case SYSCLK_SRC_MAINCK_12M_RC: + case SYSCLK_SRC_MAINCK_XTAL: + case SYSCLK_SRC_MAINCK_BYPASS: + pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK); + break; + + case SYSCLK_SRC_PLLACK: + pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK); + break; + + case SYSCLK_SRC_UPLLCK: + pmc_mck_set_source(PMC_MCKR_CSS_UPLL_CLK); + break; + } + + SystemCoreClockUpdate(); +} + +#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__) +/** + * \brief Enable USB clock. + * + * \note The SAMV71 UDP hardware interprets div as div+1. For readability the hardware div+1 + * is hidden in this implementation. Use div as div effective value. + * + * \param pll_id Source of the USB clock. + * \param div Actual clock divisor. Must be superior to 0. + */ +void sysclk_enable_usb(void) +{ + Assert(CONFIG_USBCLK_DIV > 0); + +#ifdef CONFIG_PLL0_SOURCE + if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) { + struct pll_config pllcfg; + + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); + pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1); + pmc_enable_udpck(); + return; + } +#endif + + if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_UPLL) { + + pmc_enable_upll_clock(); + pmc_switch_udpck_to_upllck(CONFIG_USBCLK_DIV - 1); + pmc_enable_udpck(); + return; + } +} + +/** + * \brief Disable the USB clock. + * + * \note This implementation does not switch off the PLL, it just turns off the USB clock. + */ +void sysclk_disable_usb(void) +{ + pmc_disable_udpck(); +} +#endif // CONFIG_USBCLK_SOURCE + +void sysclk_init(void) +{ + struct pll_config pllcfg; + + /* Set flash wait state to max in case the below clock switching. */ + system_init_flash(CHIP_FREQ_CPU_MAX/2); + + /* Config system clock setting */ + if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { + osc_enable(OSC_SLCK_32K_RC); + osc_wait_ready(OSC_SLCK_32K_RC); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { + osc_enable(OSC_SLCK_32K_XTAL); + osc_wait_ready(OSC_SLCK_32K_XTAL); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { + osc_enable(OSC_SLCK_32K_BYPASS); + osc_wait_ready(OSC_SLCK_32K_BYPASS); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) { + /* Already running from SYSCLK_SRC_MAINCK_4M_RC */ + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { + osc_enable(OSC_MAINCK_8M_RC); + osc_wait_ready(OSC_MAINCK_8M_RC); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) { + osc_enable(OSC_MAINCK_12M_RC); + osc_wait_ready(OSC_MAINCK_12M_RC); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { + osc_enable(OSC_MAINCK_XTAL); + osc_wait_ready(OSC_MAINCK_XTAL); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { + osc_enable(OSC_MAINCK_BYPASS); + osc_wait_ready(OSC_MAINCK_BYPASS); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + +#ifdef CONFIG_PLL0_SOURCE + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES); + } +#endif + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) { + pll_enable_source(CONFIG_PLL1_SOURCE); + pll_config_defaults(&pllcfg, 1); + pll_enable(&pllcfg, 1); + pll_wait_for_lock(1); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_upllck(CONFIG_SYSCLK_PRES); + } + /* Update the SystemFrequency variable */ + SystemCoreClockUpdate(); + + /* Set a flash wait state depending on the master clock frequency */ + system_init_flash(sysclk_get_cpu_hz() / CONFIG_SYSCLK_DIV); + +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) + /* Signal that the internal frequencies are setup */ + sysclk_initialized = 1; +#endif +} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/sysclk.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/sysclk.h new file mode 100644 index 00000000..1abb28ca --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/sysclk.h @@ -0,0 +1,463 @@ +/** + * \file + * + * \brief Chip-specific system clock management functions. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CHIP_SYSCLK_H_INCLUDED +#define CHIP_SYSCLK_H_INCLUDED + +#include +#include + +/** + * \page sysclk_quickstart Quick Start Guide for the System Clock Management + * service (SAMV71) + * + * This is the quick start guide for the \ref sysclk_group "System Clock + * Management" service, with step-by-step instructions on how to configure and + * use the service for specific use cases. + * + * \section sysclk_quickstart_usecases System Clock Management use cases + * - \ref sysclk_quickstart_basic + * - \ref sysclk_quickstart_use_case_2 + * + * \section sysclk_quickstart_basic Basic usage of the System Clock Management + * service + * This section will present a basic use case for the System Clock Management + * service. This use case will configure the main system clock to 120MHz, + * using an internal PLL module to multiply the frequency of a crystal attached + * to the microcontroller. + * + * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites + * - None + * + * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code + * Add to the application initialization code: + * \code + sysclk_init(); +\endcode + * + * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow + * -# Configure the system clocks according to the settings in conf_clock.h: + * \code sysclk_init(); \endcode + * + * \subsection sysclk_quickstart_use_case_1_example_code Example code + * Add or uncomment the following in your conf_clock.h header file, + * commenting out all other definitions of the same symbol(s): + * \code + #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK + + // Fpll0 = (Fclk * PLL_mul) / PLL_div + #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL + #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL) + #define CONFIG_PLL0_DIV 1 + + // Fbus = Fsys / BUS_div + #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +\endcode + * + * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow + * -# Configure the main system clock to use the output of the PLL module as + * its source: + * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode + * -# Configure the PLL module to use the fast external fast crystal + * oscillator as its source: + * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode + * -# Configure the PLL module to multiply the external fast crystal + * oscillator frequency up to 120MHz: + * \code + #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL) + #define CONFIG_PLL0_DIV 1 +\endcode + * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the + * board \c conf_board.h configuration + * file as the frequency of the fast crystal attached to the microcontroller. + * -# Configure the main clock to run at the full 120MHz, disable scaling of + * the main system clock speed: + * \code + #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +\endcode + * \note Some dividers are powers of two, while others are integer division + * factors. Refer to the formulas in the conf_clock.h template commented + * above each division define. + */ + +/** + * \page sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock + * Management (SAMV71) + * + * \section sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus + * Clock Management + * This section will present a more advanced use case for the System Clock + * Management service. This use case will configure the main system clock to + * 96MHz, using an internal PLL module to multiply the frequency of a crystal + * attached to the microcontroller. The USB clock will be configured via the + * same PLL module. + * + * \subsection sysclk_quickstart_use_case_2_prereq Prerequisites + * - None + * + * \subsection sysclk_quickstart_use_case_2_setup_steps Initialization code + * Add to the application initialization code: + * \code + sysclk_init(); +\endcode + * + * \subsection sysclk_quickstart_use_case_2_setup_steps_workflow Workflow + * -# Configure the system clocks according to the settings in conf_clock.h: + * \code sysclk_init(); \endcode + * + * \subsection sysclk_quickstart_use_case_2_example_code Example code + * Add or uncomment the following in your conf_clock.h header file, + * commenting out all other definitions of the same symbol(s): + * \code + #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK + + // Fpll0 = (Fclk * PLL_mul) / PLL_div + #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL + #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL) + #define CONFIG_PLL0_DIV 1 + + // Fbus = Fsys / BUS_div + #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 + + // Fusb = Fsys / USB_div + #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 + #define CONFIG_USBCLK_DIV 2 +\endcode + * + * \subsection sysclk_quickstart_use_case_2_example_workflow Workflow + * -# Configure the main system clock to use the output of the PLL0 module as + * its source: + * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode + * -# Configure the PLL0 module to use the fast external fast crystal + * oscillator as its source: + * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode + * -# Configure the PLL0 module to multiply the external fast crystal + * oscillator frequency up to 96MHz: + * \code + #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL) + #define CONFIG_PLL0_DIV 1 +\endcode + * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the + * board \c conf_board.h configuration file as the frequency of the fast + * crystal attached to the microcontroller. + * -# Configure the main clock to run at the full 96MHz, disable scaling of + * the main system clock speed: + * \code + #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +\endcode + * \note Some dividers are powers of two, while others are integer division + * factors. Refer to the formulas in the conf_clock.h template commented + * above each division define. + * -# Configure the USB module clock to use the output of the PLL0 module as + * its source with division 2: + * \code + #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 + #define CONFIG_USBCLK_DIV 2 +\endcode + */ + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup sysclk_group + * @{ + */ + +//! \name Configuration Symbols +//@{ +/** + * \def CONFIG_SYSCLK_SOURCE + * \brief Initial/static main system clock source + * + * The main system clock will be configured to use this clock during + * initialization. + */ +#ifndef CONFIG_SYSCLK_SOURCE +# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC +#endif +/** + * \def CONFIG_SYSCLK_PRES + * \brief Initial CPU clock divider (mck) + * + * The MCK will run at + * \f[ + * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz} + * \f] + * after initialization. + */ +#ifndef CONFIG_SYSCLK_PRES +# define CONFIG_SYSCLK_PRES 0 +#endif + +//@} + +//! \name Master Clock Sources (MCK) +//@{ +#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock +#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock +#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock +#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock +#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock +#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock +#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock +#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock +#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock +#define SYSCLK_SRC_UPLLCK 9 //!< Use UPLLCK as master source clock +//@} + +//! \name Master Clock Prescalers (MCK) +//@{ +#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1 +#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2 +#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4 +#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8 +#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16 +#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32 +#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64 +#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3 +//@} + +//! \name Master Clock Division (MCK) +//@{ +#define SYSCLK_DIV_1 PMC_MCKR_MDIV_EQ_PCK //!< Set master clock division to 1 +#define SYSCLK_DIV_2 PMC_MCKR_MDIV_PCK_DIV2 //!< Set master clock division to 2 +#define SYSCLK_DIV_4 PMC_MCKR_MDIV_PCK_DIV4 //!< Set master clock division to 4 +#define SYSCLK_DIV_3 PMC_MCKR_MDIV_PCK_DIV3 //!< Set master clock division to 3 +//@} + +//! \name USB Clock Sources +//@{ +#define USBCLK_SRC_PLL0 0 //!< Use PLLA +#define USBCLK_SRC_UPLL 1 //!< Use UPLL +//@} + +/** + * \def CONFIG_USBCLK_SOURCE + * \brief Configuration symbol for the USB generic clock source + * + * Sets the clock source to use for the USB. The source must also be properly + * configured. + * + * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if + * USB is not required. + */ +#ifdef __DOXYGEN__ +# define CONFIG_USBCLK_SOURCE +#endif + +/** + * \def CONFIG_USBCLK_DIV + * \brief Configuration symbol for the USB generic clock divider setting + * + * Sets the clock division for the USB generic clock. If a USB clock source is + * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be + * defined. + */ +#ifdef __DOXYGEN__ +# define CONFIG_USBCLK_DIV +#endif + +/** + * \name Querying the system clock + * + * The following functions may be used to query the current frequency of + * the system clock and the CPU and bus clocks derived from it. + * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be + * available on all platforms, although some platforms may define + * additional accessors for various chip-internal bus clocks. These are + * usually not intended to be queried directly by generic code. + */ +//@{ + +/** + * \brief Return the current rate in Hz of the main system clock + * + * \todo This function assumes that the main clock source never changes + * once it's been set up, and that PLL0 always runs at the compile-time + * configured default rate. While this is probably the most common + * configuration, which we want to support as a special case for + * performance reasons, we will at some point need to support more + * dynamic setups as well. + */ +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) +extern uint32_t sysclk_initialized; +#endif +static inline uint32_t sysclk_get_main_hz(void) +{ +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) + if (!sysclk_initialized ) { + return OSC_MAINCK_4M_RC_HZ; + } +#endif + + /* Config system clock setting */ + if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { + return OSC_SLCK_32K_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { + return OSC_SLCK_32K_XTAL_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { + return OSC_SLCK_32K_BYPASS_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) { + return OSC_MAINCK_4M_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { + return OSC_MAINCK_8M_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) { + return OSC_MAINCK_12M_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { + return OSC_MAINCK_XTAL_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { + return OSC_MAINCK_BYPASS_HZ; + } +#ifdef CONFIG_PLL0_SOURCE + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { + return pll_get_default_rate(0); + } +#endif + +#ifdef CONFIG_PLL1_SOURCE + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) { + return PLL_UPLL_HZ; + } +#endif + else { + /* unhandled_case(CONFIG_SYSCLK_SOURCE); */ + return 0; + } +} + +/** + * \brief Return the current rate in Hz of the CPU clock + * + * \todo This function assumes that the CPU always runs at the system + * clock frequency. We want to support at least two more scenarios: + * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus + * clock dividers (which may change at run time). Ditto for all the bus + * clocks. + * + * \return Frequency of the CPU clock, in Hz. + */ +static inline uint32_t sysclk_get_cpu_hz(void) +{ + /* CONFIG_SYSCLK_PRES is the register value for setting the expected */ + /* prescaler, not an immediate value. */ + return sysclk_get_main_hz() / + ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : + (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))); +} + +/** + * \brief Retrieves the current rate in Hz of the peripheral clocks. + * + * \return Frequency of the peripheral clocks, in Hz. + */ +static inline uint32_t sysclk_get_peripheral_hz(void) +{ + /* CONFIG_SYSCLK_PRES is the register value for setting the expected */ + /* prescaler, not an immediate value. */ + return sysclk_get_main_hz() / + (((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))) * CONFIG_SYSCLK_DIV); +} + +/** + * \brief Retrieves the current rate in Hz of the Peripheral Bus clock attached + * to the specified peripheral. + * + * \param module Pointer to the module's base address. + * + * \return Frequency of the bus attached to the specified peripheral, in Hz. + */ +static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module) +{ + UNUSED(module); + return sysclk_get_peripheral_hz(); +} +//@} + +//! \name Enabling and disabling synchronous clocks +//@{ + +/** + * \brief Enable a peripheral's clock. + * + * \param ul_id Id (number) of the peripheral clock. + */ +static inline void sysclk_enable_peripheral_clock(uint32_t ul_id) +{ + pmc_enable_periph_clk(ul_id); +} + +/** + * \brief Disable a peripheral's clock. + * + * \param ul_id Id (number) of the peripheral clock. + */ +static inline void sysclk_disable_peripheral_clock(uint32_t ul_id) +{ + pmc_disable_periph_clk(ul_id); +} + +//@} + +//! \name System Clock Source and Prescaler configuration +//@{ + +extern void sysclk_set_prescalers(uint32_t ul_pres); +extern void sysclk_set_source(uint32_t ul_src); + +//@} + +extern void sysclk_enable_usb(void); +extern void sysclk_disable_usb(void); + +extern void sysclk_init(void); + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_SYSCLK_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/sysclk.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/sysclk.h new file mode 100644 index 00000000..fda18ec4 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/clock/sysclk.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief System clock management + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef SYSCLK_H_INCLUDED +#define SYSCLK_H_INCLUDED + +#include "parts.h" +#include "conf_clock.h" + +#if SAM3S +# include "sam3s/sysclk.h" +#elif SAM3U +# include "sam3u/sysclk.h" +#elif SAM3N +# include "sam3n/sysclk.h" +#elif SAM3XA +# include "sam3x/sysclk.h" +#elif SAM4S +# include "sam4s/sysclk.h" +#elif SAM4E +# include "sam4e/sysclk.h" +#elif SAM4C +# include "sam4c/sysclk.h" +#elif SAM4CM +# include "sam4cm/sysclk.h" +#elif SAM4CP +# include "sam4cp/sysclk.h" +#elif SAM4L +# include "sam4l/sysclk.h" +#elif SAM4N +# include "sam4n/sysclk.h" +#elif SAMG +# include "samg/sysclk.h" +#elif SAMV71 +# include "samv71/sysclk.h" +#elif SAMV70 +# include "samv70/sysclk.h" +#elif SAME70 +# include "same70/sysclk.h" +#elif SAMS70 +# include "sams70/sysclk.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/sysclk.h" +#elif UC3A3 +# include "uc3a3_a4/sysclk.h" +#elif UC3B +# include "uc3b0_b1/sysclk.h" +#elif UC3C +# include "uc3c/sysclk.h" +#elif UC3D +# include "uc3d/sysclk.h" +#elif UC3L +# include "uc3l/sysclk.h" +#elif XMEGA +# include "xmega/sysclk.h" +#elif MEGA +# include "mega/sysclk.h" +#else +# error Unsupported chip type +#endif + +/** + * \defgroup clk_group Clock Management + */ + +/** + * \ingroup clk_group + * \defgroup sysclk_group System Clock Management + * + * See \ref sysclk_quickstart. + * + * The sysclk API covers the system clock and all + * clocks derived from it. The system clock is a chip-internal clock on + * which all synchronous clocks, i.e. CPU and bus/peripheral + * clocks, are based. The system clock is typically generated from one + * of a variety of sources, which may include crystal and RC oscillators + * as well as PLLs. The clocks derived from the system clock are + * sometimes also known as synchronous clocks, since they + * always run synchronously with respect to each other, as opposed to + * generic clocks which may run from different oscillators or + * PLLs. + * + * Most applications should simply call sysclk_init() to initialize + * everything related to the system clock and its source (oscillator, + * PLL or DFLL), and leave it at that. More advanced applications, and + * platform-specific drivers, may require additional services from the + * clock system, some of which may be platform-specific. + * + * \section sysclk_group_platform Platform Dependencies + * + * The sysclk API is partially chip- or platform-specific. While all + * platforms provide mostly the same functionality, there are some + * variations around how different bus types and clock tree structures + * are handled. + * + * The following functions are available on all platforms with the same + * parameters and functionality. These functions may be called freely by + * portable applications, drivers and services: + * - sysclk_init() + * - sysclk_set_source() + * - sysclk_get_main_hz() + * - sysclk_get_cpu_hz() + * - sysclk_get_peripheral_bus_hz() + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behavior. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - sysclk_enable_peripheral_clock() + * - sysclk_disable_peripheral_clock() + * - sysclk_enable_module() + * - sysclk_disable_module() + * - sysclk_module_is_enabled() + * - sysclk_set_prescalers() + * + * All other functions should be considered platform-specific. + * Enabling/disabling clocks to specific peripherals as well as + * determining the speed of these clocks should be done by calling + * functions provided by the driver for that peripheral. + * + * @{ + */ + +//! \name System Clock Initialization +//@{ +/** + * \fn void sysclk_init(void) + * \brief Initialize the synchronous clock system. + * + * This function will initialize the system clock and its source. This + * includes: + * - Mask all synchronous clocks except for any clocks which are + * essential for normal operation (for example internal memory + * clocks). + * - Set up the system clock prescalers as specified by the + * application's configuration file. + * - Enable the clock source specified by the application's + * configuration file (oscillator or PLL) and wait for it to become + * stable. + * - Set the main system clock source to the clock specified by the + * application's configuration file. + * + * Since all non-essential peripheral clocks are initially disabled, it + * is the responsibility of the peripheral driver to re-enable any + * clocks that are needed for normal operation. + */ +//@} + +//! @} + +#endif /* SYSCLK_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/gpio/gpio.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/gpio/gpio.h new file mode 100644 index 00000000..cb9ef97a --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/gpio/gpio.h @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief Common GPIO API. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include + +#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +# include "sam_gpio/sam_gpio.h" +#elif XMEGA +# include "xmega_gpio/xmega_gpio.h" +#elif MEGA || MEGA_RF +# include "mega_gpio/mega_gpio.h" +#else +# error Unsupported chip type +#endif + +/** + * \defgroup gpio_group General Purpose Input/Output + * + * This is the common API for GPIO. Additional features are available + * in the documentation of the specific modules. + * + * \section io_group_platform Platform Dependencies + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behaviour. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - gpio_pin_is_low() + * - gpio_pin_is_high() + * - gpio_set_pin_high() + * - gpio_set_pin_group_high() + * - gpio_set_pin_low() + * - gpio_set_pin_group_low() + * - gpio_toggle_pin() + * - gpio_toggle_pin_group() + * - gpio_configure_pin() + * - gpio_configure_group() + */ + +#endif /* _GPIO_H_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/gpio/sam_gpio/sam_gpio.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/gpio/sam_gpio/sam_gpio.h new file mode 100644 index 00000000..27d7489c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/gpio/sam_gpio/sam_gpio.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief GPIO service for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef SAM_GPIO_H_INCLUDED +#define SAM_GPIO_H_INCLUDED + +#include "compiler.h" +#include "pio.h" + +#define gpio_pin_is_low(io_id) \ + (pio_get_pin_value(io_id) ? 0 : 1) + +#define gpio_pin_is_high(io_id) \ + (pio_get_pin_value(io_id) ? 1 : 0) + +#define gpio_set_pin_high(io_id) \ + pio_set_pin_high(io_id) + +#define gpio_set_pin_low(io_id) \ + pio_set_pin_low(io_id) + +#define gpio_toggle_pin(io_id) \ + pio_toggle_pin(io_id) + +#define gpio_configure_pin(io_id,io_flags) \ + pio_configure_pin(io_id,io_flags) + +#define gpio_configure_group(port_id,port_mask,io_flags) \ + pio_configure_pin_group(port_id,port_mask,io_flags) + +#define gpio_set_pin_group_high(port_id,mask) \ + pio_set_pin_group_high(port_id,mask) + +#define gpio_set_pin_group_low(port_id,mask) \ + pio_set_pin_group_low(port_id,mask) + +#define gpio_toggle_pin_group(port_id,mask) \ + pio_toggle_pin_group(port_id,mask) + +#endif /* SAM_GPIO_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/ioport/ioport.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/ioport/ioport.h new file mode 100644 index 00000000..d392457c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/ioport/ioport.h @@ -0,0 +1,538 @@ +/** + * \file + * + * \brief Common IOPORT service main header file for AVR, UC3 and ARM + * architectures. + * + * Copyright (c) 2012-2020 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef IOPORT_H +#define IOPORT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * \defgroup ioport_group Common IOPORT API + * + * See \ref ioport_quickstart. + * + * This is common IOPORT service for GPIO pin configuration and control in a + * standardized manner across the MEGA, MEGA_RF, XMEGA, UC3 and ARM devices. + * + * Port pin control code is optimized for each platform, and should produce + * both compact and fast execution times when used with constant values. + * + * \section dependencies Dependencies + * This driver depends on the following modules: + * - \ref sysclk_group for clock speed and functions. + * @{ + */ + +/** + * \def IOPORT_CREATE_PIN(port, pin) + * \brief Create IOPORT pin number + * + * Create a IOPORT pin number for use with the IOPORT functions. + * + * \param port IOPORT port (e.g. PORTA, PA or PIOA depending on chosen + * architecture) + * \param pin IOPORT zero-based index of the I/O pin + */ + +/** \brief IOPORT pin directions */ +enum ioport_direction { + IOPORT_DIR_INPUT, /*!< IOPORT input direction */ + IOPORT_DIR_OUTPUT, /*!< IOPORT output direction */ +}; + +/** \brief IOPORT levels */ +enum ioport_value { + IOPORT_PIN_LEVEL_LOW, /*!< IOPORT pin value low */ + IOPORT_PIN_LEVEL_HIGH, /*!< IOPORT pin value high */ +}; + +#if MEGA_RF +/** \brief IOPORT edge sense modes */ +enum ioport_sense { + IOPORT_SENSE_LEVEL, /*!< IOPORT sense low level */ + IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ + IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ + IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ +}; +#elif SAM && !SAM4L +/** \brief IOPORT edge sense modes */ +enum ioport_sense { + IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ + IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ + IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ + IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */ + IOPORT_SENSE_LEVEL_HIGH,/*!< IOPORT sense High level */ +}; +#elif XMEGA +enum ioport_sense { + IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ + IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ + IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ + IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */ +}; +#else +enum ioport_sense { + IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ + IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ + IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ +}; +#endif + + +#if XMEGA +# include "xmega/ioport.h" +# if defined(IOPORT_XMEGA_COMPAT) +# include "xmega/ioport_compat.h" +# endif +#elif MEGA +# include "mega/ioport.h" +#elif UC3 +# include "uc3/ioport.h" +#elif SAM +# if SAM4L +# include "sam/ioport_gpio.h" +# elif (SAMD20 | SAMD21 | SAML21| SAMR34 |SAMR35 | WLR089) +# include "sam0/ioport.h" +# else +# include "sam/ioport_pio.h" +# endif +#endif + +/** + * \brief Initializes the IOPORT service, ready for use. + * + * This function must be called before using any other functions in the IOPORT + * service. + */ +static inline void ioport_init(void) +{ + arch_ioport_init(); +} + +/** + * \brief Enable an IOPORT pin, based on a pin created with \ref + * IOPORT_CREATE_PIN(). + * + * \param pin IOPORT pin to enable + */ +static inline void ioport_enable_pin(ioport_pin_t pin) +{ + arch_ioport_enable_pin(pin); +} + +/** + * \brief Enable multiple pins in a single IOPORT port. + * + * \param port IOPORT port to enable + * \param mask Mask of pins within the port to enable + */ +static inline void ioport_enable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_enable_port(port, mask); +} + +/** + * \brief Disable IOPORT pin, based on a pin created with \ref + * IOPORT_CREATE_PIN(). + * + * \param pin IOPORT pin to disable + */ +static inline void ioport_disable_pin(ioport_pin_t pin) +{ + arch_ioport_disable_pin(pin); +} + +/** + * \brief Disable multiple pins in a single IOPORT port. + * + * \param port IOPORT port to disable + * \param mask Pin mask of pins to disable + */ +static inline void ioport_disable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_disable_port(port, mask); +} + +/** + * \brief Set multiple pin modes in a single IOPORT port, such as pull-up, + * pull-down, etc. configuration. + * + * \param port IOPORT port to configure + * \param mask Pin mask of pins to configure + * \param mode Mode masks to configure for the specified pins (\ref + * ioport_modes) + */ +static inline void ioport_set_port_mode(ioport_port_t port, + ioport_port_mask_t mask, ioport_mode_t mode) +{ + arch_ioport_set_port_mode(port, mask, mode); +} + +/** + * \brief Set pin mode for one single IOPORT pin. + * + * \param pin IOPORT pin to configure + * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) + */ +static inline void ioport_set_pin_mode(ioport_pin_t pin, ioport_mode_t mode) +{ + arch_ioport_set_pin_mode(pin, mode); +} + +/** + * \brief Reset multiple pin modes in a specified IOPORT port to defaults. + * + * \param port IOPORT port to configure + * \param mask Mask of pins whose mode configuration is to be reset + */ +static inline void ioport_reset_port_mode(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_set_port_mode(port, mask, 0); +} + +/** + * \brief Reset pin mode configuration for a single IOPORT pin + * + * \param pin IOPORT pin to configure + */ +static inline void ioport_reset_pin_mode(ioport_pin_t pin) +{ + arch_ioport_set_pin_mode(pin, 0); +} + +/** + * \brief Set I/O direction for a group of pins in a single IOPORT. + * + * \param port IOPORT port to configure + * \param mask Pin mask of pins to configure + * \param dir Direction to set for the specified pins (\ref ioport_direction) + */ +static inline void ioport_set_port_dir(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_direction dir) +{ + arch_ioport_set_port_dir(port, mask, dir); +} + +/** + * \brief Set direction for a single IOPORT pin. + * + * \param pin IOPORT pin to configure + * \param dir Direction to set for the specified pin (\ref ioport_direction) + */ +static inline void ioport_set_pin_dir(ioport_pin_t pin, + enum ioport_direction dir) +{ + arch_ioport_set_pin_dir(pin, dir); +} + +/** + * \brief Set an IOPORT pin to a specified logical value. + * + * \param pin IOPORT pin to configure + * \param level Logical value of the pin + */ +static inline void ioport_set_pin_level(ioport_pin_t pin, bool level) +{ + arch_ioport_set_pin_level(pin, level); +} + +/** + * \brief Set a group of IOPORT pins in a single port to a specified logical + * value. + * + * \param port IOPORT port to write to + * \param mask Pin mask of pins to modify + * \param level Level of the pins to be modified + */ +static inline void ioport_set_port_level(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_value level) +{ + arch_ioport_set_port_level(port, mask, level); +} + +/** + * \brief Get current value of an IOPORT pin, which has been configured as an + * input. + * + * \param pin IOPORT pin to read + * \return Current logical value of the specified pin + */ +static inline bool ioport_get_pin_level(ioport_pin_t pin) +{ + return arch_ioport_get_pin_level(pin); +} + +/** + * \brief Get current value of several IOPORT pins in a single port, which have + * been configured as an inputs. + * + * \param port IOPORT port to read + * \param mask Pin mask of pins to read + * \return Logical levels of the specified pins from the read port, returned as + * a mask. + */ +static inline ioport_port_mask_t ioport_get_port_level(ioport_pin_t port, + ioport_port_mask_t mask) +{ + return arch_ioport_get_port_level(port, mask); +} + +/** + * \brief Toggle the value of an IOPORT pin, which has previously configured as + * an output. + * + * \param pin IOPORT pin to toggle + */ +static inline void ioport_toggle_pin_level(ioport_pin_t pin) +{ + arch_ioport_toggle_pin_level(pin); +} + +/** + * \brief Toggle the values of several IOPORT pins located in a single port. + * + * \param port IOPORT port to modify + * \param mask Pin mask of pins to toggle + */ +static inline void ioport_toggle_port_level(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_toggle_port_level(port, mask); +} + +/** + * \brief Set the pin sense mode of a single IOPORT pin. + * + * \param pin IOPORT pin to configure + * \param pin_sense Edge to sense for the pin (\ref ioport_sense) + */ +static inline void ioport_set_pin_sense_mode(ioport_pin_t pin, + enum ioport_sense pin_sense) +{ + arch_ioport_set_pin_sense_mode(pin, pin_sense); +} + +/** + * \brief Set the pin sense mode of a multiple IOPORT pins on a single port. + * + * \param port IOPORT port to configure + * \param mask Bitmask if pins whose edge sense is to be configured + * \param pin_sense Edge to sense for the pins (\ref ioport_sense) + */ +static inline void ioport_set_port_sense_mode(ioport_port_t port, + ioport_port_mask_t mask, + enum ioport_sense pin_sense) +{ + arch_ioport_set_port_sense_mode(port, mask, pin_sense); +} + +/** + * \brief Convert a pin ID into a its port ID. + * + * \param pin IOPORT pin ID to convert + * \retval Port ID for the given pin ID + */ +static inline ioport_port_t ioport_pin_to_port_id(ioport_pin_t pin) +{ + return arch_ioport_pin_to_port_id(pin); +} + +/** + * \brief Convert a pin ID into a bitmask mask for the given pin on its port. + * + * \param pin IOPORT pin ID to convert + * \retval Bitmask with a bit set that corresponds to the given pin ID in its port + */ +static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin) +{ + return arch_ioport_pin_to_mask(pin); +} + +/** @} */ + +/** + * \page ioport_quickstart Quick start guide for the common IOPORT service + * + * This is the quick start guide for the \ref ioport_group, with + * step-by-step instructions on how to configure and use the service in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section ioport_quickstart_basic Basic use case + * In this use case we will configure one IO pin for button input and one for + * LED control. Then it will read the button state and output it on the LED. + * + * \section ioport_quickstart_basic_setup Setup steps + * + * \subsection ioport_quickstart_basic_setup_code Example code + * \code + #define MY_LED IOPORT_CREATE_PIN(PORTA, 5) + #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6) + + ioport_init(); + + ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); + ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); + ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); +\endcode + * + * \subsection ioport_quickstart_basic_setup_flow Workflow + * -# It's useful to give the GPIOs symbolic names and this can be done with + * the \ref IOPORT_CREATE_PIN macro. We define one for a LED and one for a + * button. + * - \code + #define MY_LED IOPORT_CREATE_PIN(PORTA, 5) + #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6) +\endcode + * - \note The usefulness of the \ref IOPORT_CREATE_PIN macro and port names + * differ between architectures: + * - MEGA, MEGA_RF and XMEGA: Use \ref IOPORT_CREATE_PIN macro with port definitions + * PORTA, PORTB ... + * - UC3: Most convenient to pick up the device header file pin definition + * and us it directly. E.g.: AVR32_PIN_PB06 + * - SAM: Most convenient to pick up the device header file pin definition + * and us it directly. E.g.: PIO_PA5_IDX
+ * \ref IOPORT_CREATE_PIN can also be used with port definitions + * PIOA, PIOB ... + * -# Initialize the ioport service. This typically enables the IO module if + * needed. + * - \code ioport_init(); \endcode + * -# Set the LED GPIO as output: + * - \code ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); \endcode + * -# Set the button GPIO as input: + * - \code ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); \endcode + * -# Enable pull-up for the button GPIO: + * - \code ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); \endcode + * + * \section ioport_quickstart_basic_usage Usage steps + * + * \subsection ioport_quickstart_basic_usage_code Example code + * \code + bool value; + + value = ioport_get_pin_level(MY_BUTTON); + ioport_set_pin_level(MY_LED, value); +\endcode + * + * \subsection ioport_quickstart_basic_usage_flow Workflow + * -# Define a boolean variable for state storage: + * - \code bool value; \endcode + * -# Read out the button level into variable value: + * - \code value = ioport_get_pin_level(MY_BUTTON); \endcode + * -# Set the LED to read out value from the button: + * - \code ioport_set_pin_level(MY_LED, value); \endcode + * + * \section ioport_quickstart_advanced Advanced use cases + * - \subpage ioport_quickstart_use_case_1 : Port access + */ + +/** + * \page ioport_quickstart_use_case_1 Advanced use case doing port access + * + * In this case we will read out the pins from one whole port and write the + * read value to another port. + * + * \section ioport_quickstart_use_case_1_setup Setup steps + * + * \subsection ioport_quickstart_use_case_1_setup_code Example code + * \code + #define IN_PORT IOPORT_PORTA + #define OUT_PORT IOPORT_PORTB + #define MASK 0x00000060 + + ioport_init(); + + ioport_set_port_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); + ioport_set_port_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); +\endcode + * + * \subsection ioport_quickstart_basic_setup_flow Workflow + * -# It's useful to give the ports symbolic names: + * - \code + #define IN_PORT IOPORT_PORTA + #define OUT_PORT IOPORT_PORTB +\endcode + * - \note The port names differ between architectures: + * - MEGA_RF, MEGA and XMEGA: There are predefined names for ports: IOPORT_PORTA, + * IOPORT_PORTB ... + * - UC3: Use the index value of the different IO blocks: 0, 1 ... + * - SAM: There are predefined names for ports: IOPORT_PIOA, IOPORT_PIOB + * ... + * -# Also useful to define a mask for the bits to work with: + * - \code #define MASK 0x00000060 \endcode + * -# Initialize the ioport service. This typically enables the IO module if + * needed. + * - \code ioport_init(); \endcode + * -# Set one of the ports as input: + * - \code ioport_set_pin_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); \endcode + * -# Set the other port as output: + * - \code ioport_set_pin_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); \endcode + * + * \section ioport_quickstart_basic_usage Usage steps + * + * \subsection ioport_quickstart_basic_usage_code Example code + * \code + ioport_port_mask_t value; + + value = ioport_get_port_level(IN_PORT, MASK); + ioport_set_port_level(OUT_PORT, MASK, value); +\endcode + * + * \subsection ioport_quickstart_basic_usage_flow Workflow + * -# Define a variable for port date storage: + * - \code ioport_port_mask_t value; \endcode + * -# Read out from one port: + * - \code value = ioport_get_port_level(IN_PORT, MASK); \endcode + * -# Put the read data out on the other port: + * - \code ioport_set_port_level(OUT_PORT, MASK, value); \endcode + */ + +#ifdef __cplusplus +} +#endif + +#endif /* IOPORT_H */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/ioport/sam/ioport_pio.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/ioport/sam/ioport_pio.h new file mode 100644 index 00000000..76b4d066 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/ioport/sam/ioport_pio.h @@ -0,0 +1,373 @@ +/** + * \file + * + * \brief SAM architecture specific IOPORT service implementation header file. + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef IOPORT_SAM_H +#define IOPORT_SAM_H + +#include + +#define IOPORT_CREATE_PIN(port, pin) ((IOPORT_ ## port) * 32 + (pin)) +#define IOPORT_BASE_ADDRESS (uintptr_t)PIOA +#define IOPORT_PIO_OFFSET ((uintptr_t)PIOB - (uintptr_t)PIOA) + +#define IOPORT_PIOA 0 +#define IOPORT_PIOB 1 +#define IOPORT_PIOC 2 +#define IOPORT_PIOD 3 +#define IOPORT_PIOE 4 +#define IOPORT_PIOF 5 + +/** + * \weakgroup ioport_group + * \section ioport_modes IOPORT Modes + * + * For details on these please see the SAM Manual. + * + * @{ + */ + +/** \name IOPORT Mode bit definitions */ +/** @{ */ +#define IOPORT_MODE_MUX_MASK (0x7 << 0) /*!< MUX bits mask */ +#define IOPORT_MODE_MUX_BIT0 ( 1 << 0) /*!< MUX BIT0 mask */ + +#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 +#define IOPORT_MODE_MUX_BIT1 ( 1 << 1) /*!< MUX BIT1 mask */ +#endif + +#define IOPORT_MODE_MUX_A ( 0 << 0) /*!< MUX function A */ +#define IOPORT_MODE_MUX_B ( 1 << 0) /*!< MUX function B */ + +#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 +#define IOPORT_MODE_MUX_C ( 2 << 0) /*!< MUX function C */ +#define IOPORT_MODE_MUX_D ( 3 << 0) /*!< MUX function D */ +#endif + +#define IOPORT_MODE_PULLUP ( 1 << 3) /*!< Pull-up */ + +#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 +#define IOPORT_MODE_PULLDOWN ( 1 << 4) /*!< Pull-down */ +#endif + +#define IOPORT_MODE_OPEN_DRAIN ( 1 << 5) /*!< Open drain */ + +#define IOPORT_MODE_GLITCH_FILTER ( 1 << 6) /*!< Glitch filter */ +#define IOPORT_MODE_DEBOUNCE ( 1 << 7) /*!< Input debounce */ +/** @} */ + +/** @} */ + +typedef uint32_t ioport_mode_t; +typedef uint32_t ioport_pin_t; +typedef uint32_t ioport_port_t; +typedef uint32_t ioport_port_mask_t; + +__always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin) +{ + return pin >> 5; +} + +__always_inline static Pio *arch_ioport_port_to_base(ioport_port_t port) +{ +#if (SAM4C || SAM4CM || SAM4CP) + if (port == IOPORT_PIOC) { + return (Pio *)(uintptr_t)PIOC; +# ifdef ID_PIOD + } else if (port == IOPORT_PIOD) { + return (Pio *)(uintptr_t)PIOD; +# endif + } else { + return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS + + (IOPORT_PIO_OFFSET * port)); + } +#else + return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS + + (IOPORT_PIO_OFFSET * port)); +#endif +} + +__always_inline static Pio *arch_ioport_pin_to_base(ioport_pin_t pin) +{ + return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin)); +} + +__always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin) +{ + return 1U << (pin & 0x1F); +} + +__always_inline static void arch_ioport_init(void) +{ +#ifdef ID_PIOA + sysclk_enable_peripheral_clock(ID_PIOA); +#endif +#ifdef ID_PIOB + sysclk_enable_peripheral_clock(ID_PIOB); +#endif +#ifdef ID_PIOC + sysclk_enable_peripheral_clock(ID_PIOC); +#endif +#ifdef ID_PIOD + sysclk_enable_peripheral_clock(ID_PIOD); +#endif +#ifdef ID_PIOE + sysclk_enable_peripheral_clock(ID_PIOE); +#endif +#ifdef ID_PIOF + sysclk_enable_peripheral_clock(ID_PIOF); +#endif +} + +__always_inline static void arch_ioport_enable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_port_to_base(port)->PIO_PER = mask; +} + +__always_inline static void arch_ioport_disable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_port_to_base(port)->PIO_PDR = mask; +} + +__always_inline static void arch_ioport_enable_pin(ioport_pin_t pin) +{ + arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin)); +} + +__always_inline static void arch_ioport_disable_pin(ioport_pin_t pin) +{ + arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin)); +} + +__always_inline static void arch_ioport_set_port_mode(ioport_port_t port, + ioport_port_mask_t mask, ioport_mode_t mode) +{ + Pio *base = arch_ioport_port_to_base(port); + + if (mode & IOPORT_MODE_PULLUP) { + base->PIO_PUER = mask; + } else { + base->PIO_PUDR = mask; + } + +#if defined(IOPORT_MODE_PULLDOWN) + if (mode & IOPORT_MODE_PULLDOWN) { + base->PIO_PPDER = mask; + } else { + base->PIO_PPDDR = mask; + } +#endif + + if (mode & IOPORT_MODE_OPEN_DRAIN) { + base->PIO_MDER = mask; + } else { + base->PIO_MDDR = mask; + } + + if (mode & (IOPORT_MODE_GLITCH_FILTER | IOPORT_MODE_DEBOUNCE)) { + base->PIO_IFER = mask; + } else { + base->PIO_IFDR = mask; + } + + if (mode & IOPORT_MODE_DEBOUNCE) { +#if SAM3U || SAM3XA + base->PIO_DIFSR = mask; +#else + base->PIO_IFSCER = mask; +#endif + } else { +#if SAM3U || SAM3XA + base->PIO_SCIFSR = mask; +#else + base->PIO_IFSCDR = mask; +#endif + } + +#if !defined(IOPORT_MODE_MUX_BIT1) + if (mode & IOPORT_MODE_MUX_BIT0) { + base->PIO_ABSR |= mask; + } else { + base->PIO_ABSR &= ~mask; + } +#else + if (mode & IOPORT_MODE_MUX_BIT0) { + base->PIO_ABCDSR[0] |= mask; + } else { + base->PIO_ABCDSR[0] &= ~mask; + } + + if (mode & IOPORT_MODE_MUX_BIT1) { + base->PIO_ABCDSR[1] |= mask; + } else { + base->PIO_ABCDSR[1] &= ~mask; + } +#endif +} + +__always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin, + ioport_mode_t mode) +{ + arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin), mode); +} + +__always_inline static void arch_ioport_set_port_dir(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_direction group_direction) +{ + Pio *base = arch_ioport_port_to_base(port); + + if (group_direction == IOPORT_DIR_OUTPUT) { + base->PIO_OER = mask; + } else if (group_direction == IOPORT_DIR_INPUT) { + base->PIO_ODR = mask; + } + + base->PIO_OWER = mask; +} + +__always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin, + enum ioport_direction dir) +{ + Pio *base = arch_ioport_pin_to_base(pin); + + if (dir == IOPORT_DIR_OUTPUT) { + base->PIO_OER = arch_ioport_pin_to_mask(pin); + } else if (dir == IOPORT_DIR_INPUT) { + base->PIO_ODR = arch_ioport_pin_to_mask(pin); + } + + base->PIO_OWER = arch_ioport_pin_to_mask(pin); +} + +__always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin, + bool level) +{ + Pio *base = arch_ioport_pin_to_base(pin); + + if (level) { + base->PIO_SODR = arch_ioport_pin_to_mask(pin); + } else { + base->PIO_CODR = arch_ioport_pin_to_mask(pin); + } +} + +__always_inline static void arch_ioport_set_port_level(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_value level) +{ + Pio *base = arch_ioport_port_to_base(port); + + if (level){ + base->PIO_SODR = mask; + } else { + base->PIO_CODR = mask; + } +} + +__always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin) +{ + return arch_ioport_pin_to_base(pin)->PIO_PDSR & arch_ioport_pin_to_mask(pin); +} + +__always_inline static ioport_port_mask_t arch_ioport_get_port_level( + ioport_port_t port, ioport_port_mask_t mask) +{ + return arch_ioport_port_to_base(port)->PIO_PDSR & mask; +} + +__always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin) +{ + Pio *port = arch_ioport_pin_to_base(pin); + ioport_port_mask_t mask = arch_ioport_pin_to_mask(pin); + + if (port->PIO_PDSR & arch_ioport_pin_to_mask(pin)) { + port->PIO_CODR = mask; + } else { + port->PIO_SODR = mask; + } +} + +__always_inline static void arch_ioport_toggle_port_level(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_port_to_base(port)->PIO_ODSR ^= mask; +} + +__always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_sense pin_sense) +{ + Pio *base = arch_ioport_port_to_base(port); + /* AIMMR ELSR FRLHSR + * 0 X X IOPORT_SENSE_BOTHEDGES (Default) + * 1 0 0 IOPORT_SENSE_FALLING + * 1 0 1 IOPORT_SENSE_RISING + * 1 1 0 IOPORT_SENSE_LEVEL_LOW + * 1 1 1 IOPORT_SENSE_LEVEL_HIGH + */ + switch(pin_sense) { + case IOPORT_SENSE_LEVEL_LOW: + base->PIO_LSR = mask; + base->PIO_FELLSR = mask; + break; + case IOPORT_SENSE_LEVEL_HIGH: + base->PIO_LSR = mask; + base->PIO_REHLSR = mask; + break; + case IOPORT_SENSE_FALLING: + base->PIO_ESR = mask; + base->PIO_FELLSR = mask; + break; + case IOPORT_SENSE_RISING: + base->PIO_ESR = mask; + base->PIO_REHLSR = mask; + break; + default: + base->PIO_AIMDR = mask; + return; + } + base->PIO_AIMER = mask; +} + +__always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin, + enum ioport_sense pin_sense) +{ + arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin), pin_sense); +} + +#endif /* IOPORT_SAM_H */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/serial/sam_uart/uart_serial.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/serial/sam_uart/uart_serial.h new file mode 100644 index 00000000..fa3fd71e --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/serial/sam_uart/uart_serial.h @@ -0,0 +1,679 @@ +/** + * \file + * + * \brief Uart Serial for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _UART_SERIAL_H_ +#define _UART_SERIAL_H_ + +#include "compiler.h" +#include "sysclk.h" +#if (SAMG55) +#include "flexcom.h" +#endif +#if ((!SAM4L) && (!SAMG55)) +#include "uart.h" +#endif +#include "usart.h" + +/** + * \name Serial Management Configuration + */ +//! @{ +#include "conf_uart_serial.h" + +//! @} + +/** Input parameters when initializing RS232 and similar modes. */ +typedef struct uart_rs232_options { + /** Set baud rate of the USART (unused in slave modes). */ + uint32_t baudrate; + + /** Number of bits to transmit as a character (5-bit to 9-bit). */ + uint32_t charlength; + + /** + * Parity type: USART_PMODE_DISABLED_gc, USART_PMODE_EVEN_gc, + * USART_PMODE_ODD_gc. + */ + uint32_t paritytype; + + /** 1, 1.5 or 2 stop bits. */ + uint32_t stopbits; + +} usart_rs232_options_t; + +typedef usart_rs232_options_t usart_serial_options_t; + +typedef Usart *usart_if; + +/** + * \brief Initializes the Usart in master mode. + * + * \param p_usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see + * \ref usart_options_t). + */ +static inline void usart_serial_init(usart_if p_usart, + usart_serial_options_t *opt) +{ +#if ((!SAM4L) && (!SAMG55)) + sam_uart_opt_t uart_settings; + uart_settings.ul_mck = sysclk_get_peripheral_hz(); + uart_settings.ul_baudrate = opt->baudrate; + uart_settings.ul_mode = opt->paritytype; +#endif + + sam_usart_opt_t usart_settings; + usart_settings.baudrate = opt->baudrate; + usart_settings.char_length = opt->charlength; + usart_settings.parity_type = opt->paritytype; + usart_settings.stop_bits= opt->stopbits; + usart_settings.channel_mode= US_MR_CHMODE_NORMAL; + +#ifdef UART + if (UART == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART0); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART1); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART2); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART3); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +# ifdef UART4 + if (UART4 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART4); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { +#if (!SAM4L) + sysclk_enable_peripheral_clock(ID_USART); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +#else +# ifdef USART0 + if (USART0 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM0); + flexcom_set_opmode(FLEXCOM0, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART0); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM1); + flexcom_set_opmode(FLEXCOM1, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART1); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM2); + flexcom_set_opmode(FLEXCOM2, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART2); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM3); + flexcom_set_opmode(FLEXCOM3, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART3); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM4); + flexcom_set_opmode(FLEXCOM4, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART4); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM5); + flexcom_set_opmode(FLEXCOM5, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART5); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM6); + flexcom_set_opmode(FLEXCOM6, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART6); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM7); + flexcom_set_opmode(FLEXCOM7, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART7); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif + +#endif /* ifdef USART */ + +} + +/** + * \brief Sends a character with the USART. + * + * \param p_usart Base address of the USART instance. + * \param c Character to write. + * + * \return Status. + * \retval 1 The character was written. + * \retval 0 The function timed out before the USART transmitter became + * ready to send. + */ +static inline int usart_serial_putchar(usart_if p_usart, const uint8_t c) +{ +#ifdef UART + if (UART == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +#else +# ifdef USART0 + if (USART0 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +#endif /* ifdef USART */ + + return 0; +} +/** + * \brief Waits until a character is received, and returns it. + * + * \param p_usart Base address of the USART instance. + * \param data Data to read + * + */ +static inline void usart_serial_getchar(usart_if p_usart, uint8_t *data) +{ + uint32_t val = 0; + + /* Avoid Cppcheck Warning */ + UNUSED(val); + +#ifdef UART + if (UART == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +#else +# ifdef USART0 + if (USART0 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +#endif /* ifdef USART */ + +} + +/** + * \brief Check if Received data is ready. + * + * \param p_usart Base address of the USART instance. + * + * \retval 1 One data has been received. + * \retval 0 No data has been received. + */ +static inline uint32_t usart_serial_is_rx_ready(usart_if p_usart) +{ +#ifdef UART + if (UART == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { + return usart_is_rx_ready(p_usart); + } +#else +# ifdef USART0 + if (USART0 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +#endif /* ifdef USART */ + + return 0; +} + +/** + * \brief Send a sequence of bytes to a USART device + * + * \param usart Base address of the USART instance. + * \param data data buffer to write + * \param len Length of data + * + */ +status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data, + size_t len); + +/** + * \brief Receive a sequence of bytes to a USART device + * + * \param usart Base address of the USART instance. + * \param data data buffer to write + * \param len Length of data + * + */ +status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data, + size_t len); + +#endif /* _UART_SERIAL_H_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/serial/serial.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/serial/serial.h new file mode 100644 index 00000000..21bb1552 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/serial/serial.h @@ -0,0 +1,269 @@ +/** + * \file + * + * \brief Serial Mode management + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef SERIAL_H_INCLUDED +#define SERIAL_H_INCLUDED + +#include +#include "status_codes.h" + +/** + * \typedef usart_if + * + * This type can be used independently to refer to USART module for the + * architecture used. It refers to the correct type definition for the + * architecture, ie. USART_t* for XMEGA or avr32_usart_t* for UC3. + */ + +#if XMEGA +# include "xmega_usart/usart_serial.h" +#elif MEGA_RF +# include "megarf_usart/usart_serial.h" +#elif UC3 +# include "uc3_usart/usart_serial.h" +#elif (SAMB) +#include "samb_uart/uart_serial.h" +#elif (SAM0) +#include "sam0_usart/usart_serial.h" +#elif SAM +# include "sam_uart/uart_serial.h" +#else +# error Unsupported chip type +#endif + +/** + * + * \defgroup serial_group Serial Interface (Serial) + * + * See \ref serial_quickstart. + * + * This is the common API for serial interface. Additional features are available + * in the documentation of the specific modules. + * + * \section serial_group_platform Platform Dependencies + * + * The serial API is partially chip- or platform-specific. While all + * platforms provide mostly the same functionality, there are some + * variations around how different bus types and clock tree structures + * are handled. + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behaviour. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - usart_serial_init() + * - usart_serial_putchar() + * - usart_serial_getchar() + * - usart_serial_write_packet() + * - usart_serial_read_packet() + * + * + * @{ + */ + +//! @} + +/** + * \page serial_quickstart Quick start guide for Serial Interface service + * + * This is the quick start guide for the \ref serial_group "Serial Interface module", with + * step-by-step instructions on how to configure and use the serial in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section serial_use_cases Serial use cases + * - \ref serial_basic_use_case + * - \subpage serial_use_case_1 + * + * \section serial_basic_use_case Basic use case - transmit a character + * In this use case, the serial module is configured for: + * - Using USARTD0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case waits for a received character on the configured USART and + * echoes the character back to the same USART. + * + * \section serial_basic_use_case_setup Setup steps + * + * \subsection serial_basic_use_case_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclk)" + * + * \subsection serial_basic_use_case_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_uart_serial.h file, but it can also be added to your main application file.) + * + * \note The following takes SAM3X configuration for example, other devices have similar + * configuration, but their parameters may be different, refer to corresponding header files. + * + * \code + #define USART_SERIAL &USARTD0 + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT false +\endcode + * + * A variable for the received byte must be added: + * \code uint8_t received_byte; \endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; + + usart_serial_init(USART_SERIAL, &usart_options); +\endcode + * + * \subsection serial_basic_use_case_setup_flow Workflow + * -# Initialize system clock: + * - \code sysclk_init(); \endcode + * -# Create serial USART options struct: + * - \code + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; +\endcode + * -# Initialize the serial service: + * - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode + * + * \section serial_basic_use_case_usage Usage steps + * + * \subsection serial_basic_use_case_usage_code Example code + * Add to application C-file: + * \code + usart_serial_getchar(USART_SERIAL, &received_byte); + usart_serial_putchar(USART_SERIAL, received_byte); +\endcode + * + * \subsection serial_basic_use_case_usage_flow Workflow + * -# Wait for reception of a character: + * - \code usart_serial_getchar(USART_SERIAL, &received_byte); \endcode + * -# Echo the character back: + * - \code usart_serial_putchar(USART_SERIAL, received_byte); \endcode + */ + +/** + * \page serial_use_case_1 Advanced use case - Send a packet of serial data + * + * In this use case, the USART module is configured for: + * - Using USARTD0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case sends a string of text through the USART. + * + * \section serial_use_case_1_setup Setup steps + * + * \subsection serial_use_case_1_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclk)" + * + * \subsection serial_use_case_1_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_uart_serial.h file, but it can also be added to your main application file.): + * + * \note The following takes SAM3X configuration for example, other devices have similar + * configuration, but their parameters may be different, refer to corresponding header files. + * + * \code + #define USART_SERIAL &USARTD0 + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT false +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; + + usart_serial_init(USART_SERIAL, &usart_options); +\endcode + * + * \subsection serial_use_case_1_setup_flow Workflow + * -# Initialize system clock: + * - \code sysclk_init(); \endcode + * -# Create USART options struct: + * - \code + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; +\endcode + * -# Initialize in RS232 mode: + * - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode + * + * \section serial_use_case_1_usage Usage steps + * + * \subsection serial_use_case_1_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); +\endcode + * + * \subsection serial_use_case_1_usage_flow Workflow + * -# Write a string of text to the USART: + * - \code usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); \endcode + */ + +#endif /* SERIAL_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/serial/usart_serial.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/serial/usart_serial.c new file mode 100644 index 00000000..df022e43 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/serial/usart_serial.c @@ -0,0 +1,77 @@ +/** + * + * \file + * + * \brief USART Serial driver functions. + * + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#include "serial.h" + +/** + * \brief Send a sequence of bytes to USART device + * + * \param usart Base address of the USART instance. + * \param data Data buffer to read + * \param len Length of data + * + */ +status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data, + size_t len) +{ + while (len) { + usart_serial_putchar(usart, *data); + len--; + data++; + } + return STATUS_OK; +} + + +/** + * \brief Receive a sequence of bytes from USART device + * + * \param usart Base address of the USART instance. + * \param data Data buffer to write + * \param len Length of data + * + */ +status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data, + size_t len) +{ + while (len) { + usart_serial_getchar(usart, data); + len--; + data++; + } + return STATUS_OK; +} diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sam/sleepmgr.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sam/sleepmgr.c new file mode 100644 index 00000000..f64fe1e5 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sam/sleepmgr.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief SAM3/SAM4 Sleep manager implementation. + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include + +#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) + +uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; + +#endif /* CONFIG_SLEEPMGR_ENABLE */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sam/sleepmgr.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sam/sleepmgr.h new file mode 100644 index 00000000..e32f0ed8 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sam/sleepmgr.h @@ -0,0 +1,111 @@ +/** + * \file + * + * \brief SAM3/SAM4 Sleep manager implementation. + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef SAM_SLEEPMGR_INCLUDED +#define SAM_SLEEPMGR_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +/** + * \weakgroup sleepmgr_group + * @{ + */ +enum sleepmgr_mode { + //! Active mode. + SLEEPMGR_ACTIVE = 0, + /*! WFE sleep mode. + * Potential Wake Up sources: + * fast startup events (USB, RTC, RTT, WKUPs), + * interrupt, and events. */ + SLEEPMGR_SLEEP_WFE, + /*! WFI sleep mode. + * Potential Wake Up sources: fast startup events and interrupt. */ + SLEEPMGR_SLEEP_WFI, + /*! Wait mode, wakeup fast (in 3ms). + * XTAL is not disabled when sleep. + * Potential Wake Up sources: fast startup events */ + SLEEPMGR_WAIT_FAST, + /*! Wait mode. + * Potential Wake Up sources: fast startup events */ + SLEEPMGR_WAIT, +#if (!(SAMG51 || SAMG53 || SAMG54)) + //! Backup mode. Potential Wake Up sources: WKUPs, SM, RTT, RTC. + SLEEPMGR_BACKUP, +#endif + SLEEPMGR_NR_OF_MODES, +}; + +/** + * \internal + * \name Internal arrays + * @{ + */ +#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) +//! Sleep mode lock counters +extern uint8_t sleepmgr_locks[]; +#endif /* CONFIG_SLEEPMGR_ENABLE */ +//! @} + + +static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode) +{ + Assert(sleep_mode != SLEEPMGR_ACTIVE); +#ifdef CONFIG_SLEEPMGR_ENABLE + cpu_irq_disable(); + + // Atomically enable the global interrupts and enter the sleep mode. + pmc_sleep(sleep_mode); +#else + UNUSED(sleep_mode); + cpu_irq_enable(); +#endif /* CONFIG_SLEEPMGR_ENABLE */ + +} + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* SAM_SLEEPMGR_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sleepmgr.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sleepmgr.h new file mode 100644 index 00000000..054be7f8 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sleepmgr.h @@ -0,0 +1,263 @@ +/** + * \file + * + * \brief Sleep manager + * + * Copyright (c) 2010-2020 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef SLEEPMGR_H +#define SLEEPMGR_H + +#include +#include + +#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAMS70 || SAME70) +# include "sam/sleepmgr.h" +#elif XMEGA +# include "xmega/sleepmgr.h" +#elif UC3 +# include "uc3/sleepmgr.h" +#elif SAM4L +# include "sam4l/sleepmgr.h" +#elif MEGA +# include "mega/sleepmgr.h" +#elif (SAMD20 || SAMD21 || SAMR21 || SAMD11 || SAMDA1) +# include "samd/sleepmgr.h" +#elif (SAML21 || SAML22 || SAMR30 || SAMR34 || SAMR35 || WLR089) +# include "saml/sleepmgr.h" +#elif (SAMC21) +# include "samc/sleepmgr.h" +#else +# error Unsupported device. +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup sleepmgr_group Sleep manager + * + * The sleep manager is a service for ensuring that the device is not put to + * sleep in deeper sleep modes than the system (e.g., peripheral drivers, + * services or the application) allows at any given time. + * + * It is based on the use of lock counting for the individual sleep modes, and + * will put the device to sleep in the shallowest sleep mode that has a non-zero + * lock count. The drivers/services/application can change these counts by use + * of \ref sleepmgr_lock_mode and \ref sleepmgr_unlock_mode. + * Refer to \ref sleepmgr_mode for a list of the sleep modes available for + * locking, and the device datasheet for information on their effect. + * + * The application must supply the file \ref conf_sleepmgr.h. + * + * For the sleep manager to be enabled, the symbol \ref CONFIG_SLEEPMGR_ENABLE + * must be defined, e.g., in \ref conf_sleepmgr.h. If this symbol is not + * defined, the functions are replaced with dummy functions and no RAM is used. + * + * @{ + */ + +/** + * \def CONFIG_SLEEPMGR_ENABLE + * \brief Configuration symbol for enabling the sleep manager + * + * If this symbol is not defined, the functions of this service are replaced + * with dummy functions. This is useful for reducing code size and execution + * time if the sleep manager is not needed in the application. + * + * This symbol may be defined in \ref conf_sleepmgr.h. + */ +#if defined(__DOXYGEN__) && !defined(CONFIG_SLEEPMGR_ENABLE) +# define CONFIG_SLEEPMGR_ENABLE +#endif + +/** + * \enum sleepmgr_mode + * \brief Sleep mode locks + * + * Identifiers for the different sleep mode locks. + */ + +/** + * \brief Initialize the lock counts + * + * Sets all lock counts to 0, except the very last one, which is set to 1. This + * is done to simplify the algorithm for finding the deepest allowable sleep + * mode in \ref sleepmgr_enter_sleep. + */ +static inline void sleepmgr_init(void) +{ +#ifdef CONFIG_SLEEPMGR_ENABLE + uint8_t i; + + for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++) { + sleepmgr_locks[i] = 0; + } + sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1; +#endif /* CONFIG_SLEEPMGR_ENABLE */ +} + +/** + * \brief Increase lock count for a sleep mode + * + * Increases the lock count for \a mode to ensure that the sleep manager does + * not put the device to sleep in the deeper sleep modes. + * + * \param mode Sleep mode to lock. + */ +static inline void sleepmgr_lock_mode(enum sleepmgr_mode mode) +{ +#ifdef CONFIG_SLEEPMGR_ENABLE + irqflags_t flags; + + if(sleepmgr_locks[mode] >= 0xff) { + while (true) { + // Warning: maximum value of sleepmgr_locks buffer is no more than 255. + // Check APP or change the data type to uint16_t. + } + } + + // Enter a critical section + flags = cpu_irq_save(); + + ++sleepmgr_locks[mode]; + + // Leave the critical section + cpu_irq_restore(flags); +#else + UNUSED(mode); +#endif /* CONFIG_SLEEPMGR_ENABLE */ +} + +/** + * \brief Decrease lock count for a sleep mode + * + * Decreases the lock count for \a mode. If the lock count reaches 0, the sleep + * manager can put the device to sleep in the deeper sleep modes. + * + * \param mode Sleep mode to unlock. + */ +static inline void sleepmgr_unlock_mode(enum sleepmgr_mode mode) +{ +#ifdef CONFIG_SLEEPMGR_ENABLE + irqflags_t flags; + + if(sleepmgr_locks[mode] == 0) { + while (true) { + // Warning: minimum value of sleepmgr_locks buffer is no less than 0. + // Check APP. + } + } + + // Enter a critical section + flags = cpu_irq_save(); + + --sleepmgr_locks[mode]; + + // Leave the critical section + cpu_irq_restore(flags); +#else + UNUSED(mode); +#endif /* CONFIG_SLEEPMGR_ENABLE */ +} + + /** + * \brief Retrieves the deepest allowable sleep mode + * + * Searches through the sleep mode lock counts, starting at the shallowest sleep + * mode, until the first non-zero lock count is found. The deepest allowable + * sleep mode is then returned. + */ +static inline enum sleepmgr_mode sleepmgr_get_sleep_mode(void) +{ + enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE; + +#ifdef CONFIG_SLEEPMGR_ENABLE + uint8_t *lock_ptr = sleepmgr_locks; + + // Find first non-zero lock count, starting with the shallowest modes. + while (!(*lock_ptr)) { + lock_ptr++; + sleep_mode = (enum sleepmgr_mode)(sleep_mode + 1); + } + + // Catch the case where one too many sleepmgr_unlock_mode() call has been + // performed on the deepest sleep mode. + Assert((uintptr_t)(lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES); + +#endif /* CONFIG_SLEEPMGR_ENABLE */ + + return sleep_mode; +} + +/** + * \fn sleepmgr_enter_sleep + * \brief Go to sleep in the deepest allowed mode + * + * Searches through the sleep mode lock counts, starting at the shallowest sleep + * mode, until the first non-zero lock count is found. The device is then put to + * sleep in the sleep mode that corresponds to the lock. + * + * \note This function enables interrupts before going to sleep, and will leave + * them enabled upon return. This also applies if sleep is skipped due to ACTIVE + * mode being locked. + */ + +static inline void sleepmgr_enter_sleep(void) +{ +#ifdef CONFIG_SLEEPMGR_ENABLE + enum sleepmgr_mode sleep_mode; + + cpu_irq_disable(); + + // Find the deepest allowable sleep mode + sleep_mode = sleepmgr_get_sleep_mode(); + // Return right away if first mode (ACTIVE) is locked. + if (sleep_mode==SLEEPMGR_ACTIVE) { + cpu_irq_enable(); + return; + } + // Enter the deepest allowable sleep mode with interrupts enabled + sleepmgr_sleep(sleep_mode); +#else + cpu_irq_enable(); +#endif /* CONFIG_SLEEPMGR_ENABLE */ +} + + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* SLEEPMGR_H */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/interrupt.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/interrupt.h new file mode 100644 index 00000000..450d0f99 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/interrupt.h @@ -0,0 +1,132 @@ +/** + * \file + * + * \brief Global interrupt management for 8- and 32-bit AVR + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef UTILS_INTERRUPT_H +#define UTILS_INTERRUPT_H + +#include + +#if XMEGA || MEGA +# include "interrupt/interrupt_avr8.h" +#elif UC3 +# include "interrupt/interrupt_avr32.h" +#elif SAM || SAMB +# include "interrupt/interrupt_sam_nvic.h" +#else +# error Unsupported device. +#endif + +/** + * \defgroup interrupt_group Global interrupt management + * + * This is a driver for global enabling and disabling of interrupts. + * + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * \def CONFIG_INTERRUPT_FORCE_INTC + * \brief Force usage of the ASF INTC driver + * + * Predefine this symbol when preprocessing to force the use of the ASF INTC driver. + * This is useful to ensure compatibility across compilers and shall be used only when required + * by the application needs. + */ +# define CONFIG_INTERRUPT_FORCE_INTC +#endif + +//! \name Global interrupt flags +//@{ +/** + * \typedef irqflags_t + * \brief Type used for holding state of interrupt flag + */ + +/** + * \def cpu_irq_enable + * \brief Enable interrupts globally + */ + +/** + * \def cpu_irq_disable + * \brief Disable interrupts globally + */ + +/** + * \fn irqflags_t cpu_irq_save(void) + * \brief Get and clear the global interrupt flags + * + * Use in conjunction with \ref cpu_irq_restore. + * + * \return Current state of interrupt flags. + * + * \note This function leaves interrupts disabled. + */ + +/** + * \fn void cpu_irq_restore(irqflags_t flags) + * \brief Restore global interrupt flags + * + * Use in conjunction with \ref cpu_irq_save. + * + * \param flags State to set interrupt flag to. + */ + +/** + * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags) + * \brief Check if interrupts are globally enabled in supplied flags + * + * \param flags Currents state of interrupt flags. + * + * \return True if interrupts are enabled. + */ + +/** + * \def cpu_irq_is_enabled + * \brief Check if interrupts are globally enabled + * + * \return True if interrupts are enabled. + */ +//@} + +//! @} + +/** + * \ingroup interrupt_group + * \defgroup interrupt_deprecated_group Deprecated interrupt definitions + */ + +#endif /* UTILS_INTERRUPT_H */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c new file mode 100644 index 00000000..269b4cea --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based) + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "interrupt_sam_nvic.h" + +#if !defined(__DOXYGEN__) +/* Deprecated - global flag to determine the global interrupt state. Required by + * QTouch library, however new applications should use cpu_irq_is_enabled() + * which probes the true global interrupt state from the CPU special registers. + */ +volatile bool g_interrupt_enabled = true; +#endif + +void cpu_irq_enter_critical(void) +{ + if (cpu_irq_critical_section_counter == 0) { + if (cpu_irq_is_enabled()) { + cpu_irq_disable(); + cpu_irq_prev_interrupt_state = true; + } else { + /* Make sure the to save the prev state as false */ + cpu_irq_prev_interrupt_state = false; + } + + } + + cpu_irq_critical_section_counter++; +} + +void cpu_irq_leave_critical(void) +{ + /* Check if the user is trying to leave a critical section when not in a critical section */ + Assert(cpu_irq_critical_section_counter > 0); + + cpu_irq_critical_section_counter--; + + /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag + was enabled when entering critical state */ + if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) { + cpu_irq_enable(); + } +} + diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h new file mode 100644 index 00000000..7d215cf6 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h @@ -0,0 +1,179 @@ +/** + * \file + * + * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based) + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef UTILS_INTERRUPT_INTERRUPT_H +#define UTILS_INTERRUPT_INTERRUPT_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \weakgroup interrupt_group + * + * @{ + */ + +/** + * \name Interrupt Service Routine definition + * + * @{ + */ + +/** + * \brief Define service routine + * + * \note For NVIC devices the interrupt service routines are predefined to + * add to vector table in binary generation, so there is no service + * register at run time. The routine collections are in exceptions.h. + * + * Usage: + * \code + ISR(foo_irq_handler) + { + // Function definition + ... + } +\endcode + * + * \param func Name for the function. + */ +# define ISR(func) \ + void func (void) + +/** + * \brief Initialize interrupt vectors + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to initialize them, except defined the vector function with + * right name. + * + * This must be called prior to \ref irq_register_handler. + */ +# define irq_initialize_vectors() \ + do { \ + } while(0) + +/** + * \brief Register handler for interrupt + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to register them, except defined the vector function with + * right name. + * + * Usage: + * \code + irq_initialize_vectors(); + irq_register_handler(foo_irq_handler); +\endcode + * + * \note The function \a func must be defined with the \ref ISR macro. + * \note The functions prototypes can be found in the device exception header + * files (exceptions.h). + */ +# define irq_register_handler(int_num, int_prio) \ + NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \ + NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \ + NVIC_EnableIRQ( (IRQn_Type)int_num); \ + +//@} + +# define cpu_irq_enable() \ + do { \ + g_interrupt_enabled = true; \ + __DMB(); \ + __enable_irq(); \ + } while (0) +# define cpu_irq_disable() \ + do { \ + __disable_irq(); \ + __DMB(); \ + g_interrupt_enabled = false; \ + } while (0) + +typedef uint32_t irqflags_t; + +#if !defined(__DOXYGEN__) +extern volatile bool g_interrupt_enabled; +#endif + +#define cpu_irq_is_enabled() (__get_PRIMASK() == 0) + +static volatile uint32_t cpu_irq_critical_section_counter; +static volatile bool cpu_irq_prev_interrupt_state; + +static inline irqflags_t cpu_irq_save(void) +{ + volatile irqflags_t flags = cpu_irq_is_enabled(); + cpu_irq_disable(); + return flags; +} + +static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) +{ + return (flags); +} + +static inline void cpu_irq_restore(irqflags_t flags) +{ + if (cpu_irq_is_enabled_flags(flags)) + cpu_irq_enable(); +} + +void cpu_irq_enter_critical(void); +void cpu_irq_leave_critical(void); + +/** + * \weakgroup interrupt_deprecated_group + * @{ + */ + +#define Enable_global_interrupt() cpu_irq_enable() +#define Disable_global_interrupt() cpu_irq_disable() +#define Is_global_interrupt_enabled() cpu_irq_is_enabled() + +//@} + +//@} + +#ifdef __cplusplus +} +#endif + +#endif /* UTILS_INTERRUPT_INTERRUPT_H */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/parts.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/parts.h new file mode 100644 index 00000000..85689a89 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/parts.h @@ -0,0 +1,1768 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2012-2020 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +/** + * \defgroup part_macros_group Atmel part identification macros + * + * This collection of macros identify which series and families that the various + * Atmel parts belong to. These can be used to select part-dependent sections of + * code at compile time. + * + * @{ + */ + +/** + * \name Convenience macros for part checking + * @{ + */ +/* ! Check GCC and IAR part definition for 8-bit AVR */ +#define AVR8_PART_IS_DEFINED(part) \ + (defined(__ ## part ## __) || defined(__AVR_ ## part ## __)) + +/* ! Check GCC and IAR part definition for 32-bit AVR */ +#define AVR32_PART_IS_DEFINED(part) \ + (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __)) + +/* ! Check GCC and IAR part definition for SAM */ +#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __)) +/** @} */ + +/** + * \defgroup uc3_part_macros_group AVR UC3 parts + * @{ + */ + +/** + * \name AVR UC3 A series + * @{ + */ +#define UC3A0 ( \ + AVR32_PART_IS_DEFINED(UC3A0128) || \ + AVR32_PART_IS_DEFINED(UC3A0256) || \ + AVR32_PART_IS_DEFINED(UC3A0512) \ + ) + +#define UC3A1 ( \ + AVR32_PART_IS_DEFINED(UC3A1128) || \ + AVR32_PART_IS_DEFINED(UC3A1256) || \ + AVR32_PART_IS_DEFINED(UC3A1512) \ + ) + +#define UC3A3 ( \ + AVR32_PART_IS_DEFINED(UC3A364) || \ + AVR32_PART_IS_DEFINED(UC3A364S) || \ + AVR32_PART_IS_DEFINED(UC3A3128) || \ + AVR32_PART_IS_DEFINED(UC3A3128S) || \ + AVR32_PART_IS_DEFINED(UC3A3256) || \ + AVR32_PART_IS_DEFINED(UC3A3256S) \ + ) + +#define UC3A4 ( \ + AVR32_PART_IS_DEFINED(UC3A464) || \ + AVR32_PART_IS_DEFINED(UC3A464S) || \ + AVR32_PART_IS_DEFINED(UC3A4128) || \ + AVR32_PART_IS_DEFINED(UC3A4128S) || \ + AVR32_PART_IS_DEFINED(UC3A4256) || \ + AVR32_PART_IS_DEFINED(UC3A4256S) \ + ) +/** @} */ + +/** + * \name AVR UC3 B series + * @{ + */ +#define UC3B0 ( \ + AVR32_PART_IS_DEFINED(UC3B064) || \ + AVR32_PART_IS_DEFINED(UC3B0128) || \ + AVR32_PART_IS_DEFINED(UC3B0256) || \ + AVR32_PART_IS_DEFINED(UC3B0512) \ + ) + +#define UC3B1 ( \ + AVR32_PART_IS_DEFINED(UC3B164) || \ + AVR32_PART_IS_DEFINED(UC3B1128) || \ + AVR32_PART_IS_DEFINED(UC3B1256) || \ + AVR32_PART_IS_DEFINED(UC3B1512) \ + ) +/** @} */ + +/** + * \name AVR UC3 C series + * @{ + */ +#define UC3C0 ( \ + AVR32_PART_IS_DEFINED(UC3C064C) || \ + AVR32_PART_IS_DEFINED(UC3C0128C) || \ + AVR32_PART_IS_DEFINED(UC3C0256C) || \ + AVR32_PART_IS_DEFINED(UC3C0512C) \ + ) + +#define UC3C1 ( \ + AVR32_PART_IS_DEFINED(UC3C164C) || \ + AVR32_PART_IS_DEFINED(UC3C1128C) || \ + AVR32_PART_IS_DEFINED(UC3C1256C) || \ + AVR32_PART_IS_DEFINED(UC3C1512C) \ + ) + +#define UC3C2 ( \ + AVR32_PART_IS_DEFINED(UC3C264C) || \ + AVR32_PART_IS_DEFINED(UC3C2128C) || \ + AVR32_PART_IS_DEFINED(UC3C2256C) || \ + AVR32_PART_IS_DEFINED(UC3C2512C) \ + ) +/** @} */ + +/** + * \name AVR UC3 D series + * @{ + */ +#define UC3D3 ( \ + AVR32_PART_IS_DEFINED(UC64D3) || \ + AVR32_PART_IS_DEFINED(UC128D3) \ + ) + +#define UC3D4 ( \ + AVR32_PART_IS_DEFINED(UC64D4) || \ + AVR32_PART_IS_DEFINED(UC128D4) \ + ) +/** @} */ + +/** + * \name AVR UC3 L series + * @{ + */ +#define UC3L0 ( \ + AVR32_PART_IS_DEFINED(UC3L016) || \ + AVR32_PART_IS_DEFINED(UC3L032) || \ + AVR32_PART_IS_DEFINED(UC3L064) \ + ) + +#define UC3L0128 ( \ + AVR32_PART_IS_DEFINED(UC3L0128) \ + ) + +#define UC3L0256 ( \ + AVR32_PART_IS_DEFINED(UC3L0256) \ + ) + +#define UC3L3 ( \ + AVR32_PART_IS_DEFINED(UC64L3U) || \ + AVR32_PART_IS_DEFINED(UC128L3U) || \ + AVR32_PART_IS_DEFINED(UC256L3U) \ + ) + +#define UC3L4 ( \ + AVR32_PART_IS_DEFINED(UC64L4U) || \ + AVR32_PART_IS_DEFINED(UC128L4U) || \ + AVR32_PART_IS_DEFINED(UC256L4U) \ + ) + +#define UC3L3_L4 (UC3L3 || UC3L4) +/** @} */ + +/** + * \name AVR UC3 families + * @{ + */ +/** AVR UC3 A family */ +#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4) + +/** AVR UC3 B family */ +#define UC3B (UC3B0 || UC3B1) + +/** AVR UC3 C family */ +#define UC3C (UC3C0 || UC3C1 || UC3C2) + +/** AVR UC3 D family */ +#define UC3D (UC3D3 || UC3D4) + +/** AVR UC3 L family */ +#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4) +/** @} */ + +/** AVR UC3 product line */ +#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L) + +/** @} */ + +/** + * \defgroup xmega_part_macros_group AVR XMEGA parts + * @{ + */ + +/** + * \name AVR XMEGA A series + * @{ + */ +#define XMEGA_A1 ( \ + AVR8_PART_IS_DEFINED(ATxmega64A1) || \ + AVR8_PART_IS_DEFINED(ATxmega128A1) \ + ) + +#define XMEGA_A3 ( \ + AVR8_PART_IS_DEFINED(ATxmega64A3) || \ + AVR8_PART_IS_DEFINED(ATxmega128A3) || \ + AVR8_PART_IS_DEFINED(ATxmega192A3) || \ + AVR8_PART_IS_DEFINED(ATxmega256A3) \ + ) + +#define XMEGA_A3B ( \ + AVR8_PART_IS_DEFINED(ATxmega256A3B) \ + ) + +#define XMEGA_A4 ( \ + AVR8_PART_IS_DEFINED(ATxmega16A4) || \ + AVR8_PART_IS_DEFINED(ATxmega32A4) \ + ) +/** @} */ + +/** + * \name AVR XMEGA AU series + * @{ + */ +#define XMEGA_A1U ( \ + AVR8_PART_IS_DEFINED(ATxmega64A1U) || \ + AVR8_PART_IS_DEFINED(ATxmega128A1U) \ + ) + +#define XMEGA_A3U ( \ + AVR8_PART_IS_DEFINED(ATxmega64A3U) || \ + AVR8_PART_IS_DEFINED(ATxmega128A3U) || \ + AVR8_PART_IS_DEFINED(ATxmega192A3U) || \ + AVR8_PART_IS_DEFINED(ATxmega256A3U) \ + ) + +#define XMEGA_A3BU ( \ + AVR8_PART_IS_DEFINED(ATxmega256A3BU) \ + ) + +#define XMEGA_A4U ( \ + AVR8_PART_IS_DEFINED(ATxmega16A4U) || \ + AVR8_PART_IS_DEFINED(ATxmega32A4U) || \ + AVR8_PART_IS_DEFINED(ATxmega64A4U) || \ + AVR8_PART_IS_DEFINED(ATxmega128A4U) \ + ) +/** @} */ + +/** + * \name AVR XMEGA B series + * @{ + */ +#define XMEGA_B1 ( \ + AVR8_PART_IS_DEFINED(ATxmega64B1) || \ + AVR8_PART_IS_DEFINED(ATxmega128B1) \ + ) + +#define XMEGA_B3 ( \ + AVR8_PART_IS_DEFINED(ATxmega64B3) || \ + AVR8_PART_IS_DEFINED(ATxmega128B3) \ + ) +/** @} */ + +/** + * \name AVR XMEGA C series + * @{ + */ +#define XMEGA_C3 ( \ + AVR8_PART_IS_DEFINED(ATxmega384C3) || \ + AVR8_PART_IS_DEFINED(ATxmega256C3) || \ + AVR8_PART_IS_DEFINED(ATxmega192C3) || \ + AVR8_PART_IS_DEFINED(ATxmega128C3) || \ + AVR8_PART_IS_DEFINED(ATxmega64C3) || \ + AVR8_PART_IS_DEFINED(ATxmega32C3) \ + ) + +#define XMEGA_C4 ( \ + AVR8_PART_IS_DEFINED(ATxmega32C4) || \ + AVR8_PART_IS_DEFINED(ATxmega16C4) \ + ) +/** @} */ + +/** + * \name AVR XMEGA D series + * @{ + */ +#define XMEGA_D3 ( \ + AVR8_PART_IS_DEFINED(ATxmega32D3) || \ + AVR8_PART_IS_DEFINED(ATxmega64D3) || \ + AVR8_PART_IS_DEFINED(ATxmega128D3) || \ + AVR8_PART_IS_DEFINED(ATxmega192D3) || \ + AVR8_PART_IS_DEFINED(ATxmega256D3) || \ + AVR8_PART_IS_DEFINED(ATxmega384D3) \ + ) + +#define XMEGA_D4 ( \ + AVR8_PART_IS_DEFINED(ATxmega16D4) || \ + AVR8_PART_IS_DEFINED(ATxmega32D4) || \ + AVR8_PART_IS_DEFINED(ATxmega64D4) || \ + AVR8_PART_IS_DEFINED(ATxmega128D4) \ + ) +/** @} */ + +/** + * \name AVR XMEGA E series + * @{ + */ +#define XMEGA_E5 ( \ + AVR8_PART_IS_DEFINED(ATxmega8E5) || \ + AVR8_PART_IS_DEFINED(ATxmega16E5) || \ + AVR8_PART_IS_DEFINED(ATxmega32E5) \ + ) +/** @} */ + + +/** + * \name AVR XMEGA families + * @{ + */ +/** AVR XMEGA A family */ +#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4) + +/** AVR XMEGA AU family */ +#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U) + +/** AVR XMEGA B family */ +#define XMEGA_B (XMEGA_B1 || XMEGA_B3) + +/** AVR XMEGA C family */ +#define XMEGA_C (XMEGA_C3 || XMEGA_C4) + +/** AVR XMEGA D family */ +#define XMEGA_D (XMEGA_D3 || XMEGA_D4) + +/** AVR XMEGA E family */ +#define XMEGA_E (XMEGA_E5) +/** @} */ + + +/** AVR XMEGA product line */ +#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E) + +/** @} */ + +/** + * \defgroup mega_part_macros_group megaAVR parts + * + * \note These megaAVR groupings are based on the groups in AVR Libc for the + * part header files. They are not names of official megaAVR device series or + * families. + * + * @{ + */ + +/** + * \name ATmegaxx0/xx1 subgroups + * @{ + */ +#define MEGA_XX0 ( \ + AVR8_PART_IS_DEFINED(ATmega640) || \ + AVR8_PART_IS_DEFINED(ATmega1280) || \ + AVR8_PART_IS_DEFINED(ATmega2560) \ + ) + +#define MEGA_XX1 ( \ + AVR8_PART_IS_DEFINED(ATmega1281) || \ + AVR8_PART_IS_DEFINED(ATmega2561) \ + ) +/** @} */ + +/** + * \name megaAVR groups + * @{ + */ +/** ATmegaxx0/xx1 group */ +#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1) + +/** ATmegaxx4 group */ +#define MEGA_XX4 ( \ + AVR8_PART_IS_DEFINED(ATmega164A) || \ + AVR8_PART_IS_DEFINED(ATmega164PA) || \ + AVR8_PART_IS_DEFINED(ATmega324A) || \ + AVR8_PART_IS_DEFINED(ATmega324PA) || \ + AVR8_PART_IS_DEFINED(ATmega324PB) || \ + AVR8_PART_IS_DEFINED(ATmega644) || \ + AVR8_PART_IS_DEFINED(ATmega644A) || \ + AVR8_PART_IS_DEFINED(ATmega644PA) || \ + AVR8_PART_IS_DEFINED(ATmega1284P) || \ + AVR8_PART_IS_DEFINED(ATmega128RFA1) \ + ) + +/** ATmegaxx4 group */ +#define MEGA_XX4_A ( \ + AVR8_PART_IS_DEFINED(ATmega164A) || \ + AVR8_PART_IS_DEFINED(ATmega164PA) || \ + AVR8_PART_IS_DEFINED(ATmega324A) || \ + AVR8_PART_IS_DEFINED(ATmega324PA) || \ + AVR8_PART_IS_DEFINED(ATmega644A) || \ + AVR8_PART_IS_DEFINED(ATmega644PA) || \ + AVR8_PART_IS_DEFINED(ATmega1284P) \ + ) + +/** ATmegaxx8 group */ +#define MEGA_XX8 ( \ + AVR8_PART_IS_DEFINED(ATmega48) || \ + AVR8_PART_IS_DEFINED(ATmega48A) || \ + AVR8_PART_IS_DEFINED(ATmega48PA) || \ + AVR8_PART_IS_DEFINED(ATmega48PB) || \ + AVR8_PART_IS_DEFINED(ATmega88) || \ + AVR8_PART_IS_DEFINED(ATmega88A) || \ + AVR8_PART_IS_DEFINED(ATmega88PA) || \ + AVR8_PART_IS_DEFINED(ATmega88PB) || \ + AVR8_PART_IS_DEFINED(ATmega168) || \ + AVR8_PART_IS_DEFINED(ATmega168A) || \ + AVR8_PART_IS_DEFINED(ATmega168PA) || \ + AVR8_PART_IS_DEFINED(ATmega168PB) || \ + AVR8_PART_IS_DEFINED(ATmega328) || \ + AVR8_PART_IS_DEFINED(ATmega328P) || \ + AVR8_PART_IS_DEFINED(ATmega328PB) \ + ) + +/** ATmegaxx8A/P/PA group */ +#define MEGA_XX8_A ( \ + AVR8_PART_IS_DEFINED(ATmega48A) || \ + AVR8_PART_IS_DEFINED(ATmega48PA) || \ + AVR8_PART_IS_DEFINED(ATmega88A) || \ + AVR8_PART_IS_DEFINED(ATmega88PA) || \ + AVR8_PART_IS_DEFINED(ATmega168A) || \ + AVR8_PART_IS_DEFINED(ATmega168PA) || \ + AVR8_PART_IS_DEFINED(ATmega328P) \ + ) + +/** ATmegaxx group */ +#define MEGA_XX ( \ + AVR8_PART_IS_DEFINED(ATmega16) || \ + AVR8_PART_IS_DEFINED(ATmega16A) || \ + AVR8_PART_IS_DEFINED(ATmega32) || \ + AVR8_PART_IS_DEFINED(ATmega32A) || \ + AVR8_PART_IS_DEFINED(ATmega64) || \ + AVR8_PART_IS_DEFINED(ATmega64A) || \ + AVR8_PART_IS_DEFINED(ATmega128) || \ + AVR8_PART_IS_DEFINED(ATmega128A) \ + ) + +/** ATmegaxxA/P/PA group */ +#define MEGA_XX_A ( \ + AVR8_PART_IS_DEFINED(ATmega16A) || \ + AVR8_PART_IS_DEFINED(ATmega32A) || \ + AVR8_PART_IS_DEFINED(ATmega64A) || \ + AVR8_PART_IS_DEFINED(ATmega128A) \ + ) +/** ATmegaxxRFA1 group */ +#define MEGA_RFA1 ( \ + AVR8_PART_IS_DEFINED(ATmega128RFA1) \ + ) + +/** ATmegaxxRFR2 group */ +#define MEGA_RFR2 ( \ + AVR8_PART_IS_DEFINED(ATmega64RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega128RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega256RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega644RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega2564RFR2) \ + ) + + +/** ATmegaxxRFxx group */ +#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2) + +/** + * \name ATmegaxx_un0/un1/un2 subgroups + * @{ + */ +#define MEGA_XX_UN0 ( \ + AVR8_PART_IS_DEFINED(ATmega16) || \ + AVR8_PART_IS_DEFINED(ATmega16A) || \ + AVR8_PART_IS_DEFINED(ATmega32) || \ + AVR8_PART_IS_DEFINED(ATmega32A) \ + ) + +/** ATmegaxx group without power reduction and + * And interrupt sense register. + */ +#define MEGA_XX_UN1 ( \ + AVR8_PART_IS_DEFINED(ATmega64) || \ + AVR8_PART_IS_DEFINED(ATmega64A) || \ + AVR8_PART_IS_DEFINED(ATmega128) || \ + AVR8_PART_IS_DEFINED(ATmega128A) \ + ) + +/** ATmegaxx group without power reduction and + * And interrupt sense register. + */ +#define MEGA_XX_UN2 ( \ + AVR8_PART_IS_DEFINED(ATmega169P) || \ + AVR8_PART_IS_DEFINED(ATmega169PA) || \ + AVR8_PART_IS_DEFINED(ATmega329P) || \ + AVR8_PART_IS_DEFINED(ATmega329PA) \ + ) + +/** Devices added to complete megaAVR offering. + * Please do not use this group symbol as it is not intended + * to be permanent: the devices should be regrouped. + */ +#define MEGA_UNCATEGORIZED ( \ + AVR8_PART_IS_DEFINED(AT90CAN128) || \ + AVR8_PART_IS_DEFINED(AT90CAN32) || \ + AVR8_PART_IS_DEFINED(AT90CAN64) || \ + AVR8_PART_IS_DEFINED(AT90PWM1) || \ + AVR8_PART_IS_DEFINED(AT90PWM216) || \ + AVR8_PART_IS_DEFINED(AT90PWM2B) || \ + AVR8_PART_IS_DEFINED(AT90PWM316) || \ + AVR8_PART_IS_DEFINED(AT90PWM3B) || \ + AVR8_PART_IS_DEFINED(AT90PWM81) || \ + AVR8_PART_IS_DEFINED(AT90USB1286) || \ + AVR8_PART_IS_DEFINED(AT90USB1287) || \ + AVR8_PART_IS_DEFINED(AT90USB162) || \ + AVR8_PART_IS_DEFINED(AT90USB646) || \ + AVR8_PART_IS_DEFINED(AT90USB647) || \ + AVR8_PART_IS_DEFINED(AT90USB82) || \ + AVR8_PART_IS_DEFINED(ATmega1284) || \ + AVR8_PART_IS_DEFINED(ATmega162) || \ + AVR8_PART_IS_DEFINED(ATmega164P) || \ + AVR8_PART_IS_DEFINED(ATmega165A) || \ + AVR8_PART_IS_DEFINED(ATmega165P) || \ + AVR8_PART_IS_DEFINED(ATmega165PA) || \ + AVR8_PART_IS_DEFINED(ATmega168P) || \ + AVR8_PART_IS_DEFINED(ATmega169A) || \ + AVR8_PART_IS_DEFINED(ATmega16M1) || \ + AVR8_PART_IS_DEFINED(ATmega16U2) || \ + AVR8_PART_IS_DEFINED(ATmega16U4) || \ + AVR8_PART_IS_DEFINED(ATmega256RFA2) || \ + AVR8_PART_IS_DEFINED(ATmega324P) || \ + AVR8_PART_IS_DEFINED(ATmega325) || \ + AVR8_PART_IS_DEFINED(ATmega3250) || \ + AVR8_PART_IS_DEFINED(ATmega3250A) || \ + AVR8_PART_IS_DEFINED(ATmega3250P) || \ + AVR8_PART_IS_DEFINED(ATmega3250PA) || \ + AVR8_PART_IS_DEFINED(ATmega325A) || \ + AVR8_PART_IS_DEFINED(ATmega325P) || \ + AVR8_PART_IS_DEFINED(ATmega325PA) || \ + AVR8_PART_IS_DEFINED(ATmega329) || \ + AVR8_PART_IS_DEFINED(ATmega3290) || \ + AVR8_PART_IS_DEFINED(ATmega3290A) || \ + AVR8_PART_IS_DEFINED(ATmega3290P) || \ + AVR8_PART_IS_DEFINED(ATmega3290PA) || \ + AVR8_PART_IS_DEFINED(ATmega329A) || \ + AVR8_PART_IS_DEFINED(ATmega32M1) || \ + AVR8_PART_IS_DEFINED(ATmega32U2) || \ + AVR8_PART_IS_DEFINED(ATmega32U4) || \ + AVR8_PART_IS_DEFINED(ATmega48P) || \ + AVR8_PART_IS_DEFINED(ATmega644P) || \ + AVR8_PART_IS_DEFINED(ATmega645) || \ + AVR8_PART_IS_DEFINED(ATmega6450) || \ + AVR8_PART_IS_DEFINED(ATmega6450A) || \ + AVR8_PART_IS_DEFINED(ATmega6450P) || \ + AVR8_PART_IS_DEFINED(ATmega645A) || \ + AVR8_PART_IS_DEFINED(ATmega645P) || \ + AVR8_PART_IS_DEFINED(ATmega649) || \ + AVR8_PART_IS_DEFINED(ATmega6490) || \ + AVR8_PART_IS_DEFINED(ATmega6490A) || \ + AVR8_PART_IS_DEFINED(ATmega6490P) || \ + AVR8_PART_IS_DEFINED(ATmega649A) || \ + AVR8_PART_IS_DEFINED(ATmega649P) || \ + AVR8_PART_IS_DEFINED(ATmega64M1) || \ + AVR8_PART_IS_DEFINED(ATmega64RFA2) || \ + AVR8_PART_IS_DEFINED(ATmega8) || \ + AVR8_PART_IS_DEFINED(ATmega8515) || \ + AVR8_PART_IS_DEFINED(ATmega8535) || \ + AVR8_PART_IS_DEFINED(ATmega88P) || \ + AVR8_PART_IS_DEFINED(ATmega8A) || \ + AVR8_PART_IS_DEFINED(ATmega8U2) \ + ) + +/** Unspecified group */ +#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \ + MEGA_UNCATEGORIZED) + +/** @} */ + +/** megaAVR product line */ +#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \ + MEGA_UNSPECIFIED) + +/** @} */ + +/** + * \defgroup sam_part_macros_group SAM parts + * @{ + */ + +/** + * \name SAM3S series + * @{ + */ +#define SAM3S1 ( \ + SAM_PART_IS_DEFINED(SAM3S1A) || \ + SAM_PART_IS_DEFINED(SAM3S1B) || \ + SAM_PART_IS_DEFINED(SAM3S1C) \ + ) + +#define SAM3S2 ( \ + SAM_PART_IS_DEFINED(SAM3S2A) || \ + SAM_PART_IS_DEFINED(SAM3S2B) || \ + SAM_PART_IS_DEFINED(SAM3S2C) \ + ) + +#define SAM3S4 ( \ + SAM_PART_IS_DEFINED(SAM3S4A) || \ + SAM_PART_IS_DEFINED(SAM3S4B) || \ + SAM_PART_IS_DEFINED(SAM3S4C) \ + ) + +#define SAM3S8 ( \ + SAM_PART_IS_DEFINED(SAM3S8B) || \ + SAM_PART_IS_DEFINED(SAM3S8C) \ + ) + +#define SAM3SD8 ( \ + SAM_PART_IS_DEFINED(SAM3SD8B) || \ + SAM_PART_IS_DEFINED(SAM3SD8C) \ + ) +/** @} */ + +/** + * \name SAM3U series + * @{ + */ +#define SAM3U1 ( \ + SAM_PART_IS_DEFINED(SAM3U1C) || \ + SAM_PART_IS_DEFINED(SAM3U1E) \ + ) + +#define SAM3U2 ( \ + SAM_PART_IS_DEFINED(SAM3U2C) || \ + SAM_PART_IS_DEFINED(SAM3U2E) \ + ) + +#define SAM3U4 ( \ + SAM_PART_IS_DEFINED(SAM3U4C) || \ + SAM_PART_IS_DEFINED(SAM3U4E) \ + ) +/** @} */ + +/** + * \name SAM3N series + * @{ + */ +#define SAM3N00 ( \ + SAM_PART_IS_DEFINED(SAM3N00A) || \ + SAM_PART_IS_DEFINED(SAM3N00B) \ + ) + +#define SAM3N0 ( \ + SAM_PART_IS_DEFINED(SAM3N0A) || \ + SAM_PART_IS_DEFINED(SAM3N0B) || \ + SAM_PART_IS_DEFINED(SAM3N0C) \ + ) + +#define SAM3N1 ( \ + SAM_PART_IS_DEFINED(SAM3N1A) || \ + SAM_PART_IS_DEFINED(SAM3N1B) || \ + SAM_PART_IS_DEFINED(SAM3N1C) \ + ) + +#define SAM3N2 ( \ + SAM_PART_IS_DEFINED(SAM3N2A) || \ + SAM_PART_IS_DEFINED(SAM3N2B) || \ + SAM_PART_IS_DEFINED(SAM3N2C) \ + ) + +#define SAM3N4 ( \ + SAM_PART_IS_DEFINED(SAM3N4A) || \ + SAM_PART_IS_DEFINED(SAM3N4B) || \ + SAM_PART_IS_DEFINED(SAM3N4C) \ + ) +/** @} */ + +/** + * \name SAM3X series + * @{ + */ +#define SAM3X4 ( \ + SAM_PART_IS_DEFINED(SAM3X4C) || \ + SAM_PART_IS_DEFINED(SAM3X4E) \ + ) + +#define SAM3X8 ( \ + SAM_PART_IS_DEFINED(SAM3X8C) || \ + SAM_PART_IS_DEFINED(SAM3X8E) || \ + SAM_PART_IS_DEFINED(SAM3X8H) \ + ) +/** @} */ + +/** + * \name SAM3A series + * @{ + */ +#define SAM3A4 ( \ + SAM_PART_IS_DEFINED(SAM3A4C) \ + ) + +#define SAM3A8 ( \ + SAM_PART_IS_DEFINED(SAM3A8C) \ + ) +/** @} */ + +/** + * \name SAM4S series + * @{ + */ +#define SAM4S2 ( \ + SAM_PART_IS_DEFINED(SAM4S2A) || \ + SAM_PART_IS_DEFINED(SAM4S2B) || \ + SAM_PART_IS_DEFINED(SAM4S2C) \ + ) + +#define SAM4S4 ( \ + SAM_PART_IS_DEFINED(SAM4S4A) || \ + SAM_PART_IS_DEFINED(SAM4S4B) || \ + SAM_PART_IS_DEFINED(SAM4S4C) \ + ) + +#define SAM4S8 ( \ + SAM_PART_IS_DEFINED(SAM4S8B) || \ + SAM_PART_IS_DEFINED(SAM4S8C) \ + ) + +#define SAM4S16 ( \ + SAM_PART_IS_DEFINED(SAM4S16B) || \ + SAM_PART_IS_DEFINED(SAM4S16C) \ + ) + +#define SAM4SA16 ( \ + SAM_PART_IS_DEFINED(SAM4SA16B) || \ + SAM_PART_IS_DEFINED(SAM4SA16C) \ + ) + +#define SAM4SD16 ( \ + SAM_PART_IS_DEFINED(SAM4SD16B) || \ + SAM_PART_IS_DEFINED(SAM4SD16C) \ + ) + +#define SAM4SD32 ( \ + SAM_PART_IS_DEFINED(SAM4SD32B) || \ + SAM_PART_IS_DEFINED(SAM4SD32C) \ + ) +/** @} */ + +/** + * \name SAM4L series + * @{ + */ +#define SAM4LS ( \ + SAM_PART_IS_DEFINED(SAM4LS2A) || \ + SAM_PART_IS_DEFINED(SAM4LS2B) || \ + SAM_PART_IS_DEFINED(SAM4LS2C) || \ + SAM_PART_IS_DEFINED(SAM4LS4A) || \ + SAM_PART_IS_DEFINED(SAM4LS4B) || \ + SAM_PART_IS_DEFINED(SAM4LS4C) || \ + SAM_PART_IS_DEFINED(SAM4LS8A) || \ + SAM_PART_IS_DEFINED(SAM4LS8B) || \ + SAM_PART_IS_DEFINED(SAM4LS8C) \ + ) + +#define SAM4LC ( \ + SAM_PART_IS_DEFINED(SAM4LC2A) || \ + SAM_PART_IS_DEFINED(SAM4LC2B) || \ + SAM_PART_IS_DEFINED(SAM4LC2C) || \ + SAM_PART_IS_DEFINED(SAM4LC4A) || \ + SAM_PART_IS_DEFINED(SAM4LC4B) || \ + SAM_PART_IS_DEFINED(SAM4LC4C) || \ + SAM_PART_IS_DEFINED(SAM4LC8A) || \ + SAM_PART_IS_DEFINED(SAM4LC8B) || \ + SAM_PART_IS_DEFINED(SAM4LC8C) \ + ) +/** @} */ + +/** + * \name SAMD20 series + * @{ + */ +#define SAMD20J ( \ + SAM_PART_IS_DEFINED(SAMD20J14) || \ + SAM_PART_IS_DEFINED(SAMD20J15) || \ + SAM_PART_IS_DEFINED(SAMD20J16) || \ + SAM_PART_IS_DEFINED(SAMD20J14B) || \ + SAM_PART_IS_DEFINED(SAMD20J15B) || \ + SAM_PART_IS_DEFINED(SAMD20J16B) || \ + SAM_PART_IS_DEFINED(SAMD20J17) || \ + SAM_PART_IS_DEFINED(SAMD20J18) \ + ) + +#define SAMD20G ( \ + SAM_PART_IS_DEFINED(SAMD20G14) || \ + SAM_PART_IS_DEFINED(SAMD20G15) || \ + SAM_PART_IS_DEFINED(SAMD20G16) || \ + SAM_PART_IS_DEFINED(SAMD20G14B) || \ + SAM_PART_IS_DEFINED(SAMD20G15B) || \ + SAM_PART_IS_DEFINED(SAMD20G16B) || \ + SAM_PART_IS_DEFINED(SAMD20G17) || \ + SAM_PART_IS_DEFINED(SAMD20G17U) || \ + SAM_PART_IS_DEFINED(SAMD20G18) || \ + SAM_PART_IS_DEFINED(SAMD20G18U) \ + ) + +#define SAMD20E ( \ + SAM_PART_IS_DEFINED(SAMD20E14) || \ + SAM_PART_IS_DEFINED(SAMD20E15) || \ + SAM_PART_IS_DEFINED(SAMD20E16) || \ + SAM_PART_IS_DEFINED(SAMD20E14B) || \ + SAM_PART_IS_DEFINED(SAMD20E15B) || \ + SAM_PART_IS_DEFINED(SAMD20E16B) || \ + SAM_PART_IS_DEFINED(SAMD20E17) || \ + SAM_PART_IS_DEFINED(SAMD20E18) \ + ) + +/** @} */ + +/** + * \name SAMD21 series + * @{ + */ +#define SAMD21J ( \ + SAM_PART_IS_DEFINED(SAMD21J15A) || \ + SAM_PART_IS_DEFINED(SAMD21J16A) || \ + SAM_PART_IS_DEFINED(SAMD21J17A) || \ + SAM_PART_IS_DEFINED(SAMD21J18A) || \ + SAM_PART_IS_DEFINED(SAMD21J15B) || \ + SAM_PART_IS_DEFINED(SAMD21J16B) || \ + SAM_PART_IS_DEFINED(SAMD21J17D) \ + ) + +#define SAMD21G ( \ + SAM_PART_IS_DEFINED(SAMD21G15A) || \ + SAM_PART_IS_DEFINED(SAMD21G16A) || \ + SAM_PART_IS_DEFINED(SAMD21G17A) || \ + SAM_PART_IS_DEFINED(SAMD21G17AU) || \ + SAM_PART_IS_DEFINED(SAMD21G18A) || \ + SAM_PART_IS_DEFINED(SAMD21G18AU) || \ + SAM_PART_IS_DEFINED(SAMD21G15B) || \ + SAM_PART_IS_DEFINED(SAMD21G16B) || \ + SAM_PART_IS_DEFINED(SAMD21G15L) || \ + SAM_PART_IS_DEFINED(SAMD21G16L) || \ + SAM_PART_IS_DEFINED(SAMD21G17D) || \ + SAM_PART_IS_DEFINED(SAMD21G17L) \ + ) + +#define SAMD21GXXL ( \ + SAM_PART_IS_DEFINED(SAMD21G15L) || \ + SAM_PART_IS_DEFINED(SAMD21G16L) || \ + SAM_PART_IS_DEFINED(SAMD21G17L) \ + ) + +#define SAMD21E ( \ + SAM_PART_IS_DEFINED(SAMD21E15A) || \ + SAM_PART_IS_DEFINED(SAMD21E16A) || \ + SAM_PART_IS_DEFINED(SAMD21E17A) || \ + SAM_PART_IS_DEFINED(SAMD21E18A) || \ + SAM_PART_IS_DEFINED(SAMD21E15B) || \ + SAM_PART_IS_DEFINED(SAMD21E15BU) || \ + SAM_PART_IS_DEFINED(SAMD21E16B) || \ + SAM_PART_IS_DEFINED(SAMD21E16BU) || \ + SAM_PART_IS_DEFINED(SAMD21E15L) || \ + SAM_PART_IS_DEFINED(SAMD21E16L) || \ + SAM_PART_IS_DEFINED(SAMD21E17D) || \ + SAM_PART_IS_DEFINED(SAMD21E17DU) || \ + SAM_PART_IS_DEFINED(SAMD21E17L) \ + ) + +#define SAMD21EXXL ( \ + SAM_PART_IS_DEFINED(SAMD21E15L) || \ + SAM_PART_IS_DEFINED(SAMD21E16L) || \ + SAM_PART_IS_DEFINED(SAMD21E17L) \ + ) + +/** @} */ + +/** + * \name SAMR21 series + * @{ + */ +#define SAMR21G ( \ + SAM_PART_IS_DEFINED(SAMR21G16A) || \ + SAM_PART_IS_DEFINED(SAMR21G17A) || \ + SAM_PART_IS_DEFINED(SAMR21G18A) \ + ) + +#define SAMR21E ( \ + SAM_PART_IS_DEFINED(SAMR21E16A) || \ + SAM_PART_IS_DEFINED(SAMR21E17A) || \ + SAM_PART_IS_DEFINED(SAMR21E18A) || \ + SAM_PART_IS_DEFINED(SAMR21E19A) \ + ) +/** @} */ + +/** + * \name SAMR30 series + * @{ + */ +#define SAMR30G ( \ + SAM_PART_IS_DEFINED(SAMR30G18A) \ + ) + +#define SAMR30E ( \ + SAM_PART_IS_DEFINED(SAMR30E18A) \ + ) +/** @} */ + +/** + * \name SAMR34 series + * @{ + */ +#define SAMR34J ( \ + SAM_PART_IS_DEFINED(SAMR34J18A) || \ + SAM_PART_IS_DEFINED(SAMR34J17A) || \ + SAM_PART_IS_DEFINED(SAMR34J16A) || \ + SAM_PART_IS_DEFINED(SAMR34J18B) || \ + SAM_PART_IS_DEFINED(SAMR34J17B) || \ + SAM_PART_IS_DEFINED(SAMR34J16B) \ + ) + +/* Group for SAMR34 A variant: SAMR34J [16/17/18]A */ +#define SAMR34JXXA ( \ + SAM_PART_IS_DEFINED(SAMR34J18A) || \ + SAM_PART_IS_DEFINED(SAMR34J17A) || \ + SAM_PART_IS_DEFINED(SAMR34J16A) \ +) +/* Group for SAMR34 B variant: SAMR34J [16/17/18]B */ +#define SAMR34JXXB ( \ + SAM_PART_IS_DEFINED(SAMR34J18B) || \ + SAM_PART_IS_DEFINED(SAMR34J17B) || \ + SAM_PART_IS_DEFINED(SAMR34J16B) \ +) + +/* Group for SAMR35 B variant: SAMR35J [16/17/18]B */ +#define SAMR35J ( \ + SAM_PART_IS_DEFINED(SAMR35J18B) || \ + SAM_PART_IS_DEFINED(SAMR35J17B) || \ + SAM_PART_IS_DEFINED(SAMR35J16B) \ +) + +/* Group for SAMR35 B variant: SAMR35J [16/17/18]B */ +#define SAMR35JXXB ( \ + SAM_PART_IS_DEFINED(SAMR35J18B) || \ + SAM_PART_IS_DEFINED(SAMR35J17B) || \ + SAM_PART_IS_DEFINED(SAMR35J16B) \ +) + +/* Group for SAMR35 B variant: SAMR35J [16/17/18]B */ +#define WLR089U ( \ + SAM_PART_IS_DEFINED(WLR089U0) \ +) + +/* Group for WLR089U variant: SAMR35U [0] */ +#define WLR089U0 ( \ + SAM_PART_IS_DEFINED(WLR089U0) \ +) + +/** + * \name SAMB11 series + * @{ + */ +#define SAMB11G ( \ + SAM_PART_IS_DEFINED(SAMB11G18A) || \ + SAM_PART_IS_DEFINED(SAMB11ZR) \ + ) +#define BTLC1000 ( \ + SAM_PART_IS_DEFINED(BTLC1000WLCSP) \ + ) + +/** @} */ + +/** + * \name SAMD09 series + * @{ + */ +#define SAMD09C ( \ + SAM_PART_IS_DEFINED(SAMD09C13A) \ + ) + +#define SAMD09D ( \ + SAM_PART_IS_DEFINED(SAMD09D14A) \ + ) +/** @} */ + +/** + * \name SAMD10 series + * @{ + */ +#define SAMD10C ( \ + SAM_PART_IS_DEFINED(SAMD10C12A) || \ + SAM_PART_IS_DEFINED(SAMD10C13A) || \ + SAM_PART_IS_DEFINED(SAMD10C14A) \ + ) + +#define SAMD10DS ( \ + SAM_PART_IS_DEFINED(SAMD10D12AS) || \ + SAM_PART_IS_DEFINED(SAMD10D13AS) || \ + SAM_PART_IS_DEFINED(SAMD10D14AS) \ + ) + +#define SAMD10DM ( \ + SAM_PART_IS_DEFINED(SAMD10D12AM) || \ + SAM_PART_IS_DEFINED(SAMD10D13AM) || \ + SAM_PART_IS_DEFINED(SAMD10D14AM) \ + ) + +#define SAMD10DU ( \ + SAM_PART_IS_DEFINED(SAMD10D14AU) \ + ) +/** @} */ + +/** + * \name SAMD11 series + * @{ + */ +#define SAMD11C ( \ + SAM_PART_IS_DEFINED(SAMD11C14A) \ + ) + +#define SAMD11DS ( \ + SAM_PART_IS_DEFINED(SAMD11D14AS) \ + ) + +#define SAMD11DM ( \ + SAM_PART_IS_DEFINED(SAMD11D14AM) \ + ) + +#define SAMD11DU ( \ + SAM_PART_IS_DEFINED(SAMD11D14AU) \ + ) +/** @} */ + +/** + * \name SAML21 series + * @{ + */ +#define SAML21E ( \ + SAM_PART_IS_DEFINED(SAML21E18A) || \ + SAM_PART_IS_DEFINED(SAML21E15B) || \ + SAM_PART_IS_DEFINED(SAML21E16B) || \ + SAM_PART_IS_DEFINED(SAML21E17B) || \ + SAM_PART_IS_DEFINED(SAML21E18B) \ + ) + +#define SAML21G ( \ + SAM_PART_IS_DEFINED(SAML21G18A) || \ + SAM_PART_IS_DEFINED(SAML21G16B) || \ + SAM_PART_IS_DEFINED(SAML21G17B) || \ + SAM_PART_IS_DEFINED(SAML21G18B) \ + ) + +#define SAML21J ( \ + SAM_PART_IS_DEFINED(SAML21J18A) || \ + SAM_PART_IS_DEFINED(SAML21J16B) || \ + SAM_PART_IS_DEFINED(SAML21J17B) || \ + SAM_PART_IS_DEFINED(SAML21J18B) \ + ) + +/* Group for SAML21 A variant: SAML21[E/G/J][18]A */ +#define SAML21XXXA ( \ + SAM_PART_IS_DEFINED(SAML21E18A) || \ + SAM_PART_IS_DEFINED(SAML21G18A) || \ + SAM_PART_IS_DEFINED(SAML21J18A) \ + ) + +/* Group for SAML21 B variant: SAML21[E/G/J][15/16/1718]B */ +#define SAML21XXXB ( \ + SAM_PART_IS_DEFINED(SAML21E15B) || \ + SAM_PART_IS_DEFINED(SAML21E16B) || \ + SAM_PART_IS_DEFINED(SAML21E17B) || \ + SAM_PART_IS_DEFINED(SAML21E18B) || \ + SAM_PART_IS_DEFINED(SAML21G16B) || \ + SAM_PART_IS_DEFINED(SAML21G17B) || \ + SAM_PART_IS_DEFINED(SAML21G18B) || \ + SAM_PART_IS_DEFINED(SAML21J16B) || \ + SAM_PART_IS_DEFINED(SAML21J17B) || \ + SAM_PART_IS_DEFINED(SAML21J18B) \ + ) + +/** @} */ + +/** + * \name SAML22 series + * @{ + */ +#define SAML22N ( \ + SAM_PART_IS_DEFINED(SAML22N16A) || \ + SAM_PART_IS_DEFINED(SAML22N17A) || \ + SAM_PART_IS_DEFINED(SAML22N18A) \ + ) + +#define SAML22G ( \ + SAM_PART_IS_DEFINED(SAML22G16A) || \ + SAM_PART_IS_DEFINED(SAML22G17A) || \ + SAM_PART_IS_DEFINED(SAML22G18A) \ + ) + +#define SAML22J ( \ + SAM_PART_IS_DEFINED(SAML22J16A) || \ + SAM_PART_IS_DEFINED(SAML22J17A) || \ + SAM_PART_IS_DEFINED(SAML22J18A) \ + ) +/** @} */ + +/** + * \name SAMDA1 series + * @{ + */ +#define SAMDA1J ( \ + SAM_PART_IS_DEFINED(SAMDA1J14A) || \ + SAM_PART_IS_DEFINED(SAMDA1J15B) || \ + SAM_PART_IS_DEFINED(SAMDA1J15A) || \ + SAM_PART_IS_DEFINED(SAMDA1J15B) || \ + SAM_PART_IS_DEFINED(SAMDA1J16A) || \ + SAM_PART_IS_DEFINED(SAMDA1J16B) \ + ) + +#define SAMDA1G ( \ + SAM_PART_IS_DEFINED(SAMDA1G14A) || \ + SAM_PART_IS_DEFINED(SAMDA1G14B) || \ + SAM_PART_IS_DEFINED(SAMDA1G15A) || \ + SAM_PART_IS_DEFINED(SAMDA1G15B) || \ + SAM_PART_IS_DEFINED(SAMDA1G16A) || \ + SAM_PART_IS_DEFINED(SAMDA1G16B) \ + ) + +#define SAMDA1E ( \ + SAM_PART_IS_DEFINED(SAMDA1E14A) || \ + SAM_PART_IS_DEFINED(SAMDA1E14B) || \ + SAM_PART_IS_DEFINED(SAMDA1E15A) || \ + SAM_PART_IS_DEFINED(SAMDA1E15B) || \ + SAM_PART_IS_DEFINED(SAMDA1E16A) || \ + SAM_PART_IS_DEFINED(SAMDA1E16B) \ + ) +/** @} */ + +/** + * \name SAMHA1 series + * @{ + */ +#define SAMHA1G ( \ + SAM_PART_IS_DEFINED(SAMHA1G14A) || \ + SAM_PART_IS_DEFINED(SAMHA1G15A) || \ + SAM_PART_IS_DEFINED(SAMHA1G16A) || \ + SAM_PART_IS_DEFINED(SAMHA1G14AB) || \ + SAM_PART_IS_DEFINED(SAMHA1G15AB) || \ + SAM_PART_IS_DEFINED(SAMHA1G16AB) \ + ) + +#define SAMHA1E ( \ + SAM_PART_IS_DEFINED(SAMHA1E14A) || \ + SAM_PART_IS_DEFINED(SAMHA1E15A) || \ + SAM_PART_IS_DEFINED(SAMHA1E16A) || \ + SAM_PART_IS_DEFINED(SAMHA1E14AB) || \ + SAM_PART_IS_DEFINED(SAMHA1E15AB) || \ + SAM_PART_IS_DEFINED(SAMHA1E16AB) \ + ) + +/** @} */ + +/** + * \name SAMHA0 series + * @{ + */ +#define SAMHA0G ( \ + SAM_PART_IS_DEFINED(SAMHA0G14AB) || \ + SAM_PART_IS_DEFINED(SAMHA0G15AB) || \ + SAM_PART_IS_DEFINED(SAMHA0G16AB) \ + ) + +#define SAMHA0E ( \ + SAM_PART_IS_DEFINED(SAMHA0E14AB) || \ + SAM_PART_IS_DEFINED(SAMHA0E15AB) || \ + SAM_PART_IS_DEFINED(SAMHA0E16AB) \ + ) + +/** @} */ + +/** + * \name SAMC20 series + * @{ + */ +#define SAMC20E ( \ + SAM_PART_IS_DEFINED(SAMC20E15A) || \ + SAM_PART_IS_DEFINED(SAMC20E16A) || \ + SAM_PART_IS_DEFINED(SAMC20E17A) || \ + SAM_PART_IS_DEFINED(SAMC20E18A) \ + ) + +#define SAMC20G ( \ + SAM_PART_IS_DEFINED(SAMC20G15A) || \ + SAM_PART_IS_DEFINED(SAMC20G16A) || \ + SAM_PART_IS_DEFINED(SAMC20G17A) || \ + SAM_PART_IS_DEFINED(SAMC20G18A) \ + ) + +#define SAMC20J ( \ + SAM_PART_IS_DEFINED(SAMC20J15A) || \ + SAM_PART_IS_DEFINED(SAMC20J16A) || \ + SAM_PART_IS_DEFINED(SAMC20J17A) || \ + SAM_PART_IS_DEFINED(SAMC20J18A) \ + ) +/** @} */ + +/** + * \name SAMC21 series + * @{ + */ +#define SAMC21E ( \ + SAM_PART_IS_DEFINED(SAMC21E15A) || \ + SAM_PART_IS_DEFINED(SAMC21E16A) || \ + SAM_PART_IS_DEFINED(SAMC21E17A) || \ + SAM_PART_IS_DEFINED(SAMC21E18A) \ + ) + +#define SAMC21G ( \ + SAM_PART_IS_DEFINED(SAMC21G15A) || \ + SAM_PART_IS_DEFINED(SAMC21G16A) || \ + SAM_PART_IS_DEFINED(SAMC21G17A) || \ + SAM_PART_IS_DEFINED(SAMC21G18A) \ + ) + +#define SAMC21J ( \ + SAM_PART_IS_DEFINED(SAMC21J15A) || \ + SAM_PART_IS_DEFINED(SAMC21J16A) || \ + SAM_PART_IS_DEFINED(SAMC21J17A) || \ + SAM_PART_IS_DEFINED(SAMC21J18A) \ + ) +/** @} */ + +/** + * \name SAM4E series + * @{ + */ +#define SAM4E8 ( \ + SAM_PART_IS_DEFINED(SAM4E8C) || \ + SAM_PART_IS_DEFINED(SAM4E8CB) || \ + SAM_PART_IS_DEFINED(SAM4E8E) \ + ) + +#define SAM4E16 ( \ + SAM_PART_IS_DEFINED(SAM4E16C) || \ + SAM_PART_IS_DEFINED(SAM4E16CB) || \ + SAM_PART_IS_DEFINED(SAM4E16E) \ + ) +/** @} */ + +/** + * \name SAM4N series + * @{ + */ +#define SAM4N8 ( \ + SAM_PART_IS_DEFINED(SAM4N8A) || \ + SAM_PART_IS_DEFINED(SAM4N8B) || \ + SAM_PART_IS_DEFINED(SAM4N8C) \ + ) + +#define SAM4N16 ( \ + SAM_PART_IS_DEFINED(SAM4N16B) || \ + SAM_PART_IS_DEFINED(SAM4N16C) \ + ) +/** @} */ + +/** + * \name SAM4C series + * @{ + */ +#define SAM4C4_0 ( \ + SAM_PART_IS_DEFINED(SAM4C4C_0) \ + ) + +#define SAM4C4_1 ( \ + SAM_PART_IS_DEFINED(SAM4C4C_1) \ + ) + +#define SAM4C4 (SAM4C4_0 || SAM4C4_1) + +#define SAM4C8_0 ( \ + SAM_PART_IS_DEFINED(SAM4C8C_0) \ + ) + +#define SAM4C8_1 ( \ + SAM_PART_IS_DEFINED(SAM4C8C_1) \ + ) + +#define SAM4C8 (SAM4C8_0 || SAM4C8_1) + +#define SAM4C16_0 ( \ + SAM_PART_IS_DEFINED(SAM4C16C_0) \ + ) + +#define SAM4C16_1 ( \ + SAM_PART_IS_DEFINED(SAM4C16C_1) \ + ) + +#define SAM4C16 (SAM4C16_0 || SAM4C16_1) + +#define SAM4C32_0 ( \ + SAM_PART_IS_DEFINED(SAM4C32C_0) ||\ + SAM_PART_IS_DEFINED(SAM4C32E_0) \ + ) + +#define SAM4C32_1 ( \ + SAM_PART_IS_DEFINED(SAM4C32C_1) ||\ + SAM_PART_IS_DEFINED(SAM4C32E_1) \ + ) + + +#define SAM4C32 (SAM4C32_0 || SAM4C32_1) + +/** @} */ + +/** + * \name SAM4CM series + * @{ + */ +#define SAM4CMP8_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMP8C_0) \ + ) + +#define SAM4CMP8_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMP8C_1) \ + ) + +#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1) + +#define SAM4CMP16_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMP16C_0) \ + ) + +#define SAM4CMP16_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMP16C_1) \ + ) + +#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1) + +#define SAM4CMP32_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMP32C_0) \ + ) + +#define SAM4CMP32_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMP32C_1) \ + ) + +#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1) + +#define SAM4CMS4_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS4C_0) \ + ) + +#define SAM4CMS4_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS4C_1) \ + ) + +#define SAM4CMS4 (SAM4CMS4_0 || SAM4CMS4_1) + +#define SAM4CMS8_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS8C_0) \ + ) + +#define SAM4CMS8_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS8C_1) \ + ) + +#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1) + +#define SAM4CMS16_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS16C_0) \ + ) + +#define SAM4CMS16_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS16C_1) \ + ) + +#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1) + +#define SAM4CMS32_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS32C_0) \ + ) + +#define SAM4CMS32_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS32C_1) \ + ) + +#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1) + +/** @} */ + +/** + * \name SAM4CP series + * @{ + */ +#define SAM4CP16_0 ( \ + SAM_PART_IS_DEFINED(SAM4CP16B_0) \ + ) + +#define SAM4CP16_1 ( \ + SAM_PART_IS_DEFINED(SAM4CP16B_1) \ + ) + +#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1) +/** @} */ + +/** + * \name SAMG series + * @{ + */ +#define SAMG51 ( \ + SAM_PART_IS_DEFINED(SAMG51G18) \ + ) + +#define SAMG53 ( \ + SAM_PART_IS_DEFINED(SAMG53G19) ||\ + SAM_PART_IS_DEFINED(SAMG53N19) \ + ) + +#define SAMG54 ( \ + SAM_PART_IS_DEFINED(SAMG54G19) ||\ + SAM_PART_IS_DEFINED(SAMG54J19) ||\ + SAM_PART_IS_DEFINED(SAMG54N19) \ + ) + +#define SAMG55 ( \ + SAM_PART_IS_DEFINED(SAMG55G18) ||\ + SAM_PART_IS_DEFINED(SAMG55G19) ||\ + SAM_PART_IS_DEFINED(SAMG55J18) ||\ + SAM_PART_IS_DEFINED(SAMG55J19) ||\ + SAM_PART_IS_DEFINED(SAMG55N19) \ + ) +/** @} */ + +/** + * \name SAMV71 series + * @{ + */ +#define SAMV71J ( \ + SAM_PART_IS_DEFINED(SAMV71J19) || \ + SAM_PART_IS_DEFINED(SAMV71J20) || \ + SAM_PART_IS_DEFINED(SAMV71J21) \ + ) + +#define SAMV71JB ( \ + SAM_PART_IS_DEFINED(SAMV71J19B) || \ + SAM_PART_IS_DEFINED(SAMV71J20B) || \ + SAM_PART_IS_DEFINED(SAMV71J21B) \ + ) + +#define SAMV71N ( \ + SAM_PART_IS_DEFINED(SAMV71N19) || \ + SAM_PART_IS_DEFINED(SAMV71N20) || \ + SAM_PART_IS_DEFINED(SAMV71N21) \ + ) + +#define SAMV71NB ( \ + SAM_PART_IS_DEFINED(SAMV71N19B) || \ + SAM_PART_IS_DEFINED(SAMV71N20B) || \ + SAM_PART_IS_DEFINED(SAMV71N21B) \ + ) + +#define SAMV71Q ( \ + SAM_PART_IS_DEFINED(SAMV71Q19) || \ + SAM_PART_IS_DEFINED(SAMV71Q20) || \ + SAM_PART_IS_DEFINED(SAMV71Q21) \ + ) + +#define SAMV71QB ( \ + SAM_PART_IS_DEFINED(SAMV71Q19B) || \ + SAM_PART_IS_DEFINED(SAMV71Q20B) || \ + SAM_PART_IS_DEFINED(SAMV71Q21B) \ + ) + +/** @} */ + +/** + * \name SAMV70 series + * @{ + */ +#define SAMV70J ( \ + SAM_PART_IS_DEFINED(SAMV70J19) || \ + SAM_PART_IS_DEFINED(SAMV70J20) \ + ) + +#define SAMV70JB ( \ + SAM_PART_IS_DEFINED(SAMV70J19B) || \ + SAM_PART_IS_DEFINED(SAMV70J20B) \ + ) + +#define SAMV70N ( \ + SAM_PART_IS_DEFINED(SAMV70N19) || \ + SAM_PART_IS_DEFINED(SAMV70N20) \ + ) + +#define SAMV70NB ( \ + SAM_PART_IS_DEFINED(SAMV70N19B) || \ + SAM_PART_IS_DEFINED(SAMV70N20B) \ + ) + +#define SAMV70Q ( \ + SAM_PART_IS_DEFINED(SAMV70Q19) || \ + SAM_PART_IS_DEFINED(SAMV70Q20) \ + ) +#define SAMV70QB ( \ + SAM_PART_IS_DEFINED(SAMV70Q19B) || \ + SAM_PART_IS_DEFINED(SAMV70Q20B) \ + ) +/** @} */ + +/** + * \name SAMS70 series + * @{ + */ +#define SAMS70J ( \ + SAM_PART_IS_DEFINED(SAMS70J19) || \ + SAM_PART_IS_DEFINED(SAMS70J20) || \ + SAM_PART_IS_DEFINED(SAMS70J21) \ + ) + +#define SAMS70JB ( \ + SAM_PART_IS_DEFINED(SAMS70J19B) || \ + SAM_PART_IS_DEFINED(SAMS70J20B) || \ + SAM_PART_IS_DEFINED(SAMS70J21B) \ + ) + +#define SAMS70N ( \ + SAM_PART_IS_DEFINED(SAMS70N19) || \ + SAM_PART_IS_DEFINED(SAMS70N20) || \ + SAM_PART_IS_DEFINED(SAMS70N21) \ + ) + +#define SAMS70NB ( \ + SAM_PART_IS_DEFINED(SAMS70N19B) || \ + SAM_PART_IS_DEFINED(SAMS70N20B) || \ + SAM_PART_IS_DEFINED(SAMS70N21B) \ + ) + +#define SAMS70Q ( \ + SAM_PART_IS_DEFINED(SAMS70Q19) || \ + SAM_PART_IS_DEFINED(SAMS70Q20) || \ + SAM_PART_IS_DEFINED(SAMS70Q21) \ + ) + +#define SAMS70QB ( \ + SAM_PART_IS_DEFINED(SAMS70Q19B) || \ + SAM_PART_IS_DEFINED(SAMS70Q20B) || \ + SAM_PART_IS_DEFINED(SAMS70Q21B) \ + ) +/** @} */ + +/** + * \name SAME70 series + * @{ + */ +#define SAME70J ( \ + SAM_PART_IS_DEFINED(SAME70J19) || \ + SAM_PART_IS_DEFINED(SAME70J20) || \ + SAM_PART_IS_DEFINED(SAME70J21) \ + ) + +#define SAME70JB ( \ + SAM_PART_IS_DEFINED(SAME70J19B) || \ + SAM_PART_IS_DEFINED(SAME70J20B) || \ + SAM_PART_IS_DEFINED(SAME70J21B) \ + ) + +#define SAME70N ( \ + SAM_PART_IS_DEFINED(SAME70N19) || \ + SAM_PART_IS_DEFINED(SAME70N20) || \ + SAM_PART_IS_DEFINED(SAME70N21) \ + ) + +#define SAME70NB ( \ + SAM_PART_IS_DEFINED(SAME70N19B) || \ + SAM_PART_IS_DEFINED(SAME70N20B) || \ + SAM_PART_IS_DEFINED(SAME70N21B) \ + ) + +#define SAME70Q ( \ + SAM_PART_IS_DEFINED(SAME70Q19) || \ + SAM_PART_IS_DEFINED(SAME70Q20) || \ + SAM_PART_IS_DEFINED(SAME70Q21) \ + ) + +#define SAME70QB ( \ + SAM_PART_IS_DEFINED(SAME70Q19B) || \ + SAM_PART_IS_DEFINED(SAME70Q20B) || \ + SAM_PART_IS_DEFINED(SAME70Q21B) \ + ) +/** @} */ + +/** + * \name SAM families + * @{ + */ +/** SAM3S Family */ +#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8) + +/** SAM3U Family */ +#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4) + +/** SAM3N Family */ +#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4) + +/** SAM3XA Family */ +#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8) + +/** SAM4S Family */ +#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32) + +/** SAM4L Family */ +#define SAM4L (SAM4LS || SAM4LC) + +/** SAMD20 Family */ +#define SAMD20 (SAMD20J || SAMD20G || SAMD20E) + +/** SAMD21 Family */ +#define SAMD21 (SAMD21J || SAMD21G || SAMD21E) + +/** SAMD09 Family */ +#define SAMD09 (SAMD09C || SAMD09D) + +/** SAMD10 Family */ +#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM || SAMD10DU) + +/** SAMD11 Family */ +#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM || SAMD11DU) + +/** SAMDA1 Family */ +#define SAMDA1 (SAMDA1J || SAMDA1G || SAMDA1E) + +/** SAMHA1 Family */ +#define SAMHA1 (SAMHA1G || SAMHA1E) + +/** SAMHA0 Family */ +#define SAMHA0 (SAMHA0G || SAMHA0E) + +/** SAMD Family */ +#define SAMD (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAMDA1) + +/** SAMR21 Family */ +#define SAMR21 (SAMR21G || SAMR21E) + +/** SAMR30 Family */ +#define SAMR30 (SAMR30G || SAMR30E) + +/** SAMR34 Family */ +#define SAMR34 (SAMR34J) + +/** SAMR35 Family */ +#define SAMR35 (SAMR35J) + +/** SAMR35 Family */ +#define WLR089 (WLR089U) + +/** SAMB11 Family */ +#define SAMB11 (SAMB11G || BTLC1000) + +/** SAML21 Family */ +#define SAML21 (SAML21J || SAML21G || SAML21E) + +/** SAML22 Family */ +#define SAML22 (SAML22J || SAML22G || SAML22N) +/** SAMC20 Family */ +#define SAMC20 (SAMC20J || SAMC20G || SAMC20E) + +/** SAMC21 Family */ +#define SAMC21 (SAMC21J || SAMC21G || SAMC21E) + +/** SAM4E Family */ +#define SAM4E (SAM4E8 || SAM4E16) + +/** SAM4N Family */ +#define SAM4N (SAM4N8 || SAM4N16) + +/** SAM4C Family */ +#define SAM4C_0 (SAM4C4_0 || SAM4C8_0 || SAM4C16_0 || SAM4C32_0) +#define SAM4C_1 (SAM4C4_1 || SAM4C8_1 || SAM4C16_1 || SAM4C32_1) +#define SAM4C (SAM4C4 || SAM4C8 || SAM4C16 || SAM4C32) + +/** SAM4CM Family */ +#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || \ + SAM4CMS4_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0) +#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || \ + SAM4CMS4_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1) +#define SAM4CM (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || \ + SAM4CMS4 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32) + +/** SAM4CP Family */ +#define SAM4CP_0 (SAM4CP16_0) +#define SAM4CP_1 (SAM4CP16_1) +#define SAM4CP (SAM4CP16) + +/** SAMG Family */ +#define SAMG (SAMG51 || SAMG53 || SAMG54 || SAMG55) + +/** SAMB Family */ +#define SAMB (SAMB11) + +/** SAMV71 Family */ +#define SAMV71 (SAMV71J || SAMV71N || SAMV71Q || SAMV71JB || SAMV71NB || SAMV71QB) +#define SAMV71B (SAMV71JB || SAMV71NB || SAMV71QB) + +/** SAMV70 Family */ +#define SAMV70 (SAMV70J || SAMV70N || SAMV70Q || SAMV70JB || SAMV70NB || SAMV70QB) +#define SAMV70B (SAMV70JB || SAMV70NB || SAMV70QB) + +/** SAME70 Family */ +#define SAME70 (SAME70J || SAME70N || SAME70Q || SAME70JB || SAME70NB || SAME70QB) +#define SAME70B (SAME70JB || SAME70NB || SAME70QB) + +/** SAMS70 Family */ +#define SAMS70 (SAMS70J || SAMS70N || SAMS70Q || SAMS70JB || SAMS70NB || SAMS70QB) +#define SAMS70B (SAMS70JB || SAMS70NB || SAMS70QB) + +/** SAM0 product line (cortex-m0+) */ +#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21 ||\ + SAMDA1 || SAMC20 || SAMC21 || SAML22 || SAMD09 || SAMR30 || SAMHA1 ||\ + SAMHA0 || SAMR34 || SAMR35 || WLR089) + +/** @} */ + +/** SAM product line */ +#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \ + SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAME70 || SAMS70) + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* ATMEL_PARTS_H */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/read.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/read.c new file mode 100644 index 00000000..3812bd75 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/read.c @@ -0,0 +1,164 @@ +/** + * \file + * + * \brief System-specific implementation of the \ref _read function used by + * the standard library. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "compiler.h" + +/** + * \defgroup group_common_utils_stdio Standard I/O (stdio) + * + * Common standard I/O driver that implements the stdio + * read and write functions on AVR and SAM devices. + * + * \{ + */ + +extern volatile void *volatile stdio_base; +void (*ptr_get)(void volatile*, char*); + + +// IAR common implementation +#if ( defined(__ICCAVR32__) || defined(__ICCAVR__) || defined(__ICCARM__) ) + +#include + +#if (__VER__ < 8010000) +// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf +_STD_BEGIN +#endif + + +#pragma module_name = "?__read" + +/*! \brief Reads a number of bytes, at most \a size, into the memory area + * pointed to by \a buffer. + * + * \param handle File handle to read from. + * \param buffer Pointer to buffer to write read bytes to. + * \param size Number of bytes to read. + * + * \return The number of bytes read, \c 0 at the end of the file, or + * \c _LLIO_ERROR on failure. + */ +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + int nChars = 0; + // This implementation only reads from stdin. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDIN) { + return _LLIO_ERROR; + } + for (; size > 0; --size) { + ptr_get(stdio_base, (char*)buffer); + buffer++; + nChars++; + } + return nChars; +} + +/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 + * the implementation is empty to be compatible with old IAR version. + */ +int __close(int handle) +{ + UNUSED(handle); + return 0; +} + +/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 + * the implementation is empty to be compatible with old IAR version. + */ +int remove(const char* val) +{ + UNUSED(val); + return 0; +} + +/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 + * the implementation is empty to be compatible with old IAR version. + */ +long __lseek(int handle, long val, int val2) +{ + UNUSED(handle); + UNUSED(val2); + return val; +} + +#if (__VER__ < 8010000) +// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf +_STD_END +#endif + +// GCC AVR32 and SAM implementation +#elif (defined(__GNUC__) && !XMEGA && !MEGA) + +int __attribute__((weak)) +_read (int file, char * ptr, int len); // Remove GCC compiler warning + +int __attribute__((weak)) +_read (int file, char * ptr, int len) +{ + int nChars = 0; + + if (file != 0) { + return -1; + } + + for (; len > 0; --len) { + ptr_get(stdio_base, ptr); + ptr++; + nChars++; + } + return nChars; +} + +// GCC AVR implementation +#elif (defined(__GNUC__) && (XMEGA || MEGA) ) + +int _read (int *f); // Remove GCC compiler warning + +int _read (int *f) +{ + char c; + ptr_get(stdio_base,&c); + return c; +} +#endif + +/** + * \} + */ + diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h new file mode 100644 index 00000000..86aeadd5 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h @@ -0,0 +1,119 @@ +/** + * + * \file + * + * \brief Common Standard I/O Serial Management. + * + * This file defines a useful set of functions for the Stdio Serial interface on AVR + * and SAM devices. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + ******************************************************************************/ +/* + * Support and FAQ: visit Microchip Support + */ + + +#ifndef _STDIO_SERIAL_H_ +#define _STDIO_SERIAL_H_ + +/** + * \defgroup group_common_utils_stdio_stdio_serial Standard serial I/O (stdio) + * \ingroup group_common_utils_stdio + * + * Common standard serial I/O management driver that + * implements a stdio serial interface on AVR and SAM devices. + * + * \{ + */ + +#include +#include "compiler.h" +#ifndef SAMD20 +# include "sysclk.h" +#endif +#include "serial.h" + +#if (XMEGA || MEGA_RF) && defined(__GNUC__) + extern int _write (char c, int *f); + extern int _read (int *f); +#endif + + +//! Pointer to the base of the USART module instance to use for stdio. +extern volatile void *volatile stdio_base; +//! Pointer to the external low level write function. +extern int (*ptr_put)(void volatile*, char); + +//! Pointer to the external low level read function. +extern void (*ptr_get)(void volatile*, char*); + +/*! \brief Initializes the stdio in Serial Mode. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * + */ +static inline void stdio_serial_init(volatile void *usart, const usart_serial_options_t *opt) +{ + stdio_base = (void *)usart; + ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar; + ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar; +# if (XMEGA || MEGA_RF) + usart_serial_init((USART_t *)usart,opt); +# elif UC3 + usart_serial_init(usart,(usart_serial_options_t *)opt); +# elif SAM + usart_serial_init((Usart *)usart,(usart_serial_options_t *)opt); +# else +# error Unsupported chip type +# endif + +# if defined(__GNUC__) +# if (XMEGA || MEGA_RF) + // For AVR GCC libc print redirection uses fdevopen. + fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read)); +# endif +# if UC3 || SAM + // For AVR32 and SAM GCC + // Specify that stdout and stdin should not be buffered. + setbuf(stdout, NULL); + setbuf(stdin, NULL); + // Note: Already the case in IAR's Normal DLIB default configuration + // and AVR GCC library: + // - printf() emits one character at a time. + // - getchar() requests only 1 byte to exit. +# endif +# endif +} + +/** + * \} + */ + +#endif // _STDIO_SERIAL_H_ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/write.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/write.c new file mode 100644 index 00000000..3765ed05 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/write.c @@ -0,0 +1,143 @@ +/** + * \file + * + * \brief System-specific implementation of the \ref _write function used by + * the standard library. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "compiler.h" + +/** + * \addtogroup group_common_utils_stdio + * + * \{ + */ + +volatile void *volatile stdio_base; +int (*ptr_put)(void volatile*, char); + + +#if ( defined(__ICCAVR32__) || defined(__ICCAVR__) || defined(__ICCARM__)) + +#include + +#if (__VER__ < 8010000) +// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf +_STD_BEGIN +#endif + +#pragma module_name = "?__write" + +/*! \brief Writes a number of bytes, at most \a size, from the memory area + * pointed to by \a buffer. + * + * If \a buffer is zero then \ref __write performs flushing of internal buffers, + * if any. In this case, \a handle can be \c -1 to indicate that all handles + * should be flushed. + * + * \param handle File handle to write to. + * \param buffer Pointer to buffer to read bytes to write from. + * \param size Number of bytes to write. + * + * \return The number of bytes written, or \c _LLIO_ERROR on failure. + */ +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + size_t nChars = 0; + + if (buffer == 0) { + // This means that we should flush internal buffers. + return 0; + } + + // This implementation only writes to stdout and stderr. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { + return _LLIO_ERROR; + } + + for (; size != 0; --size) { + if (ptr_put(stdio_base, *buffer++) < 0) { + return _LLIO_ERROR; + } + ++nChars; + } + return nChars; +} + +#if (__VER__ < 8010000) +// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf +_STD_END +#endif + + +#elif (defined(__GNUC__) && !XMEGA && !MEGA) + +int __attribute__((weak)) +_write (int file, const char *ptr, int len); + +int __attribute__((weak)) +_write (int file, const char *ptr, int len) +{ + int nChars = 0; + + if ((file != 1) && (file != 2) && (file!=3)) { + return -1; + } + + for (; len != 0; --len) { + if (ptr_put(stdio_base, *ptr++) < 0) { + return -1; + } + ++nChars; + } + return nChars; +} + +#elif (defined(__GNUC__) && (XMEGA || MEGA)) + +int _write (char c, int *f); + +int _write (char c, int *f) +{ + if (ptr_put(stdio_base, c) < 0) { + return -1; + } + return 1; +} +#endif + +/** + * \} + */ + diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/init.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/init.c new file mode 100644 index 00000000..d4e4c655 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/init.c @@ -0,0 +1,600 @@ +/** + * \file + * + * \brief SAME70-XPLD board init. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "compiler.h" +#include "board.h" +#include "conf_board.h" +#include "ioport.h" +#include "pio.h" +#ifdef CONF_BOARD_CONFIG_MPU_AT_INIT +#include "mpu.h" +#endif + +/** + * \brief Set peripheral mode for IOPORT pins. + * It will configure port mode and disable pin mode (but enable peripheral). + * \param port IOPORT port to configure + * \param masks IOPORT pin masks to configure + * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) + */ +#define ioport_set_port_peripheral_mode(port, masks, mode) \ + do {\ + ioport_set_port_mode(port, masks, mode);\ + ioport_disable_port(port, masks);\ + } while (0) + +/** + * \brief Set peripheral mode for one single IOPORT pin. + * It will configure port mode and disable pin mode (but enable peripheral). + * \param pin IOPORT pin to configure + * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) + */ +#define ioport_set_pin_peripheral_mode(pin, mode) \ + do {\ + ioport_set_pin_mode(pin, mode);\ + ioport_disable_pin(pin);\ + } while (0) + +/** + * \brief Set input mode for one single IOPORT pin. + * It will configure port mode and disable pin mode (but enable peripheral). + * \param pin IOPORT pin to configure + * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) + * \param sense Sense for interrupt detection (\ref ioport_sense) + */ +#define ioport_set_pin_input_mode(pin, mode, sense) \ + do {\ + ioport_set_pin_dir(pin, IOPORT_DIR_INPUT);\ + ioport_set_pin_mode(pin, mode);\ + ioport_set_pin_sense_mode(pin, sense);\ + } while (0) + + +#ifdef CONF_BOARD_CONFIG_MPU_AT_INIT +/** + * Default memory map + * Address range Memory region Memory type Shareability Cache policy + * 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT + * 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA + * 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - + * 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA + * 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT + * 0xA0000000- 0xBFFFFFFF Device Device Shareable + * 0xC0000000- 0xDFFFFFFF Device Device Non Shareable + * 0xE0000000- 0xFFFFFFFF System - - + */ + +/** + * \brief Set up a memory region. + */ +static void _setup_memory_region( void ) +{ + + uint32_t dw_region_base_addr; + uint32_t dw_region_attr; + + __DMB(); + +/** + * ITCM memory region --- Normal + * START_Addr:- 0x00000000UL + * END_Addr:- 0x00400000UL + */ + dw_region_base_addr = + ITCM_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_ITCM_REGION; + + dw_region_attr = + MPU_AP_PRIVILEGED_READ_WRITE | + mpu_cal_mpu_region_size(ITCM_END_ADDRESS - ITCM_START_ADDRESS) | + MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +/** + * Internal flash memory region --- Normal read-only + * (update to Strongly ordered in write accesses) + * START_Addr:- 0x00400000UL + * END_Addr:- 0x00600000UL + */ + + dw_region_base_addr = + IFLASH_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_IFLASH_REGION; + + dw_region_attr = + MPU_AP_READONLY | + INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | + mpu_cal_mpu_region_size(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) | + MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +/** + * DTCM memory region --- Normal + * START_Addr:- 0x20000000L + * END_Addr:- 0x20400000UL + */ + + /* DTCM memory region */ + dw_region_base_addr = + DTCM_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_DTCM_REGION; + + dw_region_attr = + MPU_AP_PRIVILEGED_READ_WRITE | + mpu_cal_mpu_region_size(DTCM_END_ADDRESS - DTCM_START_ADDRESS) | + MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +/** + * SRAM Cacheable memory region --- Normal + * START_Addr:- 0x20400000UL + * END_Addr:- 0x2043FFFFUL + */ + /* SRAM memory region */ + dw_region_base_addr = + SRAM_FIRST_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_SRAM_REGION_1; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | + mpu_cal_mpu_region_size(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS) + | MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + + +/** + * Internal SRAM second partition memory region --- Normal + * START_Addr:- 0x20440000UL + * END_Addr:- 0x2045FFFFUL + */ + /* SRAM memory region */ + dw_region_base_addr = + SRAM_SECOND_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_SRAM_REGION_2; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | + mpu_cal_mpu_region_size(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) | + MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +#ifdef MPU_HAS_NOCACHE_REGION + dw_region_base_addr = + SRAM_NOCACHE_START_ADDRESS | + MPU_REGION_VALID | + MPU_NOCACHE_SRAM_REGION; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + INNER_OUTER_NORMAL_NOCACHE_TYPE( SHAREABLE ) | + mpu_cal_mpu_region_size(NOCACHE_SRAM_REGION_SIZE) | + MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); +#endif + +/** + * Peripheral memory region --- DEVICE Shareable + * START_Addr:- 0x40000000UL + * END_Addr:- 0x5FFFFFFFUL + */ + dw_region_base_addr = + PERIPHERALS_START_ADDRESS | + MPU_REGION_VALID | + MPU_PERIPHERALS_REGION; + + dw_region_attr = MPU_AP_FULL_ACCESS | + MPU_REGION_EXECUTE_NEVER | + SHAREABLE_DEVICE_TYPE | + mpu_cal_mpu_region_size(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS) + |MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + + +/** + * External EBI memory memory region --- Strongly Ordered + * START_Addr:- 0x60000000UL + * END_Addr:- 0x6FFFFFFFUL + */ + dw_region_base_addr = + EXT_EBI_START_ADDRESS | + MPU_REGION_VALID | + MPU_EXT_EBI_REGION; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + /* External memory Must be defined with 'Device' or 'Strongly Ordered' attribute for write accesses (AXI) */ + STRONGLY_ORDERED_SHAREABLE_TYPE | + mpu_cal_mpu_region_size(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) | + MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +/** + * SDRAM cacheable memory region --- Normal + * START_Addr:- 0x70000000UL + * END_Addr:- 0x7FFFFFFFUL + */ + dw_region_base_addr = + SDRAM_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_SDRAM_REGION; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + INNER_NORMAL_WB_RWA_TYPE( SHAREABLE ) | + mpu_cal_mpu_region_size(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) | + MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +/** + * QSPI memory region --- Strongly ordered + * START_Addr:- 0x80000000UL + * END_Addr:- 0x9FFFFFFFUL + */ + dw_region_base_addr = + QSPI_START_ADDRESS | + MPU_REGION_VALID | + MPU_QSPIMEM_REGION; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + STRONGLY_ORDERED_SHAREABLE_TYPE | + mpu_cal_mpu_region_size(QSPI_END_ADDRESS - QSPI_START_ADDRESS) | + MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + + +/** + * USB RAM Memory region --- Device + * START_Addr:- 0xA0100000UL + * END_Addr:- 0xA01FFFFFUL + */ + dw_region_base_addr = + USBHSRAM_START_ADDRESS | + MPU_REGION_VALID | + MPU_USBHSRAM_REGION; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + MPU_REGION_EXECUTE_NEVER | + SHAREABLE_DEVICE_TYPE | + mpu_cal_mpu_region_size(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) | + MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + + + /* Enable the memory management fault , Bus Fault, Usage Fault exception */ + SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk + | SCB_SHCSR_USGFAULTENA_Msk); + + /* Enable the MPU region */ + mpu_enable( MPU_ENABLE | MPU_PRIVDEFENA); + + __DSB(); + __ISB(); +} +#endif + +#ifdef CONF_BOARD_ENABLE_TCM_AT_INIT +#if defined(__GNUC__) +extern char _itcm_lma, _sitcm, _eitcm; +#endif + +/** \brief TCM memory enable +* The function enables TCM memories +*/ +static inline void tcm_enable(void) +{ + + __DSB(); + __ISB(); + + SCB->ITCMCR = (SCB_ITCMCR_EN_Msk | SCB_ITCMCR_RMW_Msk | SCB_ITCMCR_RETEN_Msk); + SCB->DTCMCR = ( SCB_DTCMCR_EN_Msk | SCB_DTCMCR_RMW_Msk | SCB_DTCMCR_RETEN_Msk); + + __DSB(); + __ISB(); +} +#else +/** \brief TCM memory Disable + + The function enables TCM memories + */ +static inline void tcm_disable(void) +{ + + __DSB(); + __ISB(); + SCB->ITCMCR &= ~(uint32_t)(1UL); + SCB->DTCMCR &= ~(uint32_t)SCB_DTCMCR_EN_Msk; + __DSB(); + __ISB(); +} +#endif + +void board_init(void) +{ +#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT + /* Disable the watchdog */ + WDT->WDT_MR = WDT_MR_WDDIS; +#endif + +#ifdef CONF_BOARD_CONFIG_MPU_AT_INIT + _setup_memory_region(); +#endif + +#ifdef CONF_BOARD_ENABLE_CACHE + /* Enabling the Cache */ + SCB_EnableICache(); + SCB_EnableDCache(); +#endif + +#ifdef CONF_BOARD_ENABLE_TCM_AT_INIT + /* TCM Configuration */ + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB + | EEFC_FCR_FARG(8)); + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SGPB + | EEFC_FCR_FARG(7)); + tcm_enable(); +#if defined(__GNUC__) + volatile char *dst = &_sitcm; + volatile char *src = &_itcm_lma; + /* copy code_TCM from flash to ITCM */ + while(dst < &_eitcm){ + *dst++ = *src++; + } +#endif +#else + /* TCM Configuration */ + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB + | EEFC_FCR_FARG(8)); + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB + | EEFC_FCR_FARG(7)); + + tcm_disable(); +#endif + + /* Initialize IOPORTs */ + ioport_init(); + + /* Configure the pins connected to LED as output and set their + * default initial state to high (LED off). + */ + ioport_set_pin_dir(LED0_GPIO, IOPORT_DIR_OUTPUT); + ioport_set_pin_level(LED0_GPIO, LED0_INACTIVE_LEVEL); + + /* Configure Push Button pins */ + ioport_set_pin_input_mode(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS, + GPIO_PUSH_BUTTON_1_SENSE); + +#ifdef CONF_BOARD_UART_CONSOLE + /* Configure UART pins */ + ioport_set_pin_peripheral_mode(USART1_RXD_GPIO, USART1_RXD_FLAGS); + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; + ioport_set_pin_peripheral_mode(USART1_TXD_GPIO, USART1_TXD_FLAGS); +#endif + +#ifdef CONF_BOARD_TWIHS0 + ioport_set_pin_peripheral_mode(TWIHS0_DATA_GPIO, TWIHS0_DATA_FLAGS); + ioport_set_pin_peripheral_mode(TWIHS0_CLK_GPIO, TWIHS0_CLK_FLAGS); +#endif + + +#ifdef CONF_BOARD_CAN0 + /* Configure the CAN0 TX and RX pins. */ + ioport_set_pin_peripheral_mode(PIN_CAN0_RX_IDX, PIN_CAN0_RX_FLAGS); + ioport_set_pin_peripheral_mode(PIN_CAN0_TX_IDX, PIN_CAN0_TX_FLAGS); + /* Configure the transiver0 RS & EN pins. */ + ioport_set_pin_dir(PIN_CAN0_TR_RS_IDX, IOPORT_DIR_OUTPUT); + ioport_set_pin_dir(PIN_CAN0_TR_EN_IDX, IOPORT_DIR_OUTPUT); +#endif + +#ifdef CONF_BOARD_CAN1 + /* Configure the CAN1 TX and RX pin. */ + ioport_set_pin_peripheral_mode(PIN_CAN1_RX_IDX, PIN_CAN1_RX_FLAGS); + ioport_set_pin_peripheral_mode(PIN_CAN1_TX_IDX, PIN_CAN1_TX_FLAGS); + +#endif + + +#ifdef CONF_BOARD_SPI + ioport_set_pin_peripheral_mode(SPI0_MISO_GPIO, SPI0_MISO_FLAGS); + ioport_set_pin_peripheral_mode(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS); + ioport_set_pin_peripheral_mode(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS); + +#ifdef CONF_BOARD_SPI_NPCS0 + ioport_set_pin_peripheral_mode(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); +#endif + +#ifdef CONF_BOARD_SPI_NPCS1 + ioport_set_pin_peripheral_mode(SPI0_NPCS1_GPIO, SPI0_NPCS1_FLAGS); +#endif + +#endif + +#ifdef CONF_BOARD_QSPI + ioport_set_pin_peripheral_mode(QSPI_QSCK_GPIO, QSPI_QSCK_FLAGS); + ioport_set_pin_peripheral_mode(QSPI_QCS_GPIO, QSPI_QCS_FLAGS); + ioport_set_pin_peripheral_mode(QSPI_QIO0_GPIO, QSPI_QIO0_FLAGS); + ioport_set_pin_peripheral_mode(QSPI_QIO1_GPIO, QSPI_QIO1_FLAGS); + ioport_set_pin_peripheral_mode(QSPI_QIO2_GPIO, QSPI_QIO2_FLAGS); + ioport_set_pin_peripheral_mode(QSPI_QIO3_GPIO, QSPI_QIO3_FLAGS); +#endif + +#ifdef CONF_BOARD_PWM_LED0 + /* Configure PWM LED0 pin */ + ioport_set_pin_peripheral_mode(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS); +#endif + +#ifdef CONF_BOARD_PWM_LED1 + /* Configure PWM LED1 pin */ + ioport_set_pin_peripheral_mode(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS); +#endif + + +#ifdef CONF_BOARD_USART_RXD + /* Configure USART RXD pin */ + ioport_set_pin_peripheral_mode(USART0_RXD_GPIO, USART0_RXD_FLAGS); +#endif + +#ifdef CONF_BOARD_USART_TXD + /* Configure USART TXD pin */ + ioport_set_pin_peripheral_mode(USART0_TXD_GPIO, USART0_TXD_FLAGS); +#endif + +#ifdef CONF_BOARD_USART_SCK + /* Configure USART synchronous communication SCK pin */ + ioport_set_pin_peripheral_mode(PIN_USART0_SCK_IDX,PIN_USART0_SCK_FLAGS); +#endif + +#ifdef CONF_BOARD_USART_CTS + /* Configure USART synchronous communication CTS pin */ + ioport_set_pin_peripheral_mode(PIN_USART0_CTS_IDX,PIN_USART0_CTS_FLAGS); +#endif + +#ifdef CONF_BOARD_USART_RTS + /* Configure USART RTS pin */ + ioport_set_pin_peripheral_mode(PIN_USART0_RTS_IDX, PIN_USART0_RTS_FLAGS); +#endif + +#ifdef CONF_BOARD_SD_MMC_HSMCI + /* Configure HSMCI pins */ + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCDA_GPIO, PIN_HSMCI_MCCDA_FLAGS); + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCK_GPIO, PIN_HSMCI_MCCK_FLAGS); + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA0_GPIO, PIN_HSMCI_MCDA0_FLAGS); + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA1_GPIO, PIN_HSMCI_MCDA1_FLAGS); + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA2_GPIO, PIN_HSMCI_MCDA2_FLAGS); + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA3_GPIO, PIN_HSMCI_MCDA3_FLAGS); + + /* Configure SD/MMC card detect pin */ + ioport_set_pin_dir(SD_MMC_0_CD_GPIO, IOPORT_DIR_INPUT); + ioport_set_pin_mode(SD_MMC_0_CD_GPIO, SD_MMC_0_CD_FLAGS); +#endif + +#ifdef CONF_BOARD_ILI9488 + /**LCD pin configure on EBI*/ + pio_configure(PIN_EBI_RESET_PIO, PIN_EBI_RESET_TYPE, PIN_EBI_RESET_MASK, PIN_EBI_RESET_ATTRI); + pio_configure(PIN_EBI_CDS_PIO, PIN_EBI_CDS_TYPE, PIN_EBI_CDS_MASK, PIN_EBI_CDS_ATTRI); + pio_configure(PIN_EBI_DATAL_PIO, PIN_EBI_DATAL_TYPE, PIN_EBI_DATAL_MASK, PIN_EBI_DATAL_ATTRI); + pio_configure(PIN_EBI_DATAH_0_PIO, PIN_EBI_DATAH_0_TYPE, PIN_EBI_DATAH_0_MASK, PIN_EBI_DATAH_0_ATTRI); + pio_configure(PIN_EBI_DATAH_1_PIO, PIN_EBI_DATAH_1_TYPE, PIN_EBI_DATAH_1_MASK, PIN_EBI_DATAH_1_ATTRI); + pio_configure(PIN_EBI_NWE_PIO, PIN_EBI_NWE_TYPE, PIN_EBI_NWE_MASK, PIN_EBI_NWE_ATTRI); + pio_configure(PIN_EBI_NRD_PIO, PIN_EBI_NRD_TYPE, PIN_EBI_NRD_MASK, PIN_EBI_NRD_ATTRI); + pio_configure(PIN_EBI_CS_PIO, PIN_EBI_CS_TYPE, PIN_EBI_CS_MASK, PIN_EBI_CS_ATTRI); + pio_configure(PIN_EBI_BACKLIGHT_PIO, PIN_EBI_BACKLIGHT_TYPE, PIN_EBI_BACKLIGHT_MASK, PIN_EBI_BACKLIGHT_ATTRI); + pio_set(PIN_EBI_BACKLIGHT_PIO, PIN_EBI_BACKLIGHT_MASK); +#endif + +#if (defined CONF_BOARD_USB_PORT) +# if defined(CONF_BOARD_USB_VBUS_DETECT) + ioport_set_pin_dir(USB_VBUS_PIN, IOPORT_DIR_INPUT); +# endif +# if defined(CONF_BOARD_USB_ID_DETECT) + ioport_set_pin_dir(USB_ID_PIN, IOPORT_DIR_INPUT); +# endif +#endif + +#ifdef CONF_BOARD_SDRAMC + pio_configure_pin(SDRAM_BA0_PIO, SDRAM_BA0_FLAGS); + pio_configure_pin(SDRAM_SDCK_PIO, SDRAM_SDCK_FLAGS); + pio_configure_pin(SDRAM_SDCKE_PIO, SDRAM_SDCKE_FLAGS); + pio_configure_pin(SDRAM_SDCS_PIO, SDRAM_SDCS_FLAGS); + pio_configure_pin(SDRAM_RAS_PIO, SDRAM_RAS_FLAGS); + pio_configure_pin(SDRAM_CAS_PIO, SDRAM_CAS_FLAGS); + pio_configure_pin(SDRAM_SDWE_PIO, SDRAM_SDWE_FLAGS); + pio_configure_pin(SDRAM_NBS0_PIO, SDRAM_NBS0_FLAGS); + pio_configure_pin(SDRAM_NBS1_PIO, SDRAM_NBS1_FLAGS); + pio_configure_pin(SDRAM_A2_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A3_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A4_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A5_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A6_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A7_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A8_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A9_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A10_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A11_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_SDA10_PIO, SDRAM_SDA10_FLAGS); + pio_configure_pin(SDRAM_D0_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D1_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D2_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D3_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D4_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D5_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D6_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D7_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D8_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D9_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D10_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D11_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D12_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D13_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D14_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D15_PIO, SDRAM_D_FLAGS); + + MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SDRAMEN; +#endif + +#ifdef CONF_BOARD_ILI9488 + /**LCD pin configure on SPI*/ + pio_configure_pin(LCD_SPI_MISO_PIO, LCD_SPI_MISO_FLAGS); + pio_configure_pin(LCD_SPI_MOSI_PIO, LCD_SPI_MOSI_FLAGS); + pio_configure_pin(LCD_SPI_SPCK_PIO, LCD_SPI_SPCK_FLAGS); + pio_configure_pin(LCD_SPI_NPCS_PIO, LCD_SPI_NPCS_FLAGS); + pio_configure_pin(LCD_SPI_RESET_PIO, LCD_SPI_RESET_FLAGS); + pio_configure_pin(LCD_SPI_CDS_PIO, LCD_SPI_CDS_FLAGS); + pio_configure_pin(LCD_SPI_BACKLIGHT_PIO, LCD_SPI_BACKLIGHT_FLAGS); + pio_set_pin_high(LCD_SPI_BACKLIGHT_PIO); + +#endif +} diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/led.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/led.h new file mode 100644 index 00000000..ec3719c5 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/led.h @@ -0,0 +1,71 @@ +/** + * \file + * + * \brief SAME70-XPLD LEDs support package. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef LED_H_INCLUDED +#define LED_H_INCLUDED + +#include "compiler.h" +#include "ioport.h" + +/** + * \brief Turns off the specified LEDs. + * + * \param led LED to turn off (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_Off(led) ioport_set_pin_level(led##_GPIO, led##_INACTIVE_LEVEL) + +/** + * \brief Turns on the specified LEDs. + * + * \param led LED to turn on (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_On(led) ioport_set_pin_level(led##_GPIO, led##_ACTIVE_LEVEL) + +/** + * \brief Toggles the specified LEDs. + * + * \param led LED to toggle (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_Toggle(led) ioport_toggle_pin_level(led##_GPIO) + + +#endif // LED_H_INCLUDED diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/same70_xplained.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/same70_xplained.h new file mode 100644 index 00000000..d0c4a262 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/same70_xplained.h @@ -0,0 +1,659 @@ +/** + * \file + * + * \brief SAME70-XPLD Board Definition. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_XPLD_H_ +#define _SAME70_XPLD_H_ + +#include "compiler.h" +#include "system_same70.h" + +/*----------------------------------------------------------------------------*/ +/** + * \page same70_xplained_pro_opfreq "SAME70-XPLD - Operating frequencies" + * This page lists several definition related to the board operating frequency + * + * \section Definitions + * - \ref BOARD_FREQ_* + * - \ref BOARD_MCK + */ + +/** Board oscillator settings */ +#define BOARD_FREQ_SLCK_XTAL (32768U) +#define BOARD_FREQ_SLCK_BYPASS (32768U) +#define BOARD_FREQ_MAINCK_XTAL (12000000U) +#define BOARD_FREQ_MAINCK_BYPASS (12000000U) + +/** Master clock frequency */ +#define BOARD_MCK CHIP_FREQ_CPU_MAX + +/** board main clock xtal statup time */ +#define BOARD_OSC_STARTUP_US 15625 + +/*----------------------------------------------------------------------------*/ +/** + * \page same70_xplained_info "SAME70-XPLD - Board informations" + * This page lists several definition related to the board description. + * + * \section Definitions + * - \ref BOARD_NAME + */ + +/** Name of the board */ +#define BOARD_NAME "SAME70-XPLD" +/** Board definition */ +#define same70xpld +/** Family definition (already defined) */ +#define same70 +/** Core definition */ +#define cortexm7 + +/*----------------------------------------------------------------------------*/ + +#define CONSOLE_UART USART1 +#define CONSOLE_UART_ID ID_USART1 +/** USART1 pins definitions, PA21,PB4. */ +#define USART1_RXD_GPIO PIO_PA21_IDX +#define USART1_RXD_FLAGS IOPORT_MODE_MUX_A +#define USART1_TXD_GPIO PIO_PB4_IDX +#define USART1_TXD_FLAGS IOPORT_MODE_MUX_D + +/** USART0 pins definitions, PB0,PB1. */ +#define USART0_RXD_GPIO PIO_PB0_IDX +#define USART0_RXD_FLAGS IOPORT_MODE_MUX_C +#define USART0_TXD_GPIO PIO_PB1_IDX +#define USART0_TXD_FLAGS IOPORT_MODE_MUX_C + +#define PIN_USART0_SCK_IDX (PIO_PB13_IDX) +#define PIN_USART0_SCK_FLAGS (IOPORT_MODE_MUX_C) + +/** USART0 pin CTS */ +#define PIN_USART0_CTS_IDX (PIO_PB2_IDX) +#define PIN_USART0_CTS_FLAGS (IOPORT_MODE_MUX_C) + +/** USART0 pin RTS */ +#define PIN_USART0_RTS_IDX (PIO_PB3_IDX) +#define PIN_USART0_RTS_FLAGS (IOPORT_MODE_MUX_C) + + +//! \name LED definitions +//@{ +#define LED0_GPIO (PIO_PC8_IDX) +#define LED0_FLAGS (0) +#define LED0_ACTIVE_LEVEL (IOPORT_PIN_LEVEL_LOW) +#define LED0_INACTIVE_LEVEL (IOPORT_PIN_LEVEL_HIGH) + +#define LED_COUNT (1) +//@} + +//! \name SW0 definitions +//@{ +#define SW0_PIN (PIO_PA11_IDX) +#define SW0_ACTIVE (IOPORT_PIN_LEVEL_LOW) +#define SW0_INACTIVE (!SW0_ACTIVE) +#define SW0_SUPC_INPUT 2 + +/** + * Wrapper macros for SW0, to ensure common naming across all Xplained + * boards. + */ +#define PIN_SW0 {PIO_PA11, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} +#define PIN_SW0_MASK PIO_PA11 +#define PIN_SW0_PIO PIOA +#define PIN_SW0_ID ID_PIOA +#define PIN_SW0_TYPE PIO_INPUT +#define PIN_SW0_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) +//@} + +/** + * \name LED #0 definitions + * + * Wrapper macros for LED0, to ensure common naming across all Xplained + * boards. + */ +//@{ +#define LED_0_NAME "LED0 (yellow)" +#define LED_0_PIN LED0_GPIO +#define LED_0_ACTIVE LED0_ACTIVE_LEVEL +#define LED_0_INACTIVE LED0_INACTIVE_LEVEL + +#define PIN_LED_0 {PIO_PC8, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#define PIN_LED_0_MASK PIO_PC8 +#define PIN_LED_0_PIO PIOC +#define PIN_LED_0_ID ID_PIOC +#define PIN_LED_0_TYPE PIO_OUTPUT_1 +#define PIN_LED_0_ATTR PIO_DEFAULT +//@} + +/* TC-- Timer Count */ +#define PIN_TC0_TIOA0 (PIO_PA0_IDX) +#define PIN_TC0_TIOA0_MUX (IOPORT_MODE_MUX_B) +#define PIN_TC0_TIOA0_FLAGS (IOPORT_MODE_MUX_B) + +#define PIN_TC0_TIOA0_PIO PIOA +#define PIN_TC0_TIOA0_MASK PIO_PA0 +#define PIN_TC0_TIOA0_ID ID_PIOA +#define PIN_TC0_TIOA0_TYPE PIO_PERIPH_B +#define PIN_TC0_TIOA0_ATTR PIO_DEFAULT + +#define PIN_TC3_TIOA11 (PIO_PD21_IDX) +#define PIN_TC3_TIOA11_MUX (IOPORT_MODE_MUX_C) +#define PIN_TC3_TIOA11_FLAGS (IOPORT_MODE_MUX_C) + +#define PIN_TC3_TIOA11_PIO PIOD +#define PIN_TC3_TIOA11_MASK PIO_PD21 +#define PIN_TC3_TIOA11_ID ID_PIOD +#define PIN_TC3_TIOA11_TYPE PIO_PERIPH_C +#define PIN_TC3_TIOA11_ATTR PIO_DEFAULT + +//! Number of on-board LEDs +#define BOARD_NUM_OF_LED 1 + +/** + * Push button #0 definition. Attributes = pull-up + debounce + interrupt on + * rising edge. + */ +#define BUTTON_0_NAME "SW0" +#define BUTTON_0_PIN SW0_PIN +#define BUTTON_0_ACTIVE SW0_ACTIVE +#define BUTTON_0_INACTIVE SW0_INACTIVE +#define BUTTON_0_SUPC_INPUT SW0_SUPC_INPUT +#define GPIO_PUSH_BUTTON_0 BUTTON_0_PIN + +#define PUSHBUTTON_1_NAME "SW0" +#define PUSHBUTTON_1_WKUP_LINE (2) +#define PUSHBUTTON_1_WKUP_FSTT (PMC_FSMR_FSTT2) +#define GPIO_PUSH_BUTTON_1 (PIO_PA11_IDX) +#define GPIO_PUSH_BUTTON_1_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE) +#define GPIO_PUSH_BUTTON_1_SENSE (IOPORT_SENSE_RISING) + +#define PIN_PUSHBUTTON_1 {PIO_PA11, PIOA, ID_PIOA, PIO_INPUT, \ + PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} +#define PIN_PUSHBUTTON_1_MASK PIO_PA11 +#define PIN_PUSHBUTTON_1_PIO PIOA +#define PIN_PUSHBUTTON_1_ID ID_PIOA +#define PIN_PUSHBUTTON_1_TYPE PIO_INPUT +#define PIN_PUSHBUTTON_1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) +#define PIN_PUSHBUTTON_1_IRQn PIOA_IRQn + +/** List of all push button definitions. */ +#define PINS_PUSHBUTTONS {PIN_PUSHBUTTON_1} + +//! \name Extension header #1 pin definitions +//@{ +#define EXT1_PIN_3 PIO_PC31_IDX +#define EXT1_PIN_4 PIO_PA19_IDX +#define EXT1_PIN_5 PIO_PB3_IDX +#define EXT1_PIN_6 PIO_PB2_IDX +#define EXT1_PIN_7 PIO_PA0_IDX +#define EXT1_PIN_8 PIO_PC30_IDX +#define EXT1_PIN_9 PIO_PD28_IDX +#define EXT1_PIN_10 PIO_PC17_IDX +#define EXT1_PIN_11 PIO_PA3_IDX +#define EXT1_PIN_12 PIO_PA4_IDX +#define EXT1_PIN_13 PIO_PB0_IDX +#define EXT1_PIN_14 PIO_PB1_IDX +#define EXT1_PIN_15 PIO_PD25_IDX +#define EXT1_PIN_16 PIO_PD21_IDX +#define EXT1_PIN_17 PIO_PD20_IDX +#define EXT1_PIN_18 PIO_PD22_IDX +//@} + +//! \name Extension header #1 pin definitions by function +//@{ +#define EXT1_PIN_ADC_0 EXT1_PIN_3 +#define EXT1_PIN_ADC_1 EXT1_PIN_4 +#define EXT1_PIN_GPIO_0 EXT1_PIN_5 +#define EXT1_PIN_GPIO_1 EXT1_PIN_6 +#define EXT1_PIN_PWM_0 EXT1_PIN_7 +#define EXT1_PIN_PWM_1 EXT1_PIN_8 +#define EXT1_PIN_IRQ EXT1_PIN_9 +#define EXT1_PIN_TWI_SDA EXT1_PIN_11 +#define EXT1_PIN_TWI_SCL EXT1_PIN_12 +#define EXT1_PIN_UART_RX EXT1_PIN_13 +#define EXT1_PIN_UART_TX EXT1_PIN_14 +#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10 +#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15 +#define EXT1_PIN_SPI_MOSI EXT1_PIN_16 +#define EXT1_PIN_SPI_MISO EXT1_PIN_17 +#define EXT1_PIN_SPI_SCK EXT1_PIN_18 +//@} + +//! \name Extension header #2 pin definitions +//@{ +#define EXT2_PIN_3 PIO_PD30_IDX +#define EXT2_PIN_4 PIO_PC13_IDX +#define EXT2_PIN_5 PIO_PA6_IDX +#define EXT2_PIN_6 PIO_PD11_IDX +#define EXT2_PIN_7 PIO_PC19_IDX +#define EXT2_PIN_8 PIO_PD26_IDX +#define EXT2_PIN_9 PIO_PA2_IDX +#define EXT2_PIN_10 PIO_PA24_IDX +#define EXT2_PIN_11 PIO_PA3_IDX +#define EXT2_PIN_12 PIO_PA4_IDX +#define EXT2_PIN_13 PIO_PA21_IDX +#define EXT2_PIN_14 PIO_PB4_IDX +#define EXT2_PIN_15 PIO_PD27_IDX +#define EXT2_PIN_16 PIO_PD21_IDX +#define EXT2_PIN_17 PIO_PD20_IDX +#define EXT2_PIN_18 PIO_PD22_IDX +//@} + +//! \name Extension header #2 pin definitions by function +//@{ +#define EXT2_PIN_ADC_0 EXT2_PIN_3 +#define EXT2_PIN_ADC_1 EXT2_PIN_4 +#define EXT2_PIN_GPIO_0 EXT2_PIN_5 +#define EXT2_PIN_GPIO_1 EXT2_PIN_6 +#define EXT2_PIN_PWM_0 EXT2_PIN_7 +#define EXT2_PIN_PWM_1 EXT2_PIN_8 +#define EXT2_PIN_IRQ EXT2_PIN_9 +#define EXT2_PIN_TWI_SDA EXT2_PIN_11 +#define EXT2_PIN_TWI_SCL EXT2_PIN_12 +#define EXT2_PIN_UART_RX EXT2_PIN_13 +#define EXT2_PIN_UART_TX EXT2_PIN_14 +#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10 +#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15 +#define EXT2_PIN_SPI_MOSI EXT2_PIN_16 +#define EXT2_PIN_SPI_MISO EXT2_PIN_17 +#define EXT2_PIN_SPI_SCK EXT2_PIN_18 +//@} + +/** PCK0 pin definition (PA6) */ +#define PIN_PCK0 (PIO_PA6_IDX) +#define PIN_PCK0_MUX (IOPORT_MODE_MUX_B) +#define PIN_PCK0_FLAGS (IOPORT_MODE_MUX_B) +#define PIN_PCK0_PORT IOPORT_PIOA +#define PIN_PCK0_MASK PIO_PA6B_PCK0 +#define PIN_PCK0_PIO PIOA +#define PIN_PCK0_ID ID_PIOA +#define PIN_PCK0_TYPE PIO_PERIPH_B +#define PIN_PCK0_ATTR PIO_DEFAULT + + +/** TWI0 pins definition */ +#define TWIHS0_DATA_GPIO PIO_PA3_IDX +#define TWIHS0_DATA_FLAGS (IOPORT_MODE_MUX_A) +#define TWIHS0_CLK_GPIO PIO_PA4_IDX +#define TWIHS0_CLK_FLAGS (IOPORT_MODE_MUX_A) + +/** SPI0 pins definition */ +#define SPI0_MISO_GPIO PIO_PD20_IDX +#define SPI0_MISO_FLAGS (IOPORT_MODE_MUX_B) +#define SPI0_MOSI_GPIO PIO_PD21_IDX +#define SPI0_MOSI_FLAGS (IOPORT_MODE_MUX_B) +#define SPI0_NPCS0_GPIO PIO_PB2_IDX +#define SPI0_NPCS0_FLAGS (IOPORT_MODE_MUX_D) +#define SPI0_NPCS1_GPIO PIO_PD25_IDX +#define SPI0_NPCS1_FLAGS (IOPORT_MODE_MUX_B) +#define SPI0_NPCS2_GPIO PIO_PD12_IDX +#define SPI0_NPCS2_FLAGS (IOPORT_MODE_MUX_C) +#define SPI0_NPCS3_GPIO PIO_PD27_IDX +#define SPI0_NPCS3_FLAGS (IOPORT_MODE_MUX_B) +#define SPI0_SPCK_GPIO PIO_PD22_IDX +#define SPI0_SPCK_FLAGS (IOPORT_MODE_MUX_B) + +/** QSPI pins definition */ +#define QSPI_QSCK_GPIO PIO_PA14_IDX +#define QSPI_QSCK_FLAGS (IOPORT_MODE_MUX_A) +#define QSPI_QCS_GPIO PIO_PA11_IDX +#define QSPI_QCS_FLAGS (IOPORT_MODE_MUX_A) +#define QSPI_QIO0_GPIO PIO_PA13_IDX +#define QSPI_QIO0_FLAGS (IOPORT_MODE_MUX_A) +#define QSPI_QIO1_GPIO PIO_PA12_IDX +#define QSPI_QIO1_FLAGS (IOPORT_MODE_MUX_A) +#define QSPI_QIO2_GPIO PIO_PA17_IDX +#define QSPI_QIO2_FLAGS (IOPORT_MODE_MUX_A) +#define QSPI_QIO3_GPIO PIO_PD31_IDX +#define QSPI_QIO3_FLAGS (IOPORT_MODE_MUX_A) + +/** AFEC channel for potentiometer */ +#define AFEC_CHANNEL_POTENTIOMETER AFEC_CHANNEL_0 + +#define MCAN_MODULE MCAN1 +/*----------------------------------------------------------------------------*/ +/** + * \page same70_xpld_CAN "SAME70-XPLD - CAN" + * This page lists definitions related to CAN0 and CAN1. + * + * CAN + * - \ref PIN_CAN0_TRANSCEIVER_RXEN + * - \ref PIN_CAN0_TRANSCEIVER_RS + * - \ref PIN_CAN0_TXD + * - \ref PIN_CAN0_RXD + * - \ref PINS_CAN0 + * + * - \ref PIN_CAN1_TRANSCEIVER_RXEN + * - \ref PIN_CAN1_TRANSCEIVER_RS + * - \ref PIN_CAN1_TXD + * - \ref PIN_CAN1_RXD + * - \ref PINS_CAN1 + */ +/** CAN0 transceiver PIN RS. */ +#define PIN_CAN0_TR_RS_IDX PIO_PE0_IDX +#define PIN_CAN0_TR_RS_FLAGS IOPORT_DIR_OUTPUT + +/** CAN0 transceiver PIN EN. */ +#define PIN_CAN0_TR_EN_IDX PIO_PE1_IDX +#define PIN_CAN0_TR_EN_FLAGS IOPORT_DIR_OUTPUT + +/** CAN0 PIN RX. */ +#define PIN_CAN0_RX_IDX PIO_PB3_IDX +#define PIN_CAN0_RX_FLAGS IOPORT_MODE_MUX_A + +/** CAN0 PIN TX. */ +#define PIN_CAN0_TX_IDX PIO_PB2_IDX +#define PIN_CAN0_TX_FLAGS IOPORT_MODE_MUX_A + +/** CAN1 transceiver PIN RS. */ +#define PIN_CAN1_TR_RS_IDX PIO_PE2_IDX +#define PIN_CAN1_TR_RS_FLAGS IOPORT_DIR_OUTPUT + +/** CAN1 transceiver PIN EN. */ +#define PIN_CAN1_TR_EN_IDX PIO_PE3_IDX +#define PIN_CAN1_TR_EN_FLAGS IOPORT_DIR_OUTPUT + +/** CAN1 PIN RX. */ +#define PIN_CAN1_RX_IDX PIO_PC12_IDX +#define PIN_CAN1_RX_FLAGS IOPORT_MODE_MUX_C + +/** CAN1 PIN TX. */ +#define PIN_CAN1_TX_IDX PIO_PC14_IDX +#define PIN_CAN1_TX_FLAGS IOPORT_MODE_MUX_C + +/** PWM LED0 pin definitions. */ +#define PIN_PWM_LED0_GPIO PIO_PA23_IDX +#define PIN_PWM_LED0_FLAGS (IOPORT_MODE_MUX_B) +#define PIN_PWM_LED0_CHANNEL PWM_CHANNEL_0 + +/** PWM LED1 pin definitions. */ +#define PIN_PWM_LED1_GPIO PIO_PA24_IDX +#define PIN_PWM_LED1_FLAGS (IOPORT_MODE_MUX_B) +#define PIN_PWM_LED1_CHANNEL PWM_CHANNEL_1 + +/*----------------------------------------------------------------------------*/ +/** GMAC HW configurations */ +#define BOARD_GMAC_PHY_ADDR 0 + +#define PIN_GMAC_RESET_MASK PIO_PC10 +#define PIN_GMAC_RESET_PIO PIOC +#define PIN_GMAC_INT_MASK PIO_PA14 +#define PIN_GMAC_INT_PIO PIOA +#define PIN_GMAC_PERIPH PIO_PERIPH_A +#define PIN_GMAC_PIO PIOD +#define PIN_GMAC_MASK (PIO_PD0A_GTXCK | PIO_PD1A_GTXEN | PIO_PD2A_GTX0 | \ + PIO_PD3A_GTX1 | PIO_PD4A_GRXDV | PIO_PD5A_GRX0 | \ + PIO_PD6A_GRX1 | PIO_PD7A_GRXER | PIO_PD8A_GMDC | \ + PIO_PD9A_GMDIO) + +/** Board configuration of the AT24MAC EEPROM */ +#define BOARD_AT24MAC_TWIHS TWIHS0 +//#define BOARD_AT24MAC_ADDRESS (0xBE >> 1) +#define BOARD_AT24MAC_TWIHS_CLK (400000UL) +#define BOARD_AT24MAC_PAGE_SIZE 16 +#define BOARD_AT24MAC_TWIHS_INSTANCE TWIHS0 +#define BOARD_AT24MAC_ADDRESS (0xAE >> 1) +#define BOARD_CLK_TWIHS_EEPROM PIO_PA4 + +/** HSMCI pins definition. */ +/*! Number of slot connected on HSMCI interface */ +#define SD_MMC_HSMCI_MEM_CNT 1 +#define SD_MMC_HSMCI_SLOT_0_SIZE 4 +/** HSMCI MCCDA pin definition. */ +#define PIN_HSMCI_MCCDA_GPIO (PIO_PA28_IDX) +#define PIN_HSMCI_MCCDA_FLAGS (IOPORT_MODE_MUX_C) +/** HSMCI MCCK pin definition. */ +#define PIN_HSMCI_MCCK_GPIO (PIO_PA25_IDX) +#define PIN_HSMCI_MCCK_FLAGS (IOPORT_MODE_MUX_D) +/** HSMCI MCDA0 pin definition. */ +#define PIN_HSMCI_MCDA0_GPIO (PIO_PA30_IDX) +#define PIN_HSMCI_MCDA0_FLAGS (IOPORT_MODE_MUX_C) +/** HSMCI MCDA1 pin definition. */ +#define PIN_HSMCI_MCDA1_GPIO (PIO_PA31_IDX) +#define PIN_HSMCI_MCDA1_FLAGS (IOPORT_MODE_MUX_C) +/** HSMCI MCDA2 pin definition. */ +#define PIN_HSMCI_MCDA2_GPIO (PIO_PA26_IDX) +#define PIN_HSMCI_MCDA2_FLAGS (IOPORT_MODE_MUX_C) +/** HSMCI MCDA3 pin definition. */ +#define PIN_HSMCI_MCDA3_GPIO (PIO_PA27_IDX) +#define PIN_HSMCI_MCDA3_FLAGS (IOPORT_MODE_MUX_C) + +/** SD/MMC card detect pin definition. */ +#define PIN_HSMCI_CD {PIO_PC16, PIOD, ID_PIOD, PIO_INPUT, PIO_PULLUP} +#define SD_MMC_0_CD_GPIO (PIO_PC16_IDX) +#define SD_MMC_0_CD_PIO_ID ID_PIOD +#define SD_MMC_0_CD_FLAGS (IOPORT_MODE_PULLUP) +#define SD_MMC_0_CD_DETECT_VALUE 0 + +/** EBI pins configuration for LCD */ +/** LCD reset pin */ +#define PIN_EBI_RESET_MASK PIO_PC13 +#define PIN_EBI_RESET_PIO PIOC +#define PIN_EBI_RESET_TYPE PIO_OUTPUT_1 +#define PIN_EBI_RESET_ATTRI PIO_DEFAULT + +/** LCD command/data select pin */ +#define PIN_EBI_CDS_MASK PIO_PC30 +#define PIN_EBI_CDS_PIO PIOC +#define PIN_EBI_CDS_TYPE PIO_OUTPUT_1 +#define PIN_EBI_CDS_ATTRI PIO_DEFAULT + +/** LCD data pin */ +#define PIN_EBI_DATAL_MASK 0xFF +#define PIN_EBI_DATAL_PIO PIOC +#define PIN_EBI_DATAL_TYPE PIO_PERIPH_A +#define PIN_EBI_DATAL_ATTRI PIO_PULLUP + +#define PIN_EBI_DATAH_0_MASK 0x3F +#define PIN_EBI_DATAH_0_PIO PIOE +#define PIN_EBI_DATAH_0_TYPE PIO_PERIPH_A +#define PIN_EBI_DATAH_0_ATTRI PIO_PULLUP + +#define PIN_EBI_DATAH_1_MASK (PIO_PA15A_D14|PIO_PA16A_D15) +#define PIN_EBI_DATAH_1_PIO PIOA +#define PIN_EBI_DATAH_1_TYPE PIO_PERIPH_A +#define PIN_EBI_DATAH_1_ATTRI PIO_PULLUP + +/** LCD WE pin */ +#define PIN_EBI_NWE_MASK PIO_PC8A_NWE +#define PIN_EBI_NWE_PIO PIOC +#define PIN_EBI_NWE_TYPE PIO_PERIPH_A +#define PIN_EBI_NWE_ATTRI PIO_PULLUP + +/** LCD RD pin */ +#define PIN_EBI_NRD_MASK PIO_PC11A_NRD +#define PIN_EBI_NRD_PIO PIOC +#define PIN_EBI_NRD_TYPE PIO_PERIPH_A +#define PIN_EBI_NRD_ATTRI PIO_PULLUP + +/** LCD CS pin (NCS3) */ +#define PIN_EBI_CS_MASK PIO_PD19A_NCS3 +#define PIN_EBI_CS_PIO PIOD +#define PIN_EBI_CS_TYPE PIO_PERIPH_A +#define PIN_EBI_CS_ATTRI PIO_PULLUP + +/** Back-light pin definition. */ +#define PIN_EBI_BACKLIGHT_MASK PIO_PC9B_TIOB7 +#define PIN_EBI_BACKLIGHT_PIO PIOC +#define PIN_EBI_BACKLIGHT_TYPE PIO_PERIPH_B +#define PIN_EBI_BACKLIGHT_ATTRI PIO_DEFAULT + +/*! \name GPIO Connections of VBUS monitoring + */ +//! @{ +#define USB_VBUS_FLAGS (PIO_INPUT | PIO_PULLUP) +#define USB_VBUS_PIN PIO_PC9_IDX /* As IO pin input */ +#define USB_VBUS_PIN_IRQn ( PIOC_IRQn) +#define USB_VBUS_PIO_ID ID_PIOC +#define USB_VBUS_PIO_MASK PIO_PC9 +//! @} + +/*! \name GPIO Connections of ID detecting + */ +//! @{ +#define USB_ID_FLAGS (PIO_INPUT | PIO_PULLUP) +#define USB_ID_PIN PIO_PC16_IDX /* As IO pin input */ +#define USB_ID_PIN_IRQn (PIOC_IRQn) +#define USB_ID_PIO_ID ID_PIOC +#define USB_ID_PIO_MASK PIO_PC16 +//! @} + +/** WM8904 Slave address */ +#define WM8904_SLAVE_ADDRESS (0x34 >> 1) + +/** TWI interface for WM8904 */ +#define WM8904_TWIHS TWIHS0 + +/** WM8904 pins definition */ +#define WM8904_TK_PIO PIO_PB1_IDX +#define WM8904_TK_FLAGS PIO_PERIPH_D +#define WM8904_TF_PIO PIO_PB0_IDX +#define WM8904_TF_FLAGS PIO_PERIPH_D +#define WM8904_TD_PIO PIO_PD26_IDX +#define WM8904_TD_FLAGS PIO_PERIPH_B +#define WM8904_RK_PIO PIO_PA22_IDX +#define WM8904_RK_FLAGS PIO_PERIPH_A +#define WM8904_RF_PIO PIO_PD24_IDX +#define WM8904_RF_FLAGS PIO_PERIPH_B +#define WM8904_RD_PIO PIO_PA10_IDX +#define WM8904_RD_FLAGS PIO_PERIPH_C +#define WM8904_PCK2_PIO PIO_PA18_IDX +#define WM8904_PCK2_FLAGS PIO_PERIPH_B + +/** Board SDRAM size for MT48LC16M16A2 */ +#define BOARD_SDRAM_SIZE (2 * 1024 * 1024) + +/** Address for transferring command bytes to the SDRAM. */ +#define BOARD_SDRAM_ADDR 0x70000000 + +/** SDRAM pins definitions */ +#define SDRAM_BA0_PIO PIO_PA20_IDX +#define SDRAM_SDCK_PIO PIO_PD23_IDX +#define SDRAM_SDCKE_PIO PIO_PD14_IDX +#define SDRAM_SDCS_PIO PIO_PC15_IDX +#define SDRAM_RAS_PIO PIO_PD16_IDX +#define SDRAM_CAS_PIO PIO_PD17_IDX +#define SDRAM_SDWE_PIO PIO_PD29_IDX +#define SDRAM_NBS0_PIO PIO_PC18_IDX +#define SDRAM_NBS1_PIO PIO_PD15_IDX +#define SDRAM_A2_PIO PIO_PC20_IDX +#define SDRAM_A3_PIO PIO_PC21_IDX +#define SDRAM_A4_PIO PIO_PC22_IDX +#define SDRAM_A5_PIO PIO_PC23_IDX +#define SDRAM_A6_PIO PIO_PC24_IDX +#define SDRAM_A7_PIO PIO_PC25_IDX +#define SDRAM_A8_PIO PIO_PC26_IDX +#define SDRAM_A9_PIO PIO_PC27_IDX +#define SDRAM_A10_PIO PIO_PC28_IDX +#define SDRAM_A11_PIO PIO_PC29_IDX +#define SDRAM_SDA10_PIO PIO_PD13_IDX +#define SDRAM_D0_PIO PIO_PC0_IDX +#define SDRAM_D1_PIO PIO_PC1_IDX +#define SDRAM_D2_PIO PIO_PC2_IDX +#define SDRAM_D3_PIO PIO_PC3_IDX +#define SDRAM_D4_PIO PIO_PC4_IDX +#define SDRAM_D5_PIO PIO_PC5_IDX +#define SDRAM_D6_PIO PIO_PC6_IDX +#define SDRAM_D7_PIO PIO_PC7_IDX +#define SDRAM_D8_PIO PIO_PE0_IDX +#define SDRAM_D9_PIO PIO_PE1_IDX +#define SDRAM_D10_PIO PIO_PE2_IDX +#define SDRAM_D11_PIO PIO_PE3_IDX +#define SDRAM_D12_PIO PIO_PE4_IDX +#define SDRAM_D13_PIO PIO_PE5_IDX +#define SDRAM_D14_PIO PIO_PA15_IDX +#define SDRAM_D15_PIO PIO_PA16_IDX + +#define SDRAM_BA0_FLAGS PIO_PERIPH_C +#define SDRAM_SDCK_FLAGS PIO_PERIPH_C +#define SDRAM_SDCKE_FLAGS PIO_PERIPH_C +#define SDRAM_SDCS_FLAGS PIO_PERIPH_A +#define SDRAM_RAS_FLAGS PIO_PERIPH_C +#define SDRAM_CAS_FLAGS PIO_PERIPH_C +#define SDRAM_SDWE_FLAGS PIO_PERIPH_C +#define SDRAM_NBS0_FLAGS PIO_PERIPH_A +#define SDRAM_NBS1_FLAGS PIO_PERIPH_C +#define SDRAM_A_FLAGS PIO_PERIPH_A +#define SDRAM_SDA10_FLAGS PIO_PERIPH_C +#define SDRAM_D_FLAGS PIO_PERIPH_A + +/** LCD SPI configuration */ +#define BOARD_ILI9488_SPI SPI0 +#define BOARD_ILI9488_SPI_IRQN SPI0_IRQn +#define BOARD_ILI9488_SPI_NPCS 3 + +/** LCD SPI pins definition */ +#define LCD_SPI_MISO_PIO PIO_PD20_IDX +#define LCD_SPI_MISO_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +#define LCD_SPI_MOSI_PIO PIO_PD21_IDX +#define LCD_SPI_MOSI_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +#define LCD_SPI_SPCK_PIO PIO_PD22_IDX +#define LCD_SPI_SPCK_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +#define LCD_SPI_NPCS_PIO PIO_PD27_IDX +#define LCD_SPI_NPCS_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) + +#define LCD_SPI_RESET_PIO PIO_PA24_IDX +#define LCD_SPI_RESET_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT) +#define LCD_SPI_CDS_PIO PIO_PA6_IDX +#define LCD_SPI_CDS_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT) +#define LCD_SPI_BACKLIGHT_PIO PIO_PC19_IDX +#define LCD_SPI_BACKLIGHT_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT) + + +/** TWI interface for maXTouch XPRO */ +#define MAXTOUCH_XPRO_TWIHS TWIHS0 + +#define MAXTOUCH_XPRO_CHG_PIO PIO_PA2_IDX + +/** BNO055 external interrupt pin definition */ +#define PIN_BNO055_EXT_INIERRUPT {PIO_PD28, PIOD, ID_PIOD, PIO_INPUT, \ + PIO_DEFAULT | PIO_IT_RISE_EDGE} +#define PIN_BNO055_EXT_INIERRUPT_MASK PIO_PD28 +#define PIN_BNO055_EXT_INIERRUPT_PIO PIOD +#define PIN_BNO055_EXT_INIERRUPT_ID ID_PIOD +#define PIN_BNO055_EXT_INIERRUPT_TYPE PIO_INPUT +#define PIN_BNO055_EXT_INIERRUPT_ATTR (PIO_DEFAULT | PIO_IT_RISE_EDGE) +#define PIN_BNO055_EXT_INIERRUPT_IRQn PIOD_IRQn + +#define BOARD_BNO055_TWIHS TWIHS0 +#define BOARD_BNO055_ID_TWIHS ID_TWIHS0 + +/** TWIHS ID for simulated EEPROM application to use */ +#define BOARD_AT30TSE_ID_TWIHS ID_TWIHS0 +/** TWIHS Base for simulated TWI EEPROM application to use */ +#define BOARD_AT30TSE_TWIHS TWIHS0 + +/*----------------------------------------------------------------------------*/ +#endif /* _SAME70_XPLD_H_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/acc/acc.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/acc/acc.c new file mode 100644 index 00000000..a4a832c2 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/acc/acc.c @@ -0,0 +1,428 @@ +/** + * \file + * + * \brief SAM4 Analog Comparator Controller (ACC) driver. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "acc.h" + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#ifndef ACC_WPMR_WPKEY_PASSWD +# define ACC_WPMR_WPKEY_PASSWD ACC_WPMR_WPKEY((uint32_t) 0x414343) +#endif + +/** + * \brief Initialize the ACC module. + * + * \note This function performs a \ref acc_reset() "software reset" on the + * ACC module prior to its initialization. + * + * \param[in,out] p_acc Module hardware register base address pointer + * \param[in] ul_select_plus Selection for the plus comparator input (inp) + * \param[in] ul_select_minus Selection for the minus comparator input (inn) + * \param[in] ul_edge_type Comparison flag triggering mode + * \param[in] ul_invert Invert the comparator output mode + * + * Where the input parameter ul_select_plus is one of the following: + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Parameter ValueDescription
ACC_MR_SELPLUS_AD0Select AD0 as the plus input
ACC_MR_SELPLUS_AD1Select AD1 as the plus input
ACC_MR_SELPLUS_AD2Select AD2 as the plus input
ACC_MR_SELPLUS_AD3Select AD3 as the plus input
ACC_MR_SELPLUS_AD4Select AD4 as the plus input
ACC_MR_SELPLUS_AD5Select AD5 as the plus input
ACC_MR_SELPLUS_AD6Select AD6 as the plus input
ACC_MR_SELPLUS_AD7Select AD7 as the plus input
+ * + * Where the input parameter ul_select_minus is one of the following: + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Parameter ValueDescription
ACC_MR_SELMINUS_TSSelect TS as the minus input
ACC_MR_SELMINUS_ADVREFSelect ADVREF as the minus input
ACC_MR_SELMINUS_DAC0Select DAC0 as the minus input
ACC_MR_SELMINUS_DAC1Select DAC1 as the minus input
ACC_MR_SELMINUS_AD0Select AD0 as the minus input
ACC_MR_SELMINUS_AD1Select AD1 as the minus input
ACC_MR_SELMINUS_AD2Select AD2 as the minus input
ACC_MR_SELMINUS_AD3Select AD3 as the minus input
+ * + * Where the input parameter ul_edge_type is one of the following: + * + * + * + * + * + * + * + * + *
Parameter ValueDescription
ACC_MR_EDGETYP_RISINGRising edge of comparator output
ACC_MR_EDGETYP_FALLINGFalling edge of comparator output
ACC_MR_EDGETYP_ANYAny edge of comparator output
+ * + * Where the input parameter ul_invert is one of the following: + * + * + * + * + * + * + * + *
Parameter ValueDescription
ACC_MR_INV_DISComparator output is directly processed
ACC_MR_INV_ENComparator output is inverted prior to being processed
+ */ +void acc_init( + Acc *p_acc, + uint32_t ul_select_plus, + uint32_t ul_select_minus, + uint32_t ul_edge_type, + uint32_t ul_invert) +{ + /* Validate the parameters. */ + Assert(p_acc); + + /* Reset the controller. */ + p_acc->ACC_CR |= ACC_CR_SWRST; + + /* Write to the MR register. */ + p_acc->ACC_MR = (((ul_select_plus) & ACC_MR_SELPLUS_Msk) | + ((ul_select_minus) & ACC_MR_SELMINUS_Msk) | + ((ul_edge_type) & ACC_MR_EDGETYP_Msk) | + ((ul_invert) & ACC_MR_INV)) | ACC_MR_ACEN_EN; + + /* Set hysteresis and current option. */ + p_acc->ACC_ACR = (ACC_ACR_ISEL_HISP | + ACC_ACR_HYST(ACC_ACR_HYST_50mv_max)); + + /* Automatic Output Masking Period. */ + while (p_acc->ACC_ISR & (uint32_t) ACC_ISR_MASK); +} + +/** + * \brief Enable the ACC module. + * + * \param[in,out] p_acc Module hardware register base address pointer + */ +void acc_enable( + Acc *p_acc) +{ + /* Validate the parameters. */ + Assert(p_acc); + + p_acc->ACC_MR |= ACC_MR_ACEN_EN; +} + +/** + * \brief Disable the ACC module. + * + * \param[in,out] p_acc Module hardware register base address pointer + */ +void acc_disable( + Acc *p_acc) +{ + /* Validate the parameters. */ + Assert(p_acc); + + p_acc->ACC_MR &= ~ACC_MR_ACEN_EN; +} + +/** + * \brief Software reset the ACC module. + * + * \param[out] p_acc Module hardware register base address pointer + */ +void acc_reset( + Acc *p_acc) +{ + /* Validate the parameters. */ + Assert(p_acc); + + p_acc->ACC_CR = ACC_CR_SWRST; +} + +/** + * \brief Set the ACC comparator plus/minus input sources. + * + * \param[in,out] p_acc Module hardware register base address pointer + * \param[in] ul_select_minus Selection for the minus comparator input (inn) + * \param[in] ul_select_plus Selection for the plus comparator input (inp) + * + * Where the input parameter ul_select_minus is one of the following: + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Parameter ValueDescription
ACC_MR_SELMINUS_TSSelect TS as the minus input
ACC_MR_SELMINUS_ADVREFSelect ADVREF as the minus input
ACC_MR_SELMINUS_DAC0Select DAC0 as the minus input
ACC_MR_SELMINUS_DAC1Select DAC1 as the minus input
ACC_MR_SELMINUS_AD0Select AD0 as the minus input
ACC_MR_SELMINUS_AD1Select AD1 as the minus input
ACC_MR_SELMINUS_AD2Select AD2 as the minus input
ACC_MR_SELMINUS_AD3Select AD3 as the minus input
+ * + * Where the input parameter ul_select_plus is one of the following: + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Parameter ValueDescription
ACC_MR_SELPLUS_AD0Select AD0 as the plus input
ACC_MR_SELPLUS_AD1Select AD1 as the plus input
ACC_MR_SELPLUS_AD2Select AD2 as the plus input
ACC_MR_SELPLUS_AD3Select AD3 as the plus input
ACC_MR_SELPLUS_AD4Select AD4 as the plus input
ACC_MR_SELPLUS_AD5Select AD5 as the plus input
ACC_MR_SELPLUS_AD6Select AD6 as the plus input
ACC_MR_SELPLUS_AD7Select AD7 as the plus input
+ */ +void acc_set_input( + Acc *p_acc, + uint32_t ul_select_minus, + uint32_t ul_select_plus) +{ + /* Validate the parameters. */ + Assert(p_acc); + + p_acc->ACC_MR &= ~(ACC_MR_SELMINUS_Msk | ACC_MR_SELPLUS_Msk); + p_acc->ACC_MR |= ul_select_plus | ul_select_minus; +} + +/** + * \brief Set the ACC output. + * + * \param[in,out] p_acc Module hardware register base address pointer + * \param[in] ul_invert Invert comparator output + * \param[in] ul_fault_enable Fault enable + * \param[in] ul_fault_source Selection of fault source + * + * Where the input parameter ul_invert is one of the following: + * + * + * + * + * + * + * + *
Parameter ValueDescription
ACC_MR_INV_DISComparator output is directly processed
ACC_MR_INV_ENComparator output is inverted prior to being processed
+ * + * Where the input parameter ul_fault_enable is one of the following: + * + * + * + * + * + * + * + *
Parameter ValueDescription
ACC_MR_FE_DISThe FAULT output is tied to 0
ACC_MR_FE_ENThe FAULT output is driven by ul_fault_source
+ * + * Where the input parameter ul_fault_source is one of the following: + * + * + * + * + * + * + * + *
Parameter ValueDescription
ACC_MR_SELFS_CFThe CF flag is used to drive the FAULT output
ACC_MR_SELFS_OUTPUTThe output of the Analog Comparator flag is used to drive the FAULT output
+ */ +void acc_set_output( + Acc *p_acc, + uint32_t ul_invert, + uint32_t ul_fault_enable, + uint32_t ul_fault_source) +{ + /* Validate the parameters. */ + Assert(p_acc); + + p_acc->ACC_MR &= ~(ACC_MR_INV_EN | ACC_MR_FE_EN | ACC_MR_SELFS_OUTPUT); + + p_acc->ACC_MR |= ul_invert | ul_fault_source | ul_fault_enable; +} + +/** + * \brief Get the ACC comparison result. + * + * \param[in] p_acc Module hardware register base address pointer + * + * \return The ACC comparison result. + * \retval 0 Comparator minus input is greater than its plus input (inn>inp) + * \retval 1 Comparator plus input is greater than its minus input (inp>inn) + */ +uint32_t acc_get_comparison_result( + Acc *p_acc) +{ + /* Validate the parameters. */ + Assert(p_acc); + + uint32_t ul_temp = p_acc->ACC_MR; + uint32_t ul_status = p_acc->ACC_ISR; + + if ((ul_temp & ACC_MR_INV_EN) == ACC_MR_INV_EN) { + if (ul_status & ACC_ISR_SCO) { + return 0; /* inn>inp */ + } else { + return 1; /* inp>inn */ + } + } else { + if (ul_status & ACC_ISR_SCO) { + return 1; /* inp>inn */ + } else { + return 0; /* inn>inp */ + } + } +} + +/** + * \brief Enable the ACC comparison edge interrupt. + * + * \param[out] p_acc Module hardware register base address pointer + */ +void acc_enable_interrupt( + Acc *p_acc) +{ + /* Validate the parameters. */ + Assert(p_acc); + + p_acc->ACC_IER = ACC_IER_CE; +} + +/** + * \brief Disable the ACC comparison edge interrupt. + * + * \param[out] p_acc Module hardware register base address pointer + */ +void acc_disable_interrupt( + Acc *p_acc) +{ + /* Validate the parameters. */ + Assert(p_acc); + + p_acc->ACC_IDR = ACC_IDR_CE; +} + +/** + * \brief Get the ACC comparison edge interrupt status. + * + * \param[in] p_acc Module hardware register base address pointer + * + * \return The ACC comparison edge interrupt status. + */ +uint32_t acc_get_interrupt_status( + Acc *p_acc) +{ + /* Validate the parameters. */ + Assert(p_acc); + + return p_acc->ACC_ISR; +} + +/** + * \brief Set the ACC register write-protection. + * + * \param[out] p_acc Module hardware register base address pointer + * \param[in] ul_enable 1 to enable, 0 to disable + */ +void acc_set_writeprotect( + Acc *p_acc, + uint32_t ul_enable) +{ + /* Validate the parameters. */ + Assert(p_acc); + + if (ul_enable) + p_acc->ACC_WPMR = ACC_WPMR_WPKEY_PASSWD | ACC_WPMR_WPEN; + else + p_acc->ACC_WPMR = ACC_WPMR_WPKEY_PASSWD; +} + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Get the ACC register write-protection status. + * + * \param[in] p_acc Module hardware register base address pointer + * + * \return The ACC register write-protection status. + * \retval 0 No write-protection violation occurred + * \retval ACC_WPSR_WPVS Write-protection violation (WPEN = 1) has occurred since the last read of ACC_WPSR + */ +uint32_t acc_get_writeprotect_status( + Acc *p_acc) +{ + /* Validate the parameters. */ + Assert(p_acc); + + return p_acc->ACC_WPSR & ACC_WPSR_WPVS; +} +#else +/** + * \brief Get the ACC register write-protection status. + * + * \param[in] p_acc Module hardware register base address pointer + * + * \return The ACC register write-protection status. + * \retval 0 No write-protection error + * \retval ACC_WPSR_WPROTERR Write-protection error + */ +uint32_t acc_get_writeprotect_status( + Acc *p_acc) +{ + /* Validate the parameters. */ + Assert(p_acc); + + return p_acc->ACC_WPSR & ACC_WPSR_WPROTERR; +} +#endif + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/acc/acc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/acc/acc.h new file mode 100644 index 00000000..7a9ba737 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/acc/acc.h @@ -0,0 +1,372 @@ +/** + * \file + * + * \brief SAM Analog Comparator Controller (ACC) driver. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef ACC_H_INCLUDED +#define ACC_H_INCLUDED + +/** + * \defgroup asfdoc_sam_drivers_acc_group SAM3S/4E/4S/V71/V70/S70/E70 Analog Comparator Controller (ACC) Driver + * + * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for + * the configuration and management of the device's Analog Comparator Controller functionality. + * + * The Analog Comparator compares two voltages, and the result of this comparison + * gives a compare output. The user application can select whether to use a high-speed + * or a low-power option as well as selecting the hysteresis level, edge detection, + * and polarity. + * + * Devices from the following series can use this module: + * - Atmel | SMART SAM3S + * - Atmel | SMART SAM4E + * - Atmel | SMART SAM4S + * - Atmel | SMART SAMV71 + * - Atmel | SMART SAMV70 + * - Atmel | SMART SAME70 + * - Atmel | SMART SAMS70 + * + * The outline of this documentation is as follows: + * - \ref asfdoc_sam_drivers_acc_prerequisites + * - \ref asfdoc_sam_drivers_acc_module_overview + * - \ref asfdoc_sam_drivers_acc_special_considerations + * - \ref asfdoc_sam_drivers_acc_extra_info + * - \ref asfdoc_sam_drivers_acc_examples + * - \ref asfdoc_sam_drivers_acc_api_overview + * + * + * \section asfdoc_sam_drivers_acc_prerequisites Prerequisites + * + * There are no prerequisites for this module. + * + * + * \section asfdoc_sam_drivers_acc_module_overview Module Overview + * + * The Analog Comparator Controller configures the Analog Comparator, and + * generates an interrupt according to the user application's settings. The + * analog comparator embeds 8 to 1 multiplexers on both its plus and minus + * inputs. + * + * The Analog Comparator compares two voltages, and the result of this comparison + * gives a compare output and an interrupt can be generated accordingly. The user + * application can select a high-speed or low-power option, the hysteresis level, + * edge detection, and polarity. + * + * The ACC can also generate a comparison event that can be used by the Pulse Width + * Modulation (PWM) module. + * + * + * \section asfdoc_sam_drivers_acc_special_considerations Special Considerations + * + * \subsection asfdoc_sam_drivers_acc_special_considerations_config Configuration Changes + * + * As soon as the analog comparator settings are modified, the output of the + * analog comparator is masked for the time that its output may be invalid. + * Depending on the user application the following function calls may require + * the comparator output to be valid before continuing: + * - \ref acc_enable() + * - \ref acc_set_input() + * - \ref acc_set_output() + * + * The following code may be used to check if the comparator output is valid + * before continuing: + * \code + * while ((acc_get_interrupt_status(ACC) & ACC_ISR_MASK) == ACC_ISR_MASK) { + * } \endcode + * + * \subsection asfdoc_sam_drivers_acc_special_considerations_io I/O Lines + * + * The analog input pins (AD0-AD7 and DAC0-1) are multiplexed with general-purpose + * input/output (GPIO) lines. The assignment of these pins to ACC module inputs + * is automatically done when the corresponding input is assigned to the + * comparator's plus/minus inputs by the user application performing a write to + * the module's Mode Register. + * + * \subsection asfdoc_sam_drivers_acc_special_considerations_power Power Management + * The ACC module is clocked through the Power Management Controller (PMC), + * thus the user application must first configure the PMC, in order to enable the + * Analog Comparator Controller clock. + * + * \note The voltage regulator must be activated before the Analog Comparator module + * is used. + * + * \subsection asfdoc_sam_drivers_acc_special_considerations_irq Interrupt + * + * The ACC module has an interrupt line connected to the Nested Vectored Interrupt + * Controller (NVIC). Handling the ACC interrupt requires that the NVIC is configured + * before configuring the ACC. + * + * \subsection asfdoc_sam_drivers_acc_special_considerations_fault Fault Output + * + * The ACC module has a FAULT output that is connected to the FAULT input of the + * PWM module. Refer to "fault mode" and the implementation of the PWM in + * the device-specific datasheet. + * + * + * \section asfdoc_sam_drivers_acc_extra_info Extra Information + * + * For extra information, see \ref asfdoc_sam_drivers_acc_extra. This includes: + * - \ref asfdoc_sam_drivers_acc_extra_acronyms + * - \ref asfdoc_sam_drivers_acc_extra_dependencies + * - \ref asfdoc_sam_drivers_acc_extra_errata + * - \ref asfdoc_sam_drivers_acc_extra_history + * + * \section asfdoc_sam_drivers_acc_examples Examples + * + * For a list of examples related to this driver, see + * \ref asfdoc_sam_drivers_acc_exqsg. + * + * + * \section asfdoc_sam_drivers_acc_api_overview API Overview + * @{ + */ + +#include + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** \name Hysteresis Levels + * Refer to the "Analog Comparator Characteristics" table in the + * "Electrical Characteristics" chapter of the device-specific datasheet. + * @{ + */ +#define ACC_ACR_HYST_0mv_max 0x00 +#define ACC_ACR_HYST_50mv_max 0x01 +#define ACC_ACR_HYST_90mv_max 0x11 +/** @} */ + +void acc_init(Acc *p_acc, uint32_t ul_select_plus, uint32_t ul_select_minus, + uint32_t ul_edge_type, uint32_t ul_invert); +void acc_enable(Acc *p_acc); +void acc_disable(Acc *p_acc); +void acc_reset(Acc *p_acc); +void acc_set_input(Acc *p_acc, uint32_t ul_select_minus, + uint32_t ul_select_plus); +void acc_set_output(Acc *p_acc, uint32_t ul_invert, + uint32_t ul_fault_enable, uint32_t ul_fault_source); +uint32_t acc_get_comparison_result(Acc *p_acc); +void acc_enable_interrupt(Acc *p_acc); +void acc_disable_interrupt(Acc *p_acc); +uint32_t acc_get_interrupt_status(Acc *p_acc); +void acc_set_writeprotect(Acc *p_acc, uint32_t ul_enable); +uint32_t acc_get_writeprotect_status(Acc *p_acc); + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +/** @} */ + +/** + * \page asfdoc_sam_drivers_acc_extra Extra Information for Analog Comparator Controller + * + * \section asfdoc_sam_drivers_acc_extra_acronyms Acronyms + * Below is a table listing the acronyms used in this module, along with their + * intended meanings. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
AcronymDefinition
ADAnalog to Digital
DACDigital to Analog Converter
GPIOGeneral Purpose Input Output
NVICNested Vectored Interrupt Controller
PMCPower Management Controller
PWMPulse Width Modulator
QSGQuick Start Guide
+ * + * + * \section asfdoc_sam_drivers_acc_extra_dependencies Dependencies + * This driver has the following dependencies: + * + * - None + * + * + * \section asfdoc_sam_drivers_acc_extra_errata Errata + * There are no errata related to this driver. + * + * + * \section asfdoc_sam_drivers_acc_extra_history Module History + * An overview of the module history is presented in the table below, with + * details on the enhancements and fixes made to the module since its first + * release. The current version of this corresponds to the newest version in + * the table. + * + * + * + * + * + * + * + * + *
Changelog
Initial document release
+ */ + +/** + * \page asfdoc_sam_drivers_acc_exqsg Examples for Analog Comparator Controller + * + * This is a list of the available Quick Start guides (QSGs) and example + * applications for \ref asfdoc_sam_drivers_acc_group. QSGs are simple examples, with + * step-by-step instructions to configure and use this driver in a selection of + * use cases. Note that a QSG can be compiled as a standalone application or be + * added to the user application. + * + * - \subpage asfdoc_sam_drivers_acc_qsg + * - \subpage asfdoc_sam_drivers_acc_example_irq + * + * \page asfdoc_sam_drivers_acc_document_revision_history Document Revision History + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Doc. Rev. + * Date + * Comments + *
42292B07/2015Updated title of application note and added list of supported devices
42292A05/2014Initial document release
+ * + */ + +/** + * \page asfdoc_sam_drivers_acc_qsg Quick Start Guide for the ACC driver + * + * This is the quick start guide for the \ref asfdoc_sam_drivers_acc_group, with + * step-by-step instructions on how to configure and use the driver for + * a specific use case. The code examples can be copied into e.g. the main + * application loop or any other function that will need to control the + * ACC module. + * + * \section asfdoc_sam_drivers_acc_qsg_use_cases Use Cases + * - \ref asfdoc_sam_drivers_acc_qsg_basic + * + * \section asfdoc_sam_drivers_acc_qsg_basic ACC Basic Usage + * + * This use case will demonstrate how to initialize the ACC module in + * interrupt mode. + * + * + * \section asfdoc_sam_drivers_acc_qsg_basic_setup Setup Steps + * + * \subsection asfdoc_sam_acc_qsg_basic_prereq Prerequisites + * + * This module requires the following service: + * - \ref clk_group "System Clock Management (sysclock)" + * + * \subsection asfdoc_sam_drivers_acc_qsg_basic_setup_code Setup Code + * + * Add this to your main application C-file: + * \verbatim + void ACC_Handler(void) + { + } \endverbatim + * Add this to the main loop or a setup function: + * \snippet acc_example.c acc_enable_clock + * + * \subsection asfdoc_sam_drivers_acc_qsg_basic_setup_workflow Workflow + * + * -# Initialize the ACC module so that: + * - ADC channel 5 is connected to its positive input + * - DAC channel 0 is connected to its negative input + * - Generate an interrupt on either edge of the output + * - Disable the ACC module output inversion + * \snippet acc_example.c acc_init + * -# Enable the ACC module interrupt: + * \snippet acc_example.c acc_irq_enable + * + * \section asfdoc_sam_drivers_acc_qsg_basic_usage Usage Steps + * + * \subsection asfdoc_sam_drivers_acc_qsg_basic_usage_code Usage Code + * + * In the ACC_Handler() function, check if the output result is available by: + * \verbatim + if ((ul_status & ACC_ISR_CE) == ACC_ISR_CE) { + } \endverbatim + * In the ACC_Handler() function, check if ADC channel 5 is greater than + * DAC channel 0 by: + * \verbatim + if (acc_get_comparison_result(ACC)) { + do_something_with_a_greater_result(); + } \endverbatim + * In the ACC_Handler() function, check if ADC channel 5 is less than + * DAC channel 0 by: + * \verbatim + if (!acc_get_comparison_result(ACC)) { + do_something_with_a_lesser_result(); + } \endverbatim + */ + +#endif /* ACC_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/acc/acc_example/acc_example.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/acc/acc_example/acc_example.h new file mode 100644 index 00000000..64fcb4ee --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/acc/acc_example/acc_example.h @@ -0,0 +1,101 @@ +/** + * \file + * + * \brief Analog Comparator Controller (ACC) example for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + + #ifndef ACC_EXAMPLE_H_INCLUDED + #define ACC_EXAMPLE_H_INCLUDED + +/** + * \page asfdoc_sam_drivers_acc_example_irq Analog Comparator Controller - Example Interrupt Event Generation + * + * \section asfdoc_sam_drivers_acc_example_irq_purpose Purpose + * + * This example demonstrates how to use the ACC driver to perform a voltage + * comparison on a pair of inputs and generate an interrupt. + * + * \section asfdoc_sam_drivers_acc_example_irq_requirements Requirements + * + * This example can be used on the following evaluation kits: + * - SAM4S EK + * - SAM4S EK2 + * + * \section asfdoc_sam_drivers_acc_example_irq_description Description + * + * The DAC0 and AD5 signals are selected as the inputs to the analog comparator. + * The user can change the output voltage of DAC0 and also change the voltage + * on AD5 by adjusting VR1 on the evaluation kit. + * + * The DAC0 output voltage can be adjusted between (1/6)*ADVREF and (5/6)*ADVREF + * in software, whilst the input voltage on AD5 can vary between 0 and ADVREF. + * + * A comparison interrupt event is generated when the input voltages are + * no longer equal. + * + * \section asfdoc_sam_drivers_acc_example_irq_files Main Files + * - acc.c: Analog Comparator Controller driver + * - acc.h: Analog Comparator Controller driver header file + * - acc_example.c: Analog Comparator Controller example application + * + * \section asfdoc_sam_drivers_acc_example_irq_compilinfo Compilation Information + * This software is written for GNU GCC and IAR Embedded Workbench® + * for Atmel®. Other compilers may or may not work. + + * \section asfdoc_sam_drivers_acc_example_irq_usage Usage + * + * -# Build the program and download it into the evaluation board. + * -# On the computer, open, and configure a terminal application + * (e.g., HyperTerminal on Microsoft® Windows®) with these settings: + * - 115200 baud + * - 8 bits of data + * - No parity + * - 1 stop bit + * - No flow control + * -# Start the application. + * -# In the terminal window, the following text should appear: + * \verbatim + -- ACC IRQ Example xxx -- + -- xxxxxx-xx + -- Compiled: xxx xx xxxx xx:xx:xx -- + + -- Menu Choices for this example-- + -- s: Set new DAC0 output voltage.-- + -- v: Get voltage on potentiometer.-- + -- m: Display this menu again.-- \endverbatim + * -# Enter a character on the terminal to select a menu option. + * -# Change the voltage on AD5 by adjusting VR1 on the evaluation kit in order. + * To see what comparison events occur. + */ + +#endif /* ACC_EXAMPLE_H_INCLUDED */ +/* + * Support and FAQ: visit Microchip Support + */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/afec/afec.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/afec/afec.c new file mode 100644 index 00000000..bd70027d --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/afec/afec.c @@ -0,0 +1,730 @@ +/** + * \file + * + * \brief Analog-Front-End Controller driver for SAM. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "afec.h" +#include "sleepmgr.h" +#include "status_codes.h" +#include "sysclk.h" +#include "pmc.h" + +/** + * \defgroup sam_drivers_afec_group Analog-Front-End Controller + * + * See \ref sam_afec_quickstart. + * + * Driver for the Analog-Front-End Controller. This driver provides access to + * the main features of the AFEC controller. + * + * @{ + */ +#if defined(AFEC1) +#define NUM_OF_AFEC (2UL) +#else +#define NUM_OF_AFEC (1UL) +#endif + +/* The gap between bit EOC15 and DRDY in interrupt register */ +#if defined __SAM4E8C__ || defined __SAM4E16C__ || defined __SAM4E8CB__ || defined __SAM4E16CB__ +#define AFEC_INTERRUPT_GAP1 (17UL) +#elif defined __SAM4E8E__ || defined __SAM4E16E__ +#define AFEC_INTERRUPT_GAP1 (8UL) +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) +/* The gap between bit EOC11 and DRDY in interrupt register */ +#define AFEC_INTERRUPT_GAP1 (12UL) +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/* The gap between bit COMPE and TEMPCHG in interrupt register */ +#define AFEC_INTERRUPT_GAP2 (3UL) +#else +/* The gap between bit RXBUFF and TEMPCHG in interrupt register */ +#define AFEC_INTERRUPT_GAP2 (1UL) +#endif + +/* The number of channel in channel sequence1 register */ +#define AFEC_SEQ1_CHANNEL_NUM (8UL) + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/* The interrupt source number of temperature sensor */ +#define AFEC_TEMP_INT_SOURCE_NUM (11UL) +#else +/* The interrupt source number of temperature sensor */ +#define AFEC_TEMP_INT_SOURCE_NUM (15UL) +#endif + +afec_callback_t afec_callback_pointer[NUM_OF_AFEC][_AFEC_NUM_OF_INTERRUPT_SOURCE]; + + +/** + * \internal + * \brief Get AFEC instance number. + * + * \param afec Base address of the AFEC + * + * \return AFEC instance number + */ +static uint32_t afec_find_inst_num(Afec *const afec) +{ +#if defined(AFEC1) + if (afec == AFEC1) { + return 1; + } +#endif +#if defined(AFEC0) + if (afec == AFEC0) { + return 0; + } +#endif + return 0; +} + +/** + * \internal + * \brief Get AFEC Peripheral ID. + * + * \param afec Base address of the AFEC + * + * \return AFEC Peripheral ID + */ +static uint32_t afec_find_pid(Afec *const afec) +{ +#if defined(ID_AFEC1) + if (afec == AFEC1) { + return ID_AFEC1; + } +#endif +#if defined(ID_AFEC0) + if (afec == AFEC0) { + return ID_AFEC0; + } +#endif + return ID_AFEC0; +} + +/** + * \internal + * \brief Configure the AFEC Module. + * + * \param afec Base address of the AFEC + * \param config Configuration for the AFEC + */ +static void afec_set_config(Afec *const afec, struct afec_config *config) +{ + uint32_t reg = 0; + + reg = (config->useq ? AFEC_MR_USEQ_REG_ORDER : 0) | + #if (SAMV71 || SAMV70 || SAME70 || SAMS70) + AFEC_MR_PRESCAL((config->mck / config->afec_clock )- 1) | + AFEC_MR_ONE | + #else + (config->anach ? AFEC_MR_ANACH_ALLOWED : 0) | + AFEC_MR_PRESCAL(config->mck / (2 * config->afec_clock) - 1) | + (config->settling_time) | + #endif + AFEC_MR_TRACKTIM(config->tracktim) | + AFEC_MR_TRANSFER(config->transfer) | + (config->startup_time); + + afec->AFEC_MR = reg; + + afec->AFEC_EMR = (config->tag ? AFEC_EMR_TAG : 0) | + (config->resolution) | + (config->stm ? AFEC_EMR_STM : 0); + #if (SAMV71 || SAMV70 || SAME70 || SAMS70) + afec->AFEC_ACR = AFEC_ACR_IBCTL(config->ibctl) | AFEC_ACR_PGA0EN | AFEC_ACR_PGA1EN; + #else + afec->AFEC_ACR = AFEC_ACR_IBCTL(config->ibctl); + #endif +} + +/** + * \brief Configure the AFEC channel. + * + * \param afec Base address of the AFEC + * \param channel The channel number + * \param config Configuration for the AFEC channel + */ +void afec_ch_set_config(Afec *const afec, const enum afec_channel_num channel, + struct afec_ch_config *config) +{ + afec_ch_sanity_check(afec, channel); + uint32_t reg = 0; + + reg = afec->AFEC_DIFFR; + reg &= ~(0x1u << channel); + reg |= (config->diff) ? (0x1u << channel) : 0; + afec->AFEC_DIFFR = reg; + + reg = afec->AFEC_CGR; + reg &= ~(0x03u << (2 * channel)); + reg |= (config->gain) << (2 * channel); + afec->AFEC_CGR = reg; +} + +/** + * \brief Configure the AFEC temperature sensor. + * + * \param afec Base address of the AFEC + * \param config Configuration for the AFEC temperature sensor + */ +void afec_temp_sensor_set_config(Afec *const afec, + struct afec_temp_sensor_config *config) +{ + Assert(afec == AFEC0); + + uint32_t reg = 0; + + reg = ((config->rctc) ? AFEC_TEMPMR_RTCT : 0) | (config->mode); + afec->AFEC_TEMPMR = reg; + + afec->AFEC_TEMPCWR = AFEC_TEMPCWR_TLOWTHRES(config->low_threshold) | + AFEC_TEMPCWR_THIGHTHRES(config->high_threshold); + +} + +/** + * \brief Get the AFEC default configurations. + * + * Use to initialize the configuration structure to known default values. This + * function should be called at the start of any AFEC initiation. + * + * The default configuration is as follows: + * - 12 -bit resolution + * - AFEC clock frequency is 6MHz + * - Start Up Time is 64 periods AFEC clock, for SAMV71 is 24 periods AFEC clock + * - Analog Settling Time is 3 periods of AFEC clock + * - Tracking Time is 3 periods of AFEC clock + * - Transfer Period is 5 periods AFEC clock,for SAMV71 is 7 periods AFEC clock + * - Allows different analog settings for each channel + * - The controller converts channels in a simple numeric order + * - Appends the channel number to the conversion result in AFE_LDCR register + * - Only a Single Trigger is required to get an averaged value + * - AFE Bias Current Control value is 1 + * + * \param cfg Pointer to configuration structure to be initiated. + */ +void afec_get_config_defaults(struct afec_config *const cfg) +{ + /* Sanity check argument. */ + Assert(cfg); + + cfg->resolution = AFEC_12_BITS; + cfg->mck = sysclk_get_cpu_hz(); + cfg->afec_clock = 6000000UL; + cfg->startup_time = AFEC_STARTUP_TIME_4; + #if !(SAMV71 || SAMV70 || SAME70 || SAMS70) + cfg->settling_time = AFEC_SETTLING_TIME_0; + #endif + cfg->tracktim = 2; + cfg->transfer = 1; + cfg->anach = true; + cfg->useq = false; + cfg->tag = true; + cfg->stm = true; + cfg->ibctl = 1; +} + +/** + * \brief Get the AFEC channel default configurations. + * + * Use to initialize the configuration structure to known default values. + * + * The default configuration is as follows: + * - Single Ended Mode + * - Gain value is 1 + * + * \param cfg Pointer to channel configuration structure to be initiated. + */ +void afec_ch_get_config_defaults(struct afec_ch_config *const cfg) +{ + /*Sanity check argument. */ + Assert(cfg); + + cfg->diff = false; + cfg->gain = AFEC_GAINVALUE_1; + +} + +/** + * \brief Get the AFEC Temperature Sensor default configurations. + * + * Use to initialize the configuration structure to known default values. + * + * The default configuration is as follows: + * - The temperature sensor measure is not triggered by RTC event + * - Generates an event when the converted data is in the comparison window + * - The window range is 0xFF ~ 0xFFF + * + * \param cfg Pointer to temperature sensor configuration structure + * to be initiated. + */ +void afec_temp_sensor_get_config_defaults( + struct afec_temp_sensor_config *const cfg) +{ + /*Sanity check argument. */ + Assert(cfg); + + cfg->rctc = false; + cfg->mode= AFEC_TEMP_CMP_MODE_2; + cfg->low_threshold= 0xFF; + cfg->high_threshold= 0xFFF; +} + +/** + * \brief Initialize the AFEC Module. + * + * \param afec Base address of the AFEC + * \param config Configuration for the AFEC + * + * \retval STATUS_OK Initialization is finished. + * \retval STATUS_ERR_BUSY Initialization failed. + */ +enum status_code afec_init(Afec *const afec, struct afec_config *config) +{ + Assert(afec); + Assert(config); + + if ((afec_get_interrupt_status(afec) & AFEC_ISR_DRDY) == AFEC_ISR_DRDY) { + return STATUS_ERR_BUSY; + } + + /* Reset and configure the AFEC module */ + afec->AFEC_CR = AFEC_CR_SWRST; + afec_set_config(afec, config); + + uint32_t i; + if(afec == AFEC0) { + for (i = 0; i < _AFEC_NUM_OF_INTERRUPT_SOURCE; i++){ + afec_callback_pointer[0][i] = 0; + } + } + if(afec == AFEC1) { + for (i = 0; i < _AFEC_NUM_OF_INTERRUPT_SOURCE; i++){ + afec_callback_pointer[1][i] = 0; + } + } + + return STATUS_OK; +} + +/** + * \brief Configure comparison mode. + * + * \param afec Base address of the AFEC. + * \param mode Comparison mode. + * \param channel Comparison Selected Channel. + * \param cmp_filter Compare Event Filtering. + */ +void afec_set_comparison_mode(Afec *const afec, + const enum afec_cmp_mode mode, + const enum afec_channel_num channel, uint8_t cmp_filter) +{ + if (channel != AFEC_CHANNEL_ALL) { + afec_ch_sanity_check(afec, channel); + } + + uint32_t reg; + + reg = afec->AFEC_EMR; + + reg &= ~(AFEC_EMR_CMPSEL_Msk | + AFEC_EMR_CMPMODE_Msk | + AFEC_EMR_CMPFILTER_Msk); + reg |= mode | + ((channel == AFEC_CHANNEL_ALL) ? AFEC_EMR_CMPALL + : AFEC_EMR_CMPSEL(channel)) | + AFEC_EMR_CMPFILTER(cmp_filter); + + afec->AFEC_EMR = reg; +} + +/** + * \brief Configure AFEC power mode. + * + * \param afec Base address of the AFEC. + * \param mode AFEC power mode value. + */ +void afec_set_power_mode(Afec *const afec, + const enum afec_power_mode mode) +{ + uint32_t reg; + + reg = afec->AFEC_MR; + + switch(mode) { + case AFEC_POWER_MODE_0: + reg &= ~(AFEC_MR_FWUP_ON | AFEC_MR_SLEEP_SLEEP); + break; + case AFEC_POWER_MODE_1: + reg |= AFEC_MR_FWUP_ON; + break; + case AFEC_POWER_MODE_2: + reg |= AFEC_MR_SLEEP_SLEEP; + reg &= ~AFEC_MR_FWUP_ON; + break; + } + + afec->AFEC_MR = reg; +} + +/** + * \brief Set callback for AFEC + * + * \param afec Base address of the AFEC + * \param source Interrupt source + * \param callback Callback function pointer + * \param irq_level Interrupt level + */ +void afec_set_callback(Afec *const afec, enum afec_interrupt_source source, + afec_callback_t callback, uint8_t irq_level) +{ + Assert(afec); + Assert(callback); + + uint32_t i = afec_find_inst_num(afec); + afec_callback_pointer[i][source] = callback; + if (!i) { + irq_register_handler(AFEC0_IRQn, irq_level); + } else if (i == 1) { + irq_register_handler(AFEC1_IRQn, irq_level); + } + /* Enable the specified interrupt source */ + afec_enable_interrupt(afec, source); +} + +/** + * \brief Enable AFEC interrupts. + * + * \param afec Base address of the AFEC. + * \param interrupt_source Interrupts to be enabled. + */ +void afec_enable_interrupt(Afec *const afec, + enum afec_interrupt_source interrupt_source) +{ + if (interrupt_source == AFEC_INTERRUPT_ALL) { + afec->AFEC_IER = AFEC_INTERRUPT_ALL; + return; + } + + if (interrupt_source < AFEC_INTERRUPT_DATA_READY) { + #if (SAMV71 || SAMV70 || SAME70 || SAMS70) + if (interrupt_source == AFEC_INTERRUPT_EOC_11) { + afec->AFEC_IER = 1 << AFEC_TEMP_INT_SOURCE_NUM; + #else + if (interrupt_source == AFEC_INTERRUPT_EOC_15) { + afec->AFEC_IER = 1 << AFEC_TEMP_INT_SOURCE_NUM; + #endif + } else { + afec->AFEC_IER = 1 << interrupt_source; + } + } else if (interrupt_source < AFEC_INTERRUPT_TEMP_CHANGE) { + afec->AFEC_IER = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1); + } else { + afec->AFEC_IER = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1 + + AFEC_INTERRUPT_GAP2); + } +} + +/** + * \brief Disable AFEC interrupts. + * + * \param afec Base address of the AFEC. + * \param interrupt_source Interrupts to be disabled. + */ +void afec_disable_interrupt(Afec *const afec, + enum afec_interrupt_source interrupt_source) +{ + if (interrupt_source == AFEC_INTERRUPT_ALL) { + afec->AFEC_IDR = AFEC_INTERRUPT_ALL; + return; + } + + if (interrupt_source < AFEC_INTERRUPT_DATA_READY) { + #if (SAMV71 || SAMV70 || SAME70 || SAMS70) + if (interrupt_source == AFEC_INTERRUPT_EOC_11) { + afec->AFEC_IDR = 1 << AFEC_TEMP_INT_SOURCE_NUM; + #else + if (interrupt_source == AFEC_INTERRUPT_EOC_15) { + afec->AFEC_IDR = 1 << AFEC_TEMP_INT_SOURCE_NUM; + #endif + } else { + afec->AFEC_IDR = 1 << interrupt_source; + } + } else if (interrupt_source < AFEC_INTERRUPT_TEMP_CHANGE) { + afec->AFEC_IDR = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1); + } else { + afec->AFEC_IDR = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1 + + AFEC_INTERRUPT_GAP2); + } +} + +/** + * \internal + * \brief Common AFEC interrupt handler + * + * The optional callback used by the interrupt handler is set by the + * afec_set_callback() function. + * + * \param inst_num AFEC instance number to handle interrupt for + * \param source Interrupt source number + */ +static void afec_interrupt(uint8_t inst_num, + enum afec_interrupt_source source) +{ + if (afec_callback_pointer[inst_num][source]) { + afec_callback_pointer[inst_num][source](); + } +} + +/** + * \internal + * \brief Call the callback function if the corresponding interrupt is asserted + * + * \param afec Base address of the AFEC. + */ +static void afec_process_callback(Afec *const afec) +{ + volatile uint32_t status; + uint32_t cnt, inst_num; + + status = afec_get_interrupt_status(afec) & afec_get_interrupt_mask(afec); + inst_num = afec_find_inst_num(afec); + + for (cnt = 0; cnt < _AFEC_NUM_OF_INTERRUPT_SOURCE; cnt++) { + if (cnt < AFEC_INTERRUPT_DATA_READY) { + #if defined __SAM4E8C__ || defined __SAM4E16C__ || defined __SAM4E8CB__ || defined __SAM4E16CB__ + if(cnt == AFEC_INTERRUPT_EOC_15) { + if (status & (1 << AFEC_TEMP_INT_SOURCE_NUM)) { + afec_interrupt(inst_num, (enum afec_interrupt_source)cnt); + } + } else { + if (status & (1 << cnt)) { + afec_interrupt(inst_num, (enum afec_interrupt_source)cnt); + } + } + #elif defined __SAM4E8E__ || defined __SAM4E16E__ || SAMV71 || SAMV70 || SAMS70 || SAME70 + if (status & (1 << cnt)) { + afec_interrupt(inst_num, (enum afec_interrupt_source)cnt); + } + #endif + } else if (cnt < AFEC_INTERRUPT_TEMP_CHANGE) { + if (status & (1 << (cnt + AFEC_INTERRUPT_GAP1))) { + afec_interrupt(inst_num, (enum afec_interrupt_source)cnt); + } + } else { + if (status & (1 << (cnt + AFEC_INTERRUPT_GAP1 + AFEC_INTERRUPT_GAP2))) { + afec_interrupt(inst_num, (enum afec_interrupt_source)cnt); + } + } + } +} + +/** + * \brief Interrupt handler for AFEC0. + */ +void AFEC0_Handler(void) +{ + afec_process_callback(AFEC0); +} + +/** + * \brief Interrupt handler for AFEC1. + */ +void AFEC1_Handler(void) +{ + afec_process_callback(AFEC1); +} + +/** + * \brief Enable AFEC Module. + * + * \param afec Base address of the AFEC + */ +void afec_enable(Afec *const afec) +{ + Assert(afec); + uint32_t pid; + + pid = afec_find_pid(afec); + /* Enable peripheral clock. */ + pmc_enable_periph_clk(pid); + sleepmgr_lock_mode(SLEEPMGR_SLEEP_WFI); +} + +/** + * \brief Disable AFEC Module. + * + * \param afec Base address of the AFEC + */ +void afec_disable(Afec *const afec) +{ + Assert(afec); + uint32_t pid; + + pid = afec_find_pid(afec); + /* Disable peripheral clock. */ + pmc_disable_periph_clk(pid); + sleepmgr_unlock_mode(SLEEPMGR_SLEEP_WFI); +} + +/** + * \brief Configure conversion sequence. + * + * \param afec Base address of the AFEC. + * \param ch_list Channel sequence list. + * \param uc_num Number of channels in the list. + */ +void afec_configure_sequence(Afec *const afec, + const enum afec_channel_num ch_list[], uint8_t uc_num) +{ + uint8_t uc_counter; + + /* Set user sequence mode */ + afec->AFEC_MR |= AFEC_MR_USEQ_REG_ORDER; + afec->AFEC_SEQ1R = 0; + afec->AFEC_SEQ2R = 0; + + if (uc_num < AFEC_SEQ1_CHANNEL_NUM) { + for (uc_counter = 0; uc_counter < uc_num; uc_counter++) { + afec->AFEC_SEQ1R |= + ch_list[uc_counter] << (4 * uc_counter); + } + } else { + for (uc_counter = 0; uc_counter < AFEC_SEQ1_CHANNEL_NUM; uc_counter++) { + afec->AFEC_SEQ1R |= + ch_list[uc_counter] << (4 * uc_counter); + } + for (uc_counter = 0; uc_counter < uc_num - AFEC_SEQ1_CHANNEL_NUM; + uc_counter++) { + afec->AFEC_SEQ2R |= + ch_list[uc_counter + AFEC_SEQ1_CHANNEL_NUM] << (4 * uc_counter); + } + } +} + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Configure Automatic Error Correction. + * + * \param afec Base address of the AFEC + * \param channel Number of channels in the list. + * \param offsetcorr the Offset Correction value,signed value + * \param gaincorr the Gain Correction value. + */ +void afec_configure_auto_error_correction(Afec *const afec, + const enum afec_channel_num channel, int16_t offsetcorr, uint16_t gaincorr) +{ + + + if (channel != AFEC_CHANNEL_ALL) { + afec_ch_sanity_check(afec, channel); + } + + uint32_t reg = 0; + reg = afec->AFEC_CECR; + reg |= (channel == AFEC_CHANNEL_ALL)? AFEC_CHANNEL_ALL : (0x1u << channel); + afec->AFEC_CECR = reg; + + if (channel == AFEC_CHANNEL_ALL) { + afec->AFEC_COSR = 0; + afec->AFEC_CVR = AFEC_CVR_OFFSETCORR(offsetcorr) | AFEC_CVR_GAINCORR(gaincorr); + afec->AFEC_COSR = AFEC_COSR_CSEL; + } + else if (channel < AFEC_CHANNEL_6){ + afec->AFEC_COSR = 0; + } + else{ + afec->AFEC_COSR = AFEC_COSR_CSEL; + } + afec->AFEC_CVR = AFEC_CVR_OFFSETCORR(offsetcorr) | AFEC_CVR_GAINCORR(gaincorr); + +} + +/** + * \brief correct the Converted Data of the selected channel if automatic error correction is enabled. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + * + * \return AFEC corrected value of the selected channel. + */ + uint32_t afec_get_correction_value(Afec *const afec, + const enum afec_channel_num afec_ch) +{ + uint32_t corrected_data = 0; + uint32_t converted_data = 0; + + afec_ch_sanity_check(afec, afec_ch); + + afec->AFEC_CSELR = afec_ch; + converted_data = afec->AFEC_CDR; + + corrected_data = (converted_data + (afec->AFEC_CVR & AFEC_CVR_OFFSETCORR_Msk)) * + (afec->AFEC_CVR >> AFEC_CVR_GAINCORR_Pos) / 1024u; + return corrected_data; + +} + +/** + * \brief Configure sample&hold mode. + * + * \param afec Base address of the AFEC. + * \param channel AFEC Channel number. + * \param mode sample&hold mode. + */ +void afec_set_sample_hold_mode(Afec *const afec, + const enum afec_channel_num channel, const enum afec_sample_hold_mode mode) +{ + if (channel != AFEC_CHANNEL_ALL) { + afec_ch_sanity_check(afec, channel); + } + + uint32_t reg = 0; + reg = afec->AFEC_SHMR; + if (mode == AFEC_SAMPLE_HOLD_MODE_1) { + + reg |= (channel == AFEC_CHANNEL_ALL)? AFEC_CHANNEL_ALL : 0x1u << channel; + } + else { + + reg = (channel == AFEC_CHANNEL_ALL)? 0 : ~(0x1u << channel); + } + afec->AFEC_SHMR = reg; + +} +#endif + +//@} diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/afec/afec.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/afec/afec.h new file mode 100644 index 00000000..c8e8593c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/afec/afec.h @@ -0,0 +1,797 @@ +/** + * \file + * + * \brief Analog-Front-End Controller driver for SAM. + * + * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef AFEC_H_INCLUDED +#define AFEC_H_INCLUDED + +#include "compiler.h" +#include "status_codes.h" + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** Definitions for AFEC resolution */ +enum afec_resolution { + AFEC_12_BITS = AFEC_EMR_RES_NO_AVERAGE, /* AFEC 12-bit resolution */ + AFEC_13_BITS = AFEC_EMR_RES_OSR4, /* AFEC 13-bit resolution */ + AFEC_14_BITS = AFEC_EMR_RES_OSR16, /* AFEC 14-bit resolution */ + AFEC_15_BITS = AFEC_EMR_RES_OSR64, /* AFEC 15-bit resolution */ + AFEC_16_BITS = AFEC_EMR_RES_OSR256 /* AFEC 16-bit resolution */ +}; +#else +/** Definitions for AFEC resolution */ +enum afec_resolution { + AFEC_10_BITS = AFEC_EMR_RES_LOW_RES, /* AFEC 10-bit resolution */ + AFEC_12_BITS = AFEC_EMR_RES_NO_AVERAGE, /* AFEC 12-bit resolution */ + AFEC_13_BITS = AFEC_EMR_RES_OSR4, /* AFEC 13-bit resolution */ + AFEC_14_BITS = AFEC_EMR_RES_OSR16, /* AFEC 14-bit resolution */ + AFEC_15_BITS = AFEC_EMR_RES_OSR64, /* AFEC 15-bit resolution */ + AFEC_16_BITS = AFEC_EMR_RES_OSR256 /* AFEC 16-bit resolution */ +}; +#endif +/** Definitions for AFEC power mode */ +enum afec_power_mode { + /* AFEC core on and reference voltage circuitry on */ + AFEC_POWER_MODE_0 = 0, + /* AFEC core off and reference voltage circuitry on */ + AFEC_POWER_MODE_1, + /* AFEC core off and reference voltage circuitry off */ + AFEC_POWER_MODE_2 +}; + +/** Definitions for AFEC trigger */ +enum afec_trigger { + /* Starting a conversion is only possible by software. */ + AFEC_TRIG_SW = AFEC_MR_TRGEN_DIS, + /* External trigger */ + AFEC_TRIG_EXT = AFEC_MR_TRGSEL_AFEC_TRIG0 | AFEC_MR_TRGEN, + /* TIO Output of the Timer Counter Channel 0 */ + AFEC_TRIG_TIO_CH_0 = AFEC_MR_TRGSEL_AFEC_TRIG1 | AFEC_MR_TRGEN, + /* TIO Output of the Timer Counter Channel 1 */ + AFEC_TRIG_TIO_CH_1 = AFEC_MR_TRGSEL_AFEC_TRIG2 | AFEC_MR_TRGEN, + /* TIO Output of the Timer Counter Channel 2 */ + AFEC_TRIG_TIO_CH_2 = AFEC_MR_TRGSEL_AFEC_TRIG3 | AFEC_MR_TRGEN, + /* PWM Event Line 0 */ + AFEC_TRIG_PWM_EVENT_LINE_0 = AFEC_MR_TRGSEL_AFEC_TRIG4 | AFEC_MR_TRGEN, + /* PWM Event Line 1 */ + AFEC_TRIG_PWM_EVENT_LINE_1 = AFEC_MR_TRGSEL_AFEC_TRIG5 | AFEC_MR_TRGEN, +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) + /*Analog Comparator*/ + AFEC_TRIG_ANALOG_COMPARATOR = AFEC_MR_TRGSEL_AFEC_TRIG6 | AFEC_MR_TRGEN, +#endif + /* Freerun mode conversion. */ + AFEC_TRIG_FREERUN = 0xFF, +}; + +#if defined __SAM4E8C__ || defined __SAM4E16C__ || defined __SAM4E8CB__ || defined __SAM4E16CB__ +/** Definitions for AFEC channel number */ +enum afec_channel_num { + AFEC_CHANNEL_0 = 0, + AFEC_CHANNEL_1, + AFEC_CHANNEL_2, + AFEC_CHANNEL_3, + AFEC_CHANNEL_4, + AFEC_CHANNEL_5, + AFEC_TEMPERATURE_SENSOR = 15, + AFEC_CHANNEL_ALL = 0x803F, +} ; +#elif defined __SAM4E8E__ || defined __SAM4E16E__ +/** Definitions for AFEC channel number */ +enum afec_channel_num { + AFEC_CHANNEL_0 = 0, + AFEC_CHANNEL_1, + AFEC_CHANNEL_2, + AFEC_CHANNEL_3, + AFEC_CHANNEL_4, + AFEC_CHANNEL_5, + AFEC_CHANNEL_6, + AFEC_CHANNEL_7, + AFEC_CHANNEL_8, + AFEC_CHANNEL_9, + AFEC_CHANNEL_10, + AFEC_CHANNEL_11, + AFEC_CHANNEL_12, + AFEC_CHANNEL_13, + AFEC_CHANNEL_14, + AFEC_TEMPERATURE_SENSOR, + AFEC_CHANNEL_ALL = 0xFFFF, +} ; +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** Definitions for AFEC channel number */ +enum afec_channel_num { + AFEC_CHANNEL_0 = 0, + AFEC_CHANNEL_1, + AFEC_CHANNEL_2, + AFEC_CHANNEL_3, + AFEC_CHANNEL_4, + AFEC_CHANNEL_5, + AFEC_CHANNEL_6, + AFEC_CHANNEL_7, + AFEC_CHANNEL_8, + AFEC_CHANNEL_9, + AFEC_CHANNEL_10, + AFEC_TEMPERATURE_SENSOR, + AFEC_CHANNEL_ALL = 0x0FFF, +} ; + +#define NB_CH_AFE0 (12UL) +#define NB_CH_AFE1 (12UL) +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +enum afec_sample_hold_mode { + /*Single Sample-and-Hold mode*/ + AFEC_SAMPLE_HOLD_MODE_0, + /*Dual Sample-and-Hold mode*/ + AFEC_SAMPLE_HOLD_MODE_1, +}; +#endif + +/** Definitions for AFEC gain value */ +enum afec_gainvalue { + AFEC_GAINVALUE_0 = 0, + AFEC_GAINVALUE_1 = 1, + AFEC_GAINVALUE_2 = 2, + AFEC_GAINVALUE_3 = 3 +}; + +/** Definitions for AFEC Start Up Time */ +enum afec_startup_time { + AFEC_STARTUP_TIME_0 = AFEC_MR_STARTUP_SUT0, + AFEC_STARTUP_TIME_1 = AFEC_MR_STARTUP_SUT8, + AFEC_STARTUP_TIME_2 = AFEC_MR_STARTUP_SUT16, + AFEC_STARTUP_TIME_3 = AFEC_MR_STARTUP_SUT24, + AFEC_STARTUP_TIME_4 = AFEC_MR_STARTUP_SUT64, + AFEC_STARTUP_TIME_5 = AFEC_MR_STARTUP_SUT80, + AFEC_STARTUP_TIME_6 = AFEC_MR_STARTUP_SUT96, + AFEC_STARTUP_TIME_7 = AFEC_MR_STARTUP_SUT112, + AFEC_STARTUP_TIME_8 = AFEC_MR_STARTUP_SUT512, + AFEC_STARTUP_TIME_9 = AFEC_MR_STARTUP_SUT576, + AFEC_STARTUP_TIME_10 = AFEC_MR_STARTUP_SUT640, + AFEC_STARTUP_TIME_11 = AFEC_MR_STARTUP_SUT704, + AFEC_STARTUP_TIME_12 = AFEC_MR_STARTUP_SUT768, + AFEC_STARTUP_TIME_13 = AFEC_MR_STARTUP_SUT832, + AFEC_STARTUP_TIME_14 = AFEC_MR_STARTUP_SUT896, + AFEC_STARTUP_TIME_15 = AFEC_MR_STARTUP_SUT960 +}; + +#if SAM4E +/** Definitions for AFEC analog settling time */ +enum afec_settling_time { + AFEC_SETTLING_TIME_0 = AFEC_MR_SETTLING_AST3, + AFEC_SETTLING_TIME_1 = AFEC_MR_SETTLING_AST5, + AFEC_SETTLING_TIME_2 = AFEC_MR_SETTLING_AST9, + AFEC_SETTLING_TIME_3 = AFEC_MR_SETTLING_AST17 +}; +#endif + +/** Definitions for Comparison Mode */ +enum afec_cmp_mode { + AFEC_CMP_MODE_0 = AFEC_EMR_CMPMODE_LOW, + AFEC_CMP_MODE_1 = AFEC_EMR_CMPMODE_HIGH, + AFEC_CMP_MODE_2 = AFEC_EMR_CMPMODE_IN, + AFEC_CMP_MODE_3 = AFEC_EMR_CMPMODE_OUT +}; + +/** Definitions for Temperature Comparison Mode */ +enum afec_temp_cmp_mode { + AFEC_TEMP_CMP_MODE_0 = AFEC_TEMPMR_TEMPCMPMOD_LOW, + AFEC_TEMP_CMP_MODE_1 = AFEC_TEMPMR_TEMPCMPMOD_HIGH, + AFEC_TEMP_CMP_MODE_2 = AFEC_TEMPMR_TEMPCMPMOD_IN, + AFEC_TEMP_CMP_MODE_3 = AFEC_TEMPMR_TEMPCMPMOD_OUT +}; + +/** + * \brief Analog-Front-End Controller configuration structure. + * + * Configuration structure for a Analog-Front-End Controller instance. + * This structure could be initialized by the \ref afec_get_config_defaults() + * function before being modified by the user application. + */ +struct afec_config { + /** Resolution */ + enum afec_resolution resolution; + /** Master Clock */ + uint32_t mck; + /** AFEC Clock */ + uint32_t afec_clock; + /** Start Up Time */ + enum afec_startup_time startup_time; + #if SAM4E + /** Analog Settling Time = (settling_time + 1) / AFEC clock */ + enum afec_settling_time settling_time; + #endif + /** Tracking Time = tracktim / AFEC clock */ + uint8_t tracktim; + /** Transfer Period = (transfer * 2 + 3) / AFEC clock */ + uint8_t transfer; + /** Analog Change */ + bool anach; + /** Use Sequence Enable */ + bool useq; + /** TAG of AFE_LDCR register */ + bool tag; + /** Single Trigger Mode */ + bool stm; + /** AFE Bias Current Control */ + uint8_t ibctl; +}; + +/** AFEC channel configuration structure.*/ +struct afec_ch_config { + /** Differential Mode */ + bool diff; + /** Gain Value */ + enum afec_gainvalue gain; +}; + +/** AFEC Temperature Sensor configuration structure.*/ +struct afec_temp_sensor_config { + /** RTC Trigger mode */ + bool rctc; + /** Temperature Comparison Mode */ + enum afec_temp_cmp_mode mode; + /** Temperature Low Threshold */ + uint16_t low_threshold; + /** Temperature High Threshold */ + uint16_t high_threshold; +}; + +#if defined __SAM4E8C__ || defined __SAM4E16C__ || defined __SAM4E8CB__ || defined __SAM4E16CB__ +/** AFEC interrupt source type */ +enum afec_interrupt_source { + AFEC_INTERRUPT_EOC_0 = 0, + AFEC_INTERRUPT_EOC_1, + AFEC_INTERRUPT_EOC_2, + AFEC_INTERRUPT_EOC_3, + AFEC_INTERRUPT_EOC_4, + AFEC_INTERRUPT_EOC_5, + AFEC_INTERRUPT_EOC_15, + AFEC_INTERRUPT_DATA_READY, + AFEC_INTERRUPT_OVERRUN_ERROR, + AFEC_INTERRUPT_COMP_ERROR, + AFEC_INTERRUPT_END_RXBUF, + AFEC_INTERRUPT_RXBUF_FULL, + AFEC_INTERRUPT_TEMP_CHANGE, + AFEC_INTERRUPT_END_CAL, + _AFEC_NUM_OF_INTERRUPT_SOURCE, + AFEC_INTERRUPT_ALL = 0xDF00803F, +}; +#elif defined __SAM4E8E__ || defined __SAM4E16E__ +/** AFEC interrupt source type */ +enum afec_interrupt_source { + AFEC_INTERRUPT_EOC_0 = 0, + AFEC_INTERRUPT_EOC_1, + AFEC_INTERRUPT_EOC_2, + AFEC_INTERRUPT_EOC_3, + AFEC_INTERRUPT_EOC_4, + AFEC_INTERRUPT_EOC_5, + AFEC_INTERRUPT_EOC_6, + AFEC_INTERRUPT_EOC_7, + AFEC_INTERRUPT_EOC_8, + AFEC_INTERRUPT_EOC_9, + AFEC_INTERRUPT_EOC_10, + AFEC_INTERRUPT_EOC_11, + AFEC_INTERRUPT_EOC_12, + AFEC_INTERRUPT_EOC_13, + AFEC_INTERRUPT_EOC_14, + AFEC_INTERRUPT_EOC_15, + AFEC_INTERRUPT_DATA_READY, + AFEC_INTERRUPT_OVERRUN_ERROR, + AFEC_INTERRUPT_COMP_ERROR, + AFEC_INTERRUPT_END_RXBUF, + AFEC_INTERRUPT_RXBUF_FULL, + AFEC_INTERRUPT_TEMP_CHANGE, + AFEC_INTERRUPT_END_CAL, + _AFEC_NUM_OF_INTERRUPT_SOURCE, + AFEC_INTERRUPT_ALL = 0xDF00FFFF, +}; +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** AFEC interrupt source type */ +enum afec_interrupt_source { + AFEC_INTERRUPT_EOC_0 = 0, + AFEC_INTERRUPT_EOC_1, + AFEC_INTERRUPT_EOC_2, + AFEC_INTERRUPT_EOC_3, + AFEC_INTERRUPT_EOC_4, + AFEC_INTERRUPT_EOC_5, + AFEC_INTERRUPT_EOC_6, + AFEC_INTERRUPT_EOC_7, + AFEC_INTERRUPT_EOC_8, + AFEC_INTERRUPT_EOC_9, + AFEC_INTERRUPT_EOC_10, + AFEC_INTERRUPT_EOC_11, + AFEC_INTERRUPT_DATA_READY, + AFEC_INTERRUPT_OVERRUN_ERROR, + AFEC_INTERRUPT_COMP_ERROR, + AFEC_INTERRUPT_TEMP_CHANGE, + _AFEC_NUM_OF_INTERRUPT_SOURCE, + AFEC_INTERRUPT_ALL = 0x47000FFF, +}; +#endif + +typedef void (*afec_callback_t)(void); + +void afec_get_config_defaults(struct afec_config *const cfg); +void afec_ch_get_config_defaults(struct afec_ch_config *const cfg); +void afec_temp_sensor_get_config_defaults( + struct afec_temp_sensor_config *const cfg); +enum status_code afec_init(Afec *const afec, struct afec_config *const config); +void afec_temp_sensor_set_config(Afec *const afec, + struct afec_temp_sensor_config *config); +void afec_ch_set_config(Afec *const afec, const enum afec_channel_num channel, + struct afec_ch_config *config); +void afec_configure_sequence(Afec *const afec, + const enum afec_channel_num ch_list[], const uint8_t uc_num); +void afec_enable(Afec *const afec); +void afec_disable(Afec *const afec); +void afec_set_callback(Afec *const afec, enum afec_interrupt_source source, + afec_callback_t callback, uint8_t irq_level); + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +void afec_configure_auto_error_correction(Afec *const afec, + const enum afec_channel_num channel,int16_t offsetcorr, uint16_t gaincorr); + +uint32_t afec_get_correction_value(Afec *const afec, + const enum afec_channel_num afec_ch); +void afec_set_sample_hold_mode(Afec *const afec, + const enum afec_channel_num channel,const enum afec_sample_hold_mode mode); + +#endif +/** + * \internal + * \brief AFEC channel sanity check + * + * \param afec Base address of the AFEC. + * \param channel AFEC channel number. + * + */ +static inline void afec_ch_sanity_check(Afec *const afec, + const enum afec_channel_num channel) +{ + if (afec == AFEC0) { + #if defined __SAM4E8C__ || defined __SAM4E16C__ || defined __SAM4E8CB__ || defined __SAM4E16CB__ + Assert((channel < NB_CH_AFE0) || (channel == AFEC_TEMPERATURE_SENSOR)); + #elif defined __SAM4E8E__ || defined __SAM4E16E__ + Assert(channel < NB_CH_AFE0); + #elif (SAMV71 || SAMV70 || SAME70 || SAMS70) + Assert(channel < NB_CH_AFE0); + #endif + } else if (afec == AFEC1) { + Assert(channel < NB_CH_AFE1); + } + UNUSED(channel); +} + +/** + * \brief Configure conversion trigger and free run mode. + * + * \param afec Base address of the AFEC. + * \param trigger Conversion trigger. + * + */ +static inline void afec_set_trigger(Afec *const afec, + const enum afec_trigger trigger) +{ + uint32_t reg; + + reg = afec->AFEC_MR; + + if (trigger == AFEC_TRIG_FREERUN) { + reg |= AFEC_MR_FREERUN_ON; + } else { + reg &= ~(AFEC_MR_TRGSEL_Msk | AFEC_MR_TRGEN | AFEC_MR_FREERUN_ON); + reg |= trigger; + } + + afec->AFEC_MR = reg; +} + +/** + * \brief Configure conversion resolution. + * + * \param afec Base address of the AFEC. + * \param res Conversion resolution. + * + */ +static inline void afec_set_resolution(Afec *const afec, + const enum afec_resolution res) +{ + uint32_t reg; + + reg = afec->AFEC_EMR; + + reg &= ~AFEC_EMR_RES_Msk; + reg |= res; + + afec->AFEC_EMR = reg; +} + +void afec_set_comparison_mode(Afec *const afec, + const enum afec_cmp_mode mode, const enum afec_channel_num channel, + uint8_t cmp_filter); + +/** + * \brief Get comparison mode. + * + * \param afec Base address of the AFEC. + * + * \retval Compare mode value. + */ +static inline enum afec_cmp_mode afec_get_comparison_mode(Afec *const afec) +{ + return (enum afec_cmp_mode)(afec->AFEC_EMR & AFEC_EMR_CMPMODE_Msk); +} + +/** + * \brief Configure AFEC compare window. + * + * \param afec Base address of the AFEC. + * \param us_low_threshold Low threshold of compare window. + * \param us_high_threshold High threshold of compare window. + */ +static inline void afec_set_comparison_window(Afec *const afec, + const uint16_t us_low_threshold, const uint16_t us_high_threshold) +{ + afec->AFEC_CWR = AFEC_CWR_LOWTHRES(us_low_threshold) | + AFEC_CWR_HIGHTHRES(us_high_threshold); +} + +/** + * \brief Enable or disable write protection of AFEC registers. + * + * \param afec Base address of the AFEC. + * \param is_enable 1 to enable, 0 to disable. + */ +static inline void afec_set_writeprotect(Afec *const afec, + const bool is_enable) +{ + if (is_enable) { + afec->AFEC_WPMR = AFEC_WPMR_WPEN | AFEC_WPMR_WPKEY_PASSWD; + } else { + afec->AFEC_WPMR = AFEC_WPMR_WPKEY_PASSWD; + } +} + +/** + * \brief Indicate write protect status. + * + * \param afec Base address of the AFEC. + * + * \return 0 if no write protect violation occurred, or 16-bit write protect + * violation source. + */ +static inline uint32_t afec_get_writeprotect_status(Afec *const afec) +{ + uint32_t reg_value; + + reg_value = afec->AFEC_WPSR; + if (reg_value & AFEC_WPSR_WPVS) { + return (reg_value & AFEC_WPSR_WPVSRC_Msk) >> AFEC_WPSR_WPVSRC_Pos; + } else { + return 0; + } +} + +/** + * \brief Get AFEC overrun error status. + * + * \param afec Base address of the AFEC. + * + * \return AFEC overrun error status. + */ +static inline uint32_t afec_get_overrun_status(Afec *const afec) +{ + return afec->AFEC_OVER; +} + +/** + * \brief Start analog-to-digital conversion. + * + * \note If one of the hardware event is selected as AFEC trigger, + * this function can NOT start analog to digital conversion. + * + * \param afec Base address of the AFEC. + */ +static inline void afec_start_software_conversion(Afec *const afec) +{ + afec->AFEC_CR = AFEC_CR_START; +} + +void afec_set_power_mode(Afec *const afec, + const enum afec_power_mode mode); + +/** + * \brief Enable the specified AFEC channel. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + */ +static inline void afec_channel_enable(Afec *const afec, + const enum afec_channel_num afec_ch) +{ + if (afec_ch != AFEC_CHANNEL_ALL) { + afec_ch_sanity_check(afec, afec_ch); + } + + afec->AFEC_CHER = (afec_ch == AFEC_CHANNEL_ALL) ? + AFEC_CHANNEL_ALL : 1 << afec_ch; +} + +/** + * \brief Disable the specified AFEC channel. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + */ +static inline void afec_channel_disable(Afec *const afec, + const enum afec_channel_num afec_ch) +{ + if (afec_ch != AFEC_CHANNEL_ALL) { + afec_ch_sanity_check(afec, afec_ch); + } + + afec->AFEC_CHDR = (afec_ch == AFEC_CHANNEL_ALL) ? + AFEC_CHANNEL_ALL : 1 << afec_ch; +} + +/** + * \brief Get the AFEC channel status. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + * + * \retval 1 if channel is enabled. + * \retval 0 if channel is disabled. + */ +static inline uint32_t afec_channel_get_status(Afec *const afec, + const enum afec_channel_num afec_ch) +{ + afec_ch_sanity_check(afec, afec_ch); + + return afec->AFEC_CHSR & (1 << afec_ch); +} + +/** + * \brief Read the Converted Data of the selected channel. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + * + * \return AFEC converted value of the selected channel. + */ +static inline uint32_t afec_channel_get_value(Afec *const afec, + enum afec_channel_num afec_ch) +{ + afec_ch_sanity_check(afec, afec_ch); + + afec->AFEC_CSELR = afec_ch; + return afec->AFEC_CDR; +} + +/** + * \brief Set analog offset to be used for channel CSEL. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + * \param aoffset Analog offset value. + */ +static inline void afec_channel_set_analog_offset(Afec *const afec, + enum afec_channel_num afec_ch, uint16_t aoffset) +{ + afec_ch_sanity_check(afec, afec_ch); + + afec->AFEC_CSELR = afec_ch; + afec->AFEC_COCR = (aoffset & AFEC_COCR_AOFF_Msk); +} + +/** + * \brief Get the Last Data Converted. + * + * \param afec Base address of the AFEC. + * + * \return AFEC latest converted value. + */ +static inline uint32_t afec_get_latest_value(Afec *const afec) +{ + return afec->AFEC_LCDR & AFEC_LCDR_LDATA_Msk; +} + +/** + * \brief Get the Last Converted Channel Number. + * + * \param afec Base address of the AFEC. + * + * \return AFEC Last Converted Channel Number. + */ +static inline uint32_t afec_get_latest_chan_num(Afec *const afec) +{ + return (afec->AFEC_LCDR & AFEC_LCDR_CHNB_Msk) >> AFEC_LCDR_CHNB_Pos; +} + +void afec_enable_interrupt(Afec *const afec, + enum afec_interrupt_source interrupt_source); + +void afec_disable_interrupt(Afec *const afec, + enum afec_interrupt_source interrupt_source); + +/** + * \brief Get AFEC interrupt status. + * + * \param afec Base address of the AFEC. + * + * \return The interrupt status value. + */ +static inline uint32_t afec_get_interrupt_status(Afec *const afec) +{ + return afec->AFEC_ISR; +} + +/** + * \brief Get AFEC interrupt mask. + * + * \param afec Base address of the AFEC. + * + * \return The interrupt mask value. + */ +static inline uint32_t afec_get_interrupt_mask(Afec *const afec) +{ + return afec->AFEC_IMR; +} + +#if SAM4E +/** + * \brief Get PDC registers base address. + * + * \param afec Base address of the AFEC. + * + * \return AFEC PDC register base address. + */ +static inline Pdc *afec_get_pdc_base(Afec *const afec) +{ + Pdc *p_pdc_base = NULL; + +#ifdef PDC_AFEC0 + if (afec == AFEC0) { + p_pdc_base = PDC_AFEC0; + } +#endif + +#ifdef PDC_AFEC1 + else if (afec == AFEC1) { + p_pdc_base = PDC_AFEC1; + } +#endif + + return p_pdc_base; +} + +/** + * \brief Launch an automatic calibration of the AFEC on next sequence. + * + * \param afec Base address of the AFEC. + * + * \retval STATUS_OK An automatic calibration is launched. + * \retval STATUS_ERR_BUSY Automatic calibration can not be launched because + * the AFEC is in freerun mode. + */ +static inline enum status_code afec_start_calibration(Afec *const afec) +{ + uint32_t reg; + + reg = afec->AFEC_CHSR; + afec->AFEC_CDOR = reg; + + if ((afec->AFEC_MR & AFEC_MR_FREERUN) == AFEC_MR_FREERUN_ON) { + return STATUS_ERR_BUSY; + } + afec->AFEC_CR = AFEC_CR_AUTOCAL; + return STATUS_OK; +} +#endif + +/** + * \page sam_afec_quickstart Quickstart guide for SAM AFEC driver + * + * This is the quickstart guide for the \ref sam_drivers_afec_group + * "SAM AFEC driver" with step-by-step instructions on how to configure and use + * the driver in a selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section afec_basic_use_case Basic use case + * In this basic use case, the AFEC module and single channel are configured for: + * - 12 -bit resolution + * - AFEC clock frequency is 6MHz + * - Start Up Time is 64 periods AFEC clock + * - Analog Settling Time is 3 periods of AFEC clock + * - Tracking Time is 3 periods of AFEC clock + * - Transfer Period is 5 periods AFEC clock + * - Allows different analog settings for each channel + * - The controller converts channels in a simple numeric order + * - Appends the channel number to the conversion result in AFE_LDCR register + * - Only a Single Trigger is required to get an averaged value + * - AFE Bias Current Control value is 1 + * - Software triggering of conversions + * - Single channel measurement + * - AFEC_CHANNEL_5 of AFEC0 as input + * + * \subsection sam_afec_quickstart_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (Sysclock)" + * + * \section afec_basic_use_case_setup Setup steps + * \subsection afec_basic_use_case_setup_code Example code + * Add to application C-file: + * \code + afec_enable(AFEC0); + afec_get_config_defaults(&afec_cfg); + afec_init(AFEC0, &afec_cfg); + afec_set_trigger(AFEC0, AFEC_TRIG_SW); + afec_channel_enable(AFEC0, AFEC_CHANNEL_5); +\endcode + * + * \subsection afec_basic_use_case_setup_flow Workflow + * -# Enable AFEC Module: + * - \code afec_enable(AFEC0); \endcode + * -# Get the AFEC default configurations: + * - \code afec_get_config_defaults(&afec_cfg); \endcode + * -# Initialize the AFEC Module: + * - \code afec_init(AFEC0, &afec_cfg); \endcode + * -# Configure conversion trigger and free run mode: + * - \code afec_set_trigger(AFEC0, AFEC_TRIG_SW); \endcode + * -# Enable Channel: + * - \code afec_channel_enable(AFEC0, AFEC_CHANNEL_5); \endcode + * + * \section afec_basic_use_case_usage Usage steps + * \subsection afec_basic_use_case_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + afec_start_software_conversion(AFEC0); + while (afec_get_interrupt_status(AFEC0) & (1 << AFEC_CHANNEL_5)); + uint32_t result = afec_channel_get_value(AFEC0, AFEC_CHANNEL_5); +\endcode + * + * \subsection afec_basic_use_case_usage_flow Workflow + * -# Start AFEC conversion on channel: + * - \code afec_start_software_conversion(AFEC0); \endcode + * -# Wait for the conversion over: + * - \code while (afec_get_interrupt_status(AFEC0) & (1 << AFEC_CHANNEL_5)); +\endcode + * -# Get the conversion result: + * - \code uint32_t result = afec_channel_get_value(AFEC0, AFEC_CHANNEL_5); +\endcode + */ +#endif /* AFEC_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/dacc/dacc.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/dacc/dacc.c new file mode 100644 index 00000000..5378389d --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/dacc/dacc.c @@ -0,0 +1,646 @@ +/** + * \file + * + * \brief Digital-to-Analog Converter Controller (DACC) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "dacc.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_dacc_group Digital-to-Analog Converter Controller (DACC) + * + * \par Purpose + * + * Driver for the Digital-to-Analog Converter Controller. It provides access to the main + * features of the DAC controller. + * + * \par Usage + * + * -# DACC clock should be enabled before using it. + * - \ref sysclk_enable_peripheral_clock() can be used to enable the clock. + * -# Reset DACC with \ref dacc_reset(). + * -# If DACC can be enabled/disabled, uses \ref dacc_enable() and + * \ref dacc_disable(). + * -# Initialize DACC timing with \ref dacc_set_timing() (different DAC + * peripheral may require different parameters). + * -# Write conversion data with \ref dacc_write_conversion_data(). + * -# Configure trigger with \ref dacc_set_trigger() + * and \ref dacc_disable_trigger(). + * -# Configure FIFO transfer mode with \ref dacc_set_transfer_mode(). + * -# Control interrupts with \ref dacc_enable_interrupt(), + * \ref dacc_disable_interrupt(), \ref dacc_get_interrupt_mask() and + * \ref dacc_get_interrupt_status(). + * -# DACC registers support write protect with \ref dacc_set_writeprotect() + * and \ref dacc_get_writeprotect_status(). + * -# If the DACC can work with PDC, use \ref dacc_get_pdc_base() to get + * PDC register base for the DAC controller. + * -# If the DACC has several channels to process, the following functions can + * be used: + * - Enable/Disable TAG and select output channel selection by + * \ref dacc_set_channel_selection(), + * \ref dacc_enable_flexible_channel_selection(). + * - Enable/disable channel by \ref dacc_enable_channel() / + * \ref dacc_disable_channel(), get channel status by + * \ref dacc_get_channel_status(). + * + * \section dependencies Dependencies + * This driver does not depend on other modules. + * + * @{ + */ + +//! Max channel number +#if (SAM3N) || (SAM4L) || (SAM4N) +# define MAX_CH_NB 0 +#else +# define MAX_CH_NB 1 +#endif + +//! DACC Write Protect Key "DAC" in ASCII +#define DACC_WP_KEY (0x444143) + +#ifndef DACC_WPMR_WPKEY_PASSWD +# define DACC_WPMR_WPKEY_PASSWD DACC_WPMR_WPKEY(DACC_WP_KEY) +#endif + +/** + * \brief Reset DACC. + * + * \param p_dacc Pointer to a DACC instance. + */ +void dacc_reset(Dacc *p_dacc) +{ + p_dacc->DACC_CR = DACC_CR_SWRST; +} + +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Enable trigger and set the trigger source. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_trigger Trigger source number. + * \param channel Channel to be set + * + * \return \ref DACC_RC_OK for OK. + */ +uint32_t dacc_set_trigger(Dacc *p_dacc, uint32_t ul_trigger, uint32_t channel) +{ + if(channel == 0) { + uint32_t mr = p_dacc->DACC_TRIGR & (~(DACC_TRIGR_TRGSEL0_Msk)); + p_dacc->DACC_TRIGR = mr | DACC_TRIGR_TRGEN0_EN | DACC_TRIGR_TRGSEL0(ul_trigger); + }else if(channel == 1) { + uint32_t mr = p_dacc->DACC_TRIGR & (~(DACC_TRIGR_TRGSEL1_Msk)); + p_dacc->DACC_TRIGR = mr | DACC_TRIGR_TRGEN1_EN | DACC_TRIGR_TRGSEL1(ul_trigger); + + } + return DACC_RC_OK; +} +#else +/** + * \brief Enable trigger and set the trigger source. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_trigger Trigger source number. + * + * \return \ref DACC_RC_OK for OK. + */ +uint32_t dacc_set_trigger(Dacc *p_dacc, uint32_t ul_trigger) +{ + uint32_t mr = p_dacc->DACC_MR & (~(DACC_MR_TRGSEL_Msk)); +#if (SAM3N) || (SAM4L) || (SAM4N) + p_dacc->DACC_MR = mr + | DACC_MR_TRGEN + | ((ul_trigger << DACC_MR_TRGSEL_Pos) & DACC_MR_TRGSEL_Msk); +#else + p_dacc->DACC_MR = mr | DACC_MR_TRGEN_EN | DACC_MR_TRGSEL(ul_trigger); +#endif + return DACC_RC_OK; +} +#endif + +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Disable trigger (free run mode). + * + * \param p_dacc Pointer to a DACC instance. + * \param channel Channel to be disabled + */ +void dacc_disable_trigger(Dacc *p_dacc, uint32_t channel) +{ + if(channel == 0) { + p_dacc->DACC_TRIGR &= ~(DACC_TRIGR_TRGEN0_EN); + }else if(channel == 1) { + p_dacc->DACC_TRIGR &= ~(DACC_TRIGR_TRGEN1_EN); + } +} +#else +/** + * \brief Disable trigger (free run mode). + * + * \param p_dacc Pointer to a DACC instance. + */ +void dacc_disable_trigger(Dacc *p_dacc) +{ + p_dacc->DACC_MR &= ~DACC_MR_TRGEN; +} +#endif + +/** + * \brief Set the transfer mode. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_mode Transfer mode configuration. + * + * \return \ref DACC_RC_OK for OK. + */ +uint32_t dacc_set_transfer_mode(Dacc *p_dacc, uint32_t ul_mode) +{ + if (ul_mode) { +#if (SAM3N) || (SAM4L) || (SAM4N) + p_dacc->DACC_MR |= DACC_MR_WORD; +#elif (SAM4S) || (SAM4E) + p_dacc->DACC_MR |= DACC_MR_ONE; + p_dacc->DACC_MR |= DACC_MR_WORD_WORD; +#elif (SAMV70 || SAMV71 || SAME70 || SAMS70) + p_dacc->DACC_MR = ul_mode; +#else + p_dacc->DACC_MR |= DACC_MR_WORD_WORD; +#endif + } else { +#if (SAM3N) || (SAM4L) || (SAM4N) + p_dacc->DACC_MR &= (~DACC_MR_WORD); +#elif (SAM4S) || (SAM4E) + p_dacc->DACC_MR |= DACC_MR_ONE; + p_dacc->DACC_MR &= (~DACC_MR_WORD_WORD); +#elif (SAMV70 || SAMV71 || SAME70 || SAMS70) + p_dacc->DACC_MR = ul_mode; +#else + p_dacc->DACC_MR &= (~DACC_MR_WORD_WORD); +#endif + } + return DACC_RC_OK; +} + +/** + * \brief Enable DACC interrupts. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_interrupt_mask The interrupt mask. + */ +void dacc_enable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask) +{ + p_dacc->DACC_IER = ul_interrupt_mask; +} + +/** + * \brief Disable DACC interrupts. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_interrupt_mask The interrupt mask. + */ +void dacc_disable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask) +{ + p_dacc->DACC_IDR = ul_interrupt_mask; +} + +/** + * \brief Get the interrupt mask. + * + * \param p_dacc Pointer to a DACC instance. + * + * \return The interrupt mask. + */ +uint32_t dacc_get_interrupt_mask(Dacc *p_dacc) +{ + return p_dacc->DACC_IMR; +} + +/** + * \brief Get the interrupt status. + * + * \param p_dacc Pointer to a DACC instance. + * + * \return The interrupt status. + */ +uint32_t dacc_get_interrupt_status(Dacc *p_dacc) +{ + return p_dacc->DACC_ISR; +} + +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Write data to conversion register. + * + * \note The \a ul_data could be output data or data with channel TAG when + * flexible mode is used. + * + * In flexible mode the 2 bits, DACC_CDR[13:12] which are otherwise unused, + * are employed to select the channel in the same way as with the USER_SEL + * field. Finally, if the WORD field is set, the 2 bits, DACC_CDR[13:12] are + * used for channel selection of the first data and the 2 bits, + * DACC_CDR[29:28] for channel selection of the second data. + * + * \see dacc_enable_flexible_selection() + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_data The data to be transferred to analog value. + * \param channel The channel to convert the data ul_data + */ +void dacc_write_conversion_data(Dacc *p_dacc, uint32_t ul_data, uint32_t channel) +{ + p_dacc->DACC_CDR[channel] = ul_data; +} +#else +/** + * \brief Write data to conversion register. + * + * \note The \a ul_data could be output data or data with channel TAG when + * flexible mode is used. + * + * In flexible mode the 2 bits, DACC_CDR[13:12] which are otherwise unused, + * are employed to select the channel in the same way as with the USER_SEL + * field. Finally, if the WORD field is set, the 2 bits, DACC_CDR[13:12] are + * used for channel selection of the first data and the 2 bits, + * DACC_CDR[29:28] for channel selection of the second data. + * + * \see dacc_enable_flexible_selection() + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_data The data to be transferred to analog value. + */ +void dacc_write_conversion_data(Dacc *p_dacc, uint32_t ul_data) +{ + p_dacc->DACC_CDR = ul_data; +} +#endif + +/** + * \brief Enable or disable write protect of DACC registers. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_enable 1 to enable, 0 to disable. + */ +void dacc_set_writeprotect(Dacc *p_dacc, uint32_t ul_enable) +{ + if (ul_enable) { + p_dacc->DACC_WPMR = DACC_WPMR_WPKEY_PASSWD + | DACC_WPMR_WPEN; + } else { + p_dacc->DACC_WPMR = DACC_WPMR_WPKEY_PASSWD; + } +} + +/** + * \brief Get the write protect status. + * + * \param p_dacc Pointer to a DACC instance. + * + * \return Write protect status. + */ +uint32_t dacc_get_writeprotect_status(Dacc *p_dacc) +{ + return p_dacc->DACC_WPSR; +} + +#if !(SAM4L || SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Get PDC registers base address. + * + * \param p_dacc Pointer to a DACC instance. + * + * \return DACC PDC register base address. + */ +Pdc *dacc_get_pdc_base(Dacc *p_dacc) +{ + /* avoid Cppcheck Warning */ + UNUSED(p_dacc); + return PDC_DACC; +} +#endif + +#if (SAM3N) || (SAM4L) || (SAM4N) || defined(__DOXYGEN__) +/** + * \brief Enable DACC. + * + * \param p_dacc Pointer to a DACC instance. + */ +void dacc_enable(Dacc *p_dacc) +{ + p_dacc->DACC_MR |= DACC_MR_DACEN; +} + +/** + * \brief Disable DACC. + * + * \param p_dacc Pointer to a DACC instance. + * + * \return \ref DACC_RC_OK for OK. + */ +void dacc_disable(Dacc *p_dacc) +{ + p_dacc->DACC_MR &= (~DACC_MR_DACEN); +} + +/** + * \brief Set the DACC timing. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_startup Startup time selection. + * \param ul_clock_divider Clock divider for internal trigger. + * + * \return \ref DACC_RC_OK for OK. + */ +uint32_t dacc_set_timing(Dacc *p_dacc, uint32_t ul_startup, + uint32_t ul_clock_divider) +{ + uint32_t mr = p_dacc->DACC_MR + & ~(DACC_MR_STARTUP_Msk | DACC_MR_CLKDIV_Msk); + p_dacc->DACC_MR = mr | DACC_MR_STARTUP(ul_startup) + | DACC_MR_CLKDIV(ul_clock_divider); + return DACC_RC_OK; +} +#endif /* #if (SAM3N) || (SAM4L) || (SAM4N) */ + +#if (SAM3S) || (SAM3XA) || (SAM4S) || (SAM4E) || SAMV70 || SAMV71 || SAME70 || SAMS70 || defined(__DOXYGEN__) +#if !(SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Disable flexible (TAG) mode and select a channel for DAC outputs. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_channel Channel to select. + * + * \return \ref DACC_RC_OK if successful. + */ +uint32_t dacc_set_channel_selection(Dacc *p_dacc, uint32_t ul_channel) +{ + uint32_t mr = p_dacc->DACC_MR & (~DACC_MR_USER_SEL_Msk); + if (ul_channel > MAX_CH_NB) { + return DACC_RC_INVALID_PARAM; + } + mr &= ~(DACC_MR_TAG); + mr |= ul_channel << DACC_MR_USER_SEL_Pos; + p_dacc->DACC_MR = mr; + + return DACC_RC_OK; +} + +/** + * \brief Enable the flexible channel selection mode (TAG). + * + * In this mode the 2 bits, DACC_CDR[13:12] which are otherwise unused, are + * employed to select the channel in the same way as with the USER_SEL field. + * Finally, if the WORD field is set, the 2 bits, DACC_CDR[13:12] are used + * for channel selection of the first data and the 2 bits, DACC_CDR[29:28] + * for channel selection of the second data. + * + * \param p_dacc Pointer to a DACC instance. + */ +void dacc_enable_flexible_selection(Dacc *p_dacc) +{ + p_dacc->DACC_MR |= DACC_MR_TAG; +} +#endif + +#if (SAM3S) || (SAM3XA) || defined(__DOXYGEN__) +/** + * \brief Set the power save mode. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_sleep_mode Sleep mode configuration. + * \param ul_fast_wakeup_mode Fast wakeup mode configuration. + * + * \return \ref DACC_RC_OK if successful. + */ +uint32_t dacc_set_power_save(Dacc *p_dacc, + uint32_t ul_sleep_mode, uint32_t ul_fast_wakeup_mode) +{ + if (ul_sleep_mode) { + p_dacc->DACC_MR |= DACC_MR_SLEEP; + } else { + p_dacc->DACC_MR &= (~DACC_MR_SLEEP); + } + if (ul_fast_wakeup_mode) { + p_dacc->DACC_MR |= DACC_MR_FASTWKUP; + } else { + p_dacc->DACC_MR &= (~DACC_MR_FASTWKUP); + } + return DACC_RC_OK; +} +#endif /* (SAM3S) || (SAM3XA) */ + +#if !(SAMV70 || SAMV71 || SAME70 || SAMS70 || SAM4E) +/** + * \brief Set DACC timings. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_refresh Refresh period setting value. + * \param ul_maxs Max speed mode configuration. + * \param ul_startup Startup time selection. + * + * \return \ref DACC_RC_OK for OK. + */ +uint32_t dacc_set_timing(Dacc *p_dacc, + uint32_t ul_refresh, uint32_t ul_maxs, uint32_t ul_startup) +{ + uint32_t mr = p_dacc->DACC_MR + & (~(DACC_MR_REFRESH_Msk | DACC_MR_STARTUP_Msk)); + mr |= DACC_MR_REFRESH(ul_refresh); + if (ul_maxs) { + mr |= DACC_MR_MAXS; + } else { + mr &= ~DACC_MR_MAXS; + } + mr |= (DACC_MR_STARTUP_Msk & ((ul_startup) << DACC_MR_STARTUP_Pos)); + + p_dacc->DACC_MR = mr; + return DACC_RC_OK; +} +#endif + +#if (SAM4E) +/** + * \brief Set DACC timings. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_maxs Max speed mode configuration. + * \param ul_startup Startup time selection. + * + * \return \ref DACC_RC_OK for OK. + */ +uint32_t dacc_set_timing(Dacc *p_dacc, + uint32_t ul_maxs, uint32_t ul_startup) +{ + uint32_t mr = p_dacc->DACC_MR + & (~(DACC_MR_REFRESH_Msk | DACC_MR_STARTUP_Msk)); + if (ul_maxs) { + mr |= DACC_MR_MAXS; + } else { + mr &= ~DACC_MR_MAXS; + } + mr |= (DACC_MR_STARTUP_Msk & ((ul_startup) << DACC_MR_STARTUP_Pos)); + + p_dacc->DACC_MR = mr; + return DACC_RC_OK; +} +#endif + +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Set DACC prescaler. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_prescaler Prescaler value. + * + * \return \ref DACC_RC_OK for OK. + */ +uint32_t dacc_set_prescaler(Dacc *p_dacc, uint32_t ul_prescaler) +{ + uint32_t mr = p_dacc->DACC_MR & (~DACC_MR_PRESCALER_Msk); + p_dacc->DACC_MR = mr | DACC_MR_PRESCALER(ul_prescaler); + return DACC_RC_OK; +} + +/** + * \brief Set DACC osr. + * + * \param p_dacc Pointer to a DACC instance. + * \param channel DACC osr channel to be set. + * \param ul_prescaler Osr value. + * + * \return \ref DACC_RC_OK for OK. + */ +uint32_t dacc_set_osr(Dacc *p_dacc, uint32_t channel, uint32_t ul_osr) +{ + uint32_t mr = p_dacc->DACC_TRIGR; + if(channel == 0) { + mr &= (~DACC_TRIGR_OSR0_Msk); + mr |= DACC_TRIGR_OSR0(ul_osr); + }else if(channel == 1) { + mr &= (~DACC_TRIGR_OSR1_Msk); + mr |= DACC_TRIGR_OSR1(ul_osr); + } + p_dacc->DACC_TRIGR = mr; + return DACC_RC_OK; +} +#endif + +/** + * \brief Enable DACC channel. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_channel The output channel to enable. + * + * \return \ref DACC_RC_OK for OK. + */ +uint32_t dacc_enable_channel(Dacc *p_dacc, uint32_t ul_channel) +{ + if (ul_channel > MAX_CH_NB) + return DACC_RC_INVALID_PARAM; + + p_dacc->DACC_CHER = DACC_CHER_CH0 << ul_channel; + return DACC_RC_OK; +} + +/** + * \brief Disable DACC channel. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_channel The output channel to disable. + * + * \return \ref DACC_RC_OK for OK. + */ +uint32_t dacc_disable_channel(Dacc *p_dacc, uint32_t ul_channel) +{ + if (ul_channel > MAX_CH_NB) { + return DACC_RC_INVALID_PARAM; + } + p_dacc->DACC_CHDR = DACC_CHDR_CH0 << ul_channel; + return DACC_RC_OK; +} + +/** + * \brief Get the channel status. + * + * \param p_dacc Pointer to a DACC instance. + * + * \return DACC channel status. + */ +uint32_t dacc_get_channel_status(Dacc *p_dacc) +{ + return p_dacc->DACC_CHSR; +} + +/** + * \brief Set the analog control value. + * + * \param p_dacc Pointer to a DACC instance. + * \param ul_analog_control Analog control configuration. + * + * \return \ref DACC_RC_OK for OK. + */ +uint32_t dacc_set_analog_control(Dacc *p_dacc, uint32_t ul_analog_control) +{ + p_dacc->DACC_ACR = ul_analog_control; + return DACC_RC_OK; +} + +/** + * \brief Get the analog control value. + * + * \param p_dacc Pointer to a DACC instance. + * + * \return Current setting of analog control. + */ +uint32_t dacc_get_analog_control(Dacc *p_dacc) +{ + return p_dacc->DACC_ACR; +} +#endif /* (SAM3S) || (SAM3XA) || (SAM4S) || (SAM4E) || (SAMV70) || (SAMV71) || (SAME70) || (SAMS70) */ + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/dacc/dacc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/dacc/dacc.h new file mode 100644 index 00000000..62a13d6a --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/dacc/dacc.h @@ -0,0 +1,140 @@ +/** + * \file + * + * \brief Digital-to-Analog Converter Controller (DACC) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef DACC_H_INCLUDED +#define DACC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +//! DACC return codes +typedef enum dacc_rc { + DACC_RC_OK = 0, //!< Operation OK + DACC_RC_INVALID_PARAM //!< Invalid parameter +} dacc_rc_t; + +#if (SAM3N) || (SAM4L) || (SAM4N) +//! DACC resolution in number of data bits +# define DACC_RESOLUTION 10 +#else +//! DACC resolution in number of data bits +# define DACC_RESOLUTION 12 +#endif +//! DACC max data value +#define DACC_MAX_DATA ((1 << DACC_RESOLUTION) - 1) + + +void dacc_reset(Dacc *p_dacc); +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +uint32_t dacc_set_trigger(Dacc *p_dacc, uint32_t ul_trigger, uint32_t channel); +#else +uint32_t dacc_set_trigger(Dacc *p_dacc, uint32_t ul_trigger); +#endif +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +void dacc_disable_trigger(Dacc *p_dacc, uint32_t channel); +#else +void dacc_disable_trigger(Dacc *p_dacc); +#endif +uint32_t dacc_set_transfer_mode(Dacc *p_dacc, uint32_t ul_mode); +void dacc_enable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask); +void dacc_disable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask); +uint32_t dacc_get_interrupt_mask(Dacc *p_dacc); +uint32_t dacc_get_interrupt_status(Dacc *p_dacc); +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +void dacc_write_conversion_data(Dacc *p_dacc, uint32_t ul_data, uint32_t channel); +#else +void dacc_write_conversion_data(Dacc *p_dacc, uint32_t ul_data); +#endif +void dacc_set_writeprotect(Dacc *p_dacc, uint32_t ul_enable); +uint32_t dacc_get_writeprotect_status(Dacc *p_dacc); +#if !(SAM4L || SAMV70 || SAMV71 || SAME70 || SAMS70) +Pdc *dacc_get_pdc_base(Dacc *p_dacc); +#endif + +#if (SAM3N) || (SAM4L) || (SAM4N) || defined(__DOXYGEN__) +void dacc_enable(Dacc *p_dacc); +void dacc_disable(Dacc *p_dacc); +uint32_t dacc_set_timing(Dacc *p_dacc, uint32_t ul_startup, + uint32_t ul_clock_divider); +#endif + +#if (SAM4E) +uint32_t dacc_set_timing(Dacc *p_dacc, + uint32_t ul_maxs,uint32_t ul_startup); +#endif + +#if (SAM3S) || (SAM3XA) || (SAM4S) || (SAM4E) || (SAMV70) || (SAMV71) || (SAME70) || (SAMS70) || defined(__DOXYGEN__) +#if !(SAMV70 || SAMV71 || SAME70 || SAMS70) +uint32_t dacc_set_channel_selection(Dacc *p_dacc, uint32_t ul_channel); +void dacc_enable_flexible_selection(Dacc *p_dacc); +#endif + +#if (SAM3S) || (SAM3XA) +uint32_t dacc_set_power_save(Dacc *p_dacc, uint32_t ul_sleep_mode, + uint32_t ul_fast_wakeup_mode); +#endif + +#if !(SAMV70 || SAMV71 || SAME70 || SAMS70 || SAM4E) +uint32_t dacc_set_timing(Dacc *p_dacc, uint32_t ul_refresh, uint32_t ul_maxs, + uint32_t ul_startup); +#endif +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +uint32_t dacc_set_prescaler(Dacc *p_dacc, uint32_t ul_prescaler); +uint32_t dacc_set_osr(Dacc *p_dacc, uint32_t channel, uint32_t ul_osr); +#endif +uint32_t dacc_enable_channel(Dacc *p_dacc, uint32_t ul_channel); +uint32_t dacc_disable_channel(Dacc *p_dacc, uint32_t ul_channel); +uint32_t dacc_get_channel_status(Dacc *p_dacc); +uint32_t dacc_set_analog_control(Dacc *p_dacc, uint32_t ul_analog_control); +uint32_t dacc_get_analog_control(Dacc *p_dacc); +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* DACC_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/mpu/mpu.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/mpu/mpu.c new file mode 100644 index 00000000..75cefa3b --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/mpu/mpu.c @@ -0,0 +1,178 @@ +/** + * \file + * + * \brief SAMV70/SAMV71/SAME70/SAMS70-XULTRA board mpu config. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "mpu.h" + +/** + * \defgroup sam_drivers_mpu_group MPU - Memory Protect Unit + * @{ + */ + +/** \file */ + +/** + * \addtogroup mmu MMU Initialization + * + * \section Usage + * + * Translation Look-aside Buffers (TLBs) are an implementation technique that + * caches translations or translation table entries. TLBs avoid the requirement + * for every memory access to perform a translation table lookup. + * The ARM architecture does not specify the exact form of the TLB structures + * for any design. In a similar way to the requirements for caches, the + * architecture only defines certain principles for TLBs: + * + * The MMU supports memory accesses based on memory sections or pages: + * Super-sections Consist of 16MB blocks of memory. Support for Super sections + * is optional. + * -# Sections Consist of 1MB blocks of memory. + * -# Large pages Consist of 64KB blocks of memory. + * -# Small pages Consist of 4KB blocks of memory. + * + * Access to a memory region is controlled by the access permission bits and + * the domain field in the TLB entry. + * Memory region attributes + * Each TLB entry has an associated set of memory region attributes. These + * control accesses to the caches, + * how the write buffer is used, and if the memory region is Shareable and + * therefore must be kept coherent. + * + * Related files:\n + * \ref mmu.c\n + * \ref mmu.h \n + */ + +/*---------------------------------------------------------------------------- + * Exported functions + + *----------------------------------------------------------------------------*/ +/** + * \brief Enables the MPU module. + * + * \param dwMPUEnable Enable/Disable the memory region. + */ +void mpu_enable(uint32_t dw_mpu_enable) +{ + MPU->CTRL = dw_mpu_enable ; +} + +/** + * \brief Set active memory region. + * + * \param dwRegionNum The memory region to be active. + */ +void mpu_set_region_num(uint32_t dw_region_num) +{ + MPU->RNR = dw_region_num; +} + +/** + * \brief Disable the current active region. + */ +void mpu_disable_region(void) +{ + MPU->RASR &= 0xfffffffe; +} + +/** + * \brief Setup a memory region. + * + * \param dwRegionBaseAddr Memory region base address. + * \param dwRegionAttr Memory region attributes. + */ +void mpu_set_region(uint32_t dw_region_base_addr, uint32_t dw_region_attr) +{ + MPU->RBAR = dw_region_base_addr; + MPU->RASR = dw_region_attr; +} + + +/** + * \brief Calculate region size for the RASR. + */ +uint32_t mpu_cal_mpu_region_size(uint32_t dw_actual_size_in_bytes) +{ + uint32_t dwRegionSize = 32; + uint32_t dwReturnValue = 4; + + while( dwReturnValue < 31 ) { + if( dw_actual_size_in_bytes <= dwRegionSize ) { + break; + } else { + dwReturnValue++; + } + dwRegionSize <<= 1; + } + + return ( dwReturnValue << 1 ); +} + + +/** + * \brief Update MPU regions. + * + * \return Unused (ANSI-C compatibility). + */ +void mpu_update_regions(uint32_t dw_region_num, uint32_t dw_region_base_addr, uint32_t dw_region_attr) +{ + volatile irqflags_t flags; + + /* Get and clear the global interrupt flags */ + flags = cpu_irq_save(); + + /* Clean up data and instruction buffer */ + __DSB(); + __ISB(); + + /* Set active region */ + mpu_set_region_num(dw_region_num); + + /* Disable region */ + mpu_disable_region(); + + /* Update region attribute */ + mpu_set_region( dw_region_base_addr, dw_region_attr); + + /* Clean up data and instruction buffer to make the new region taking + effect at once */ + __DSB(); + __ISB(); + + /* Restore global interrupt flags */ + cpu_irq_restore(flags); +} + +//@} diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/mpu/mpu.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/mpu/mpu.h new file mode 100644 index 00000000..97019db3 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/mpu/mpu.h @@ -0,0 +1,190 @@ +/** + * \file + * + * \brief SAMV70/SAMV71/SAME70/SAMS70-XULTRA board mpu config. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + + +#ifndef _MPU_H_ +#define _MPU_H_ + +#include "compiler.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +#define ARM_MODE_USR 0x10 + +#define PRIVILEGE_MODE 0 +#define USER_MODE 1 + +#define MPU_DEFAULT_ITCM_REGION ( 1 ) +#define MPU_DEFAULT_IFLASH_REGION ( 2 ) +#define MPU_DEFAULT_DTCM_REGION ( 3 ) +#define MPU_DEFAULT_SRAM_REGION_1 ( 4 ) +#define MPU_DEFAULT_SRAM_REGION_2 ( 5 ) +#define MPU_PERIPHERALS_REGION ( 6 ) +#define MPU_EXT_EBI_REGION ( 7 ) +#define MPU_DEFAULT_SDRAM_REGION ( 8 ) +#define MPU_QSPIMEM_REGION ( 9 ) +#define MPU_USBHSRAM_REGION ( 10 ) +#if defined MPU_HAS_NOCACHE_REGION +#define MPU_NOCACHE_SRAM_REGION ( 11 ) +#endif + +#define MPU_REGION_VALID ( 0x10 ) +#define MPU_REGION_ENABLE ( 0x01 ) +#define MPU_REGION_DISABLE ( 0x0 ) + +#define MPU_ENABLE ( 0x1 << MPU_CTRL_ENABLE_Pos) +#define MPU_HFNMIENA ( 0x1 << MPU_CTRL_HFNMIENA_Pos ) +#define MPU_PRIVDEFENA ( 0x1 << MPU_CTRL_PRIVDEFENA_Pos ) + + +#define MPU_REGION_BUFFERABLE ( 0x01 << MPU_RASR_B_Pos ) +#define MPU_REGION_CACHEABLE ( 0x01 << MPU_RASR_C_Pos ) +#define MPU_REGION_SHAREABLE ( 0x01 << MPU_RASR_S_Pos ) + +#define MPU_REGION_EXECUTE_NEVER ( 0x01 << MPU_RASR_XN_Pos ) + +#define MPU_AP_NO_ACCESS ( 0x00 << MPU_RASR_AP_Pos ) +#define MPU_AP_PRIVILEGED_READ_WRITE ( 0x01 << MPU_RASR_AP_Pos ) +#define MPU_AP_UNPRIVILEGED_READONLY ( 0x02 << MPU_RASR_AP_Pos ) +#define MPU_AP_FULL_ACCESS ( 0x03 << MPU_RASR_AP_Pos ) +#define MPU_AP_RES ( 0x04 << MPU_RASR_AP_Pos ) +#define MPU_AP_PRIVILEGED_READONLY ( 0x05 << MPU_RASR_AP_Pos ) +#define MPU_AP_READONLY ( 0x06 << MPU_RASR_AP_Pos ) +#define MPU_AP_READONLY2 ( 0x07 << MPU_RASR_AP_Pos ) + +#define MPU_TEX_B000 ( 0x00 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B001 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B010 ( 0x02 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B011 ( 0x03 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B100 ( 0x04 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B101 ( 0x05 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B110 ( 0x06 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B111 ( 0x07 << MPU_RASR_TEX_Pos ) + +#define SHAREABLE 1 +#define NON_SHAREABLE 0 + +#define INNER_NORMAL_WB_RWA_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) +#define INNER_NORMAL_WB_NWA_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( ENABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) +#define INNER_OUTER_NORMAL_NOCACHE_TYPE(x) ((0x01 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define STRONGLY_ORDERED_SHAREABLE_TYPE (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos )) // DO not care // +#define SHAREABLE_DEVICE_TYPE (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos )) // DO not care // + + +/* Default memory map + Address range Memory region Memory type Shareability Cache policy + 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT + 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA + 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - + 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA + 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT + 0xA0000000- 0xBFFFFFFF Device Device Shareable + 0xC0000000- 0xDFFFFFFF Device Device Non Shareable + 0xE0000000- 0xFFFFFFFF System - - + */ + +/********* IFLASH memory macros *********************/ +#define ITCM_START_ADDRESS 0x00000000UL +#define ITCM_END_ADDRESS 0x003FFFFFUL +#define IFLASH_START_ADDRESS 0x00400000UL +#define IFLASH_END_ADDRESS 0x005FFFFFUL + + +#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS) +#define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF) + +#define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1) +#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS) + +/**************** DTCM *******************************/ +#define DTCM_START_ADDRESS 0x20000000UL +#define DTCM_END_ADDRESS 0x203FFFFFUL + + +/******* SRAM memory macros ***************************/ + +#define SRAM_START_ADDRESS 0x20400000UL +#define SRAM_END_ADDRESS 0x2045FFFFUL + +#if defined MPU_HAS_NOCACHE_REGION +#define NOCACHE_SRAM_REGION_SIZE 0x1000 +#endif + +/* Regions should be a 2^(N+1) where 4 < N < 31 */ +#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS) +#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB + +#if defined MPU_HAS_NOCACHE_REGION +#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1) +#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE ) // (2^17) 128 - 0x1000 KB +#define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1) +#define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS ) +#else +#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1) +#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB +#endif +/************** Peripherals memory region macros ********/ +#define PERIPHERALS_START_ADDRESS 0x40000000UL +#define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/******* Ext EBI memory macros ***************************/ +#define EXT_EBI_START_ADDRESS 0x60000000UL +#define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL + +/******* Ext-SRAM memory macros ***************************/ +#define SDRAM_START_ADDRESS 0x70000000UL +#define SDRAM_END_ADDRESS 0x7FFFFFFFUL + +/******* QSPI macros ***************************/ +#define QSPI_START_ADDRESS 0x80000000UL +#define QSPI_END_ADDRESS 0x9FFFFFFFUL + +/************** USBHS_RAM region macros ******************/ +#define USBHSRAM_START_ADDRESS 0xA0100000UL +#define USBHSRAM_END_ADDRESS 0xA01FFFFFUL + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ +void mpu_enable(uint32_t dw_mpu_enable); +void mpu_set_region(uint32_t dw_region_base_addr, uint32_t dw_region_attr); +void mpu_set_region_num(uint32_t dw_region_num); +void mpu_disable_region(void); +uint32_t mpu_cal_mpu_region_size(uint32_t dw_actual_size_in_bytes); +void mpu_update_regions(uint32_t dw_region_num, uint32_t dw_region_base_addr, uint32_t dw_region_attr); + +#endif /* #ifndef _MPU_H_ */ \ No newline at end of file diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio.c new file mode 100644 index 00000000..a9983ced --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio.c @@ -0,0 +1,1173 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) Controller driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "pio.h" + +#ifndef PIO_WPMR_WPKEY_PASSWD +# define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494Fu) +#endif + +/** + * \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller + * + * \par Purpose + * + * The Parallel Input/Output Controller (PIO) manages up to 32 fully + * programmable input/output lines. Each I/O line may be dedicated as a + * general-purpose I/O or be assigned to a function of an embedded peripheral. + * This assures effective optimization of the pins of a product. + * + * @{ + */ + +#ifndef FREQ_SLOW_CLOCK_EXT +/* External slow clock frequency (hz) */ +#define FREQ_SLOW_CLOCK_EXT 32768 +#endif + +/** + * \brief Configure PIO internal pull-up. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be + * configured. + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable) +{ + /* Enable the pull-up(s) if necessary */ + if (ul_pull_up_enable) { + p_pio->PIO_PUER = ul_mask; + } else { + p_pio->PIO_PUDR = ul_mask; + } +} + +/** + * \brief Configure Glitch or Debouncing filter for the specified input(s). + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_cut_off Cuts off frequency for debouncing filter. + */ +void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_cut_off) +{ +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + /* Set Debouncing, 0 bit field no effect */ + p_pio->PIO_IFSCER = ul_mask; +#elif (SAM3XA || SAM3U) + /* Set Debouncing, 0 bit field no effect */ + p_pio->PIO_DIFSR = ul_mask; +#else +#error "Unsupported device" +#endif + + /* + * The debouncing filter can filter a pulse of less than 1/2 Period of a + * programmable Divided Slow Clock: + * Tdiv_slclk = ((DIV+1)*2).Tslow_clock + */ + p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT / + (2 * (ul_cut_off))) - 1); +} + +/** + * \brief Set a high output level on all the PIOs defined in ul_mask. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will save the value if they are changed to outputs. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_SODR = ul_mask; +} + +/** + * \brief Set a low output level on all the PIOs defined in ul_mask. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will save the value if they are changed to outputs. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_clear(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_CODR = ul_mask; +} + +/** + * \brief Return 1 if one or more PIOs of the given Pin instance currently have + * a high level; otherwise returns 0. This method returns the actual value that + * is being read on the pin. To return the supposed output value of a pin, use + * pio_get_output_data_status() instead. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * + * \retval 1 at least one PIO currently has a high level. + * \retval 0 all PIOs have a low level. + */ +uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask) +{ + uint32_t ul_reg; + + if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) { + ul_reg = p_pio->PIO_ODSR; + } else { + ul_reg = p_pio->PIO_PDSR; + } + + if ((ul_reg & ul_mask) == 0) { + return 0; + } else { + return 1; + } +} + +/** + * \brief Configure IO of a PIO controller as being controlled by a specific + * peripheral. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask) +{ + uint32_t ul_sr; + + /* Disable interrupts on the pin(s) */ + p_pio->PIO_IDR = ul_mask; + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + switch (ul_type) { + case PIO_PERIPH_A: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr); + break; + case PIO_PERIPH_B: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr); + break; +#if (!SAMG) + case PIO_PERIPH_C: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr); + break; + case PIO_PERIPH_D: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr); + break; +#endif + /* Other types are invalid in this function */ + case PIO_INPUT: + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + case PIO_NOT_A_PIN: + return; + } +#elif (SAM3XA|| SAM3U) + switch (ul_type) { + case PIO_PERIPH_A: + ul_sr = p_pio->PIO_ABSR; + p_pio->PIO_ABSR &= (~ul_mask & ul_sr); + break; + + case PIO_PERIPH_B: + ul_sr = p_pio->PIO_ABSR; + p_pio->PIO_ABSR = (ul_mask | ul_sr); + break; + + // other types are invalid in this function + case PIO_INPUT: + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + case PIO_NOT_A_PIN: + return; + } +#else +#error "Unsupported device" +#endif + + /* Remove the pins from under the control of PIO */ + p_pio->PIO_PDR = ul_mask; +} + +/** + * \brief Configure one or more pin(s) or a PIO controller as inputs. + * Optionally, the corresponding internal pull-up(s) and glitch filter(s) can + * be enabled. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask indicating which pin(s) to configure as input(s). + * \param ul_attribute PIO attribute(s). + */ +void pio_set_input(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attribute) +{ + pio_disable_interrupt(p_pio, ul_mask); + pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP); + + /* Enable Input Filter if necessary */ + if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) { + p_pio->PIO_IFER = ul_mask; + } else { + p_pio->PIO_IFDR = ul_mask; + } + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + /* Enable de-glitch or de-bounce if necessary */ + if (ul_attribute & PIO_DEGLITCH) { + p_pio->PIO_IFSCDR = ul_mask; + } else { + if (ul_attribute & PIO_DEBOUNCE) { + p_pio->PIO_IFSCER = ul_mask; + } + } +#elif (SAM3XA|| SAM3U) + /* Enable de-glitch or de-bounce if necessary */ + if (ul_attribute & PIO_DEGLITCH) { + p_pio->PIO_SCIFSR = ul_mask; + } else { + if (ul_attribute & PIO_DEBOUNCE) { + p_pio->PIO_DIFSR = ul_mask; + } + } +#else +#error "Unsupported device" +#endif + + /* Configure pin as input */ + p_pio->PIO_ODR = ul_mask; + p_pio->PIO_PER = ul_mask; +} + +/** + * \brief Configure one or more pin(s) of a PIO controller as outputs, with + * the given default value. Optionally, the multi-drive feature can be enabled + * on the pin(s). + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask indicating which pin(s) to configure. + * \param ul_default_level Default level on the pin(s). + * \param ul_multidrive_enable Indicates if the pin(s) shall be configured as + * open-drain. + * \param ul_pull_up_enable Indicates if the pin shall have its pull-up + * activated. + */ +void pio_set_output(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_default_level, + const uint32_t ul_multidrive_enable, + const uint32_t ul_pull_up_enable) +{ + pio_disable_interrupt(p_pio, ul_mask); + pio_pull_up(p_pio, ul_mask, ul_pull_up_enable); + + /* Enable multi-drive if necessary */ + if (ul_multidrive_enable) { + p_pio->PIO_MDER = ul_mask; + } else { + p_pio->PIO_MDDR = ul_mask; + } + + /* Set default value */ + if (ul_default_level) { + p_pio->PIO_SODR = ul_mask; + } else { + p_pio->PIO_CODR = ul_mask; + } + + /* Configure pin(s) as output(s) */ + p_pio->PIO_OER = ul_mask; + p_pio->PIO_PER = ul_mask; +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_attribute Pins attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask, const uint32_t ul_attribute) +{ + /* Configure pins */ + switch (ul_type) { + case PIO_PERIPH_A: + case PIO_PERIPH_B: +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + case PIO_PERIPH_C: + case PIO_PERIPH_D: +#endif + pio_set_peripheral(p_pio, ul_type, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP)); + break; + + case PIO_INPUT: + pio_set_input(p_pio, ul_mask, ul_attribute); + break; + + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1), + (ul_attribute & PIO_OPENDRAIN) ? 1 : 0, + (ul_attribute & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Return 1 if one or more PIOs of the given Pin are configured to + * output a high level (even if they are not output). + * To get the actual value of the pin, use PIO_Get() instead. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s). + * + * \retval 1 At least one PIO is configured to output a high level. + * \retval 0 All PIOs are configured to output a low level. + */ +uint32_t pio_get_output_data_status(const Pio *p_pio, + const uint32_t ul_mask) +{ + if ((p_pio->PIO_ODSR & ul_mask) == 0) { + return 0; + } else { + return 1; + } +} + +/** + * \brief Configure PIO pin multi-driver. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be + * configured. + */ +void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_multi_driver_enable) +{ + /* Enable the multi-driver if necessary */ + if (ul_multi_driver_enable) { + p_pio->PIO_MDER = ul_mask; + } else { + p_pio->PIO_MDDR = ul_mask; + } +} + +/** + * \brief Get multi-driver status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The multi-driver mask value. + */ +uint32_t pio_get_multi_driver_status(const Pio *p_pio) +{ + return p_pio->PIO_MDSR; +} + + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Configure PIO pin internal pull-down. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall + * be configured. + */ +void pio_pull_down(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_down_enable) +{ + /* Enable the pull-down if necessary */ + if (ul_pull_down_enable) { + p_pio->PIO_PPDER = ul_mask; + } else { + p_pio->PIO_PPDDR = ul_mask; + } +} +#endif + +/** + * \brief Enable PIO output write for synchronous data output. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_OWER = ul_mask; +} + +/** + * \brief Disable PIO output write. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_OWDR = ul_mask; +} + +/** + * \brief Read PIO output write status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The output write mask value. + */ +uint32_t pio_get_output_write_status(const Pio *p_pio) +{ + return p_pio->PIO_OWSR; +} + +/** + * \brief Synchronously write on output pins. + * \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are + * written. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_ODSR = ul_mask; +} + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is + * active. + * Disabling the Schmitt Trigger is requested when using the QTouch Library. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_SCHMITT = ul_mask; +} + +/** + * \brief Get PIO pin schmitt trigger status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The schmitt trigger mask value. + */ +uint32_t pio_get_schmitt_trigger(const Pio *p_pio) +{ + return p_pio->PIO_SCHMITT; +} +#endif + +/** + * \brief Configure the given interrupt source. + * Interrupt can be configured to trigger on rising edge, falling edge, + * high level, low level or simply on level change. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt source bit map. + * \param ul_attr Interrupt source attributes. + */ +void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attr) +{ + /* Configure additional interrupt mode registers. */ + if (ul_attr & PIO_IT_AIME) { + /* Enable additional interrupt mode. */ + p_pio->PIO_AIMER = ul_mask; + + /* If bit field of the selected pin is 1, set as + Rising Edge/High level detection event. */ + if (ul_attr & PIO_IT_RE_OR_HL) { + /* Rising Edge or High Level */ + p_pio->PIO_REHLSR = ul_mask; + } else { + /* Falling Edge or Low Level */ + p_pio->PIO_FELLSR = ul_mask; + } + + /* If bit field of the selected pin is 1, set as + edge detection source. */ + if (ul_attr & PIO_IT_EDGE) { + /* Edge select */ + p_pio->PIO_ESR = ul_mask; + } else { + /* Level select */ + p_pio->PIO_LSR = ul_mask; + } + } else { + /* Disable additional interrupt mode. */ + p_pio->PIO_AIMDR = ul_mask; + } +} + +/** + * \brief Enable the given interrupt source. + * The PIO must be configured as an NVIC interrupt source as well. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_IER = ul_mask; +} + +/** + * \brief Disable a given interrupt source, with no added side effects. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_IDR = ul_mask; +} + +/** + * \brief Read and clear PIO interrupt status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt status value. + */ +uint32_t pio_get_interrupt_status(const Pio *p_pio) +{ + return p_pio->PIO_ISR; +} + +/** + * \brief Read PIO interrupt mask. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt mask value. + */ +uint32_t pio_get_interrupt_mask(const Pio *p_pio) +{ + return p_pio->PIO_IMR; +} + +/** + * \brief Set additional interrupt mode. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + * \param ul_attribute Pin(s) attributes. + */ +void pio_set_additional_interrupt_mode(Pio *p_pio, + const uint32_t ul_mask, const uint32_t ul_attribute) +{ + /* Enables additional interrupt mode if needed */ + if (ul_attribute & PIO_IT_AIME) { + /* Enables additional interrupt mode */ + p_pio->PIO_AIMER = ul_mask; + + /* Configures the Polarity of the event detection */ + /* (Rising/Falling Edge or High/Low Level) */ + if (ul_attribute & PIO_IT_RE_OR_HL) { + /* Rising Edge or High Level */ + p_pio->PIO_REHLSR = ul_mask; + } else { + /* Falling Edge or Low Level */ + p_pio->PIO_FELLSR = ul_mask; + } + + /* Configures the type of event detection (Edge or Level) */ + if (ul_attribute & PIO_IT_EDGE) { + /* Edge select */ + p_pio->PIO_ESR = ul_mask; + } else { + /* Level select */ + p_pio->PIO_LSR = ul_mask; + } + } else { + /* Disable additional interrupt mode */ + p_pio->PIO_AIMDR = ul_mask; + } +} + +#ifndef PIO_WPMR_WPKEY_PASSWD +#define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494FU) +#endif + +/** + * \brief Enable or disable write protect of PIO registers. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_enable 1 to enable, 0 to disable. + */ +void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable) +{ + p_pio->PIO_WPMR = PIO_WPMR_WPKEY_PASSWD | (ul_enable & PIO_WPMR_WPEN); +} + +/** + * \brief Read write protect status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return Return write protect status. + */ +uint32_t pio_get_writeprotect_status(const Pio *p_pio) +{ + return p_pio->PIO_WPSR; +} + +/** + * \brief Return the value of a pin. + * + * \param ul_pin The pin number. + * + * \return The pin value. + * + * \note If pin is output: a pull-up or pull-down could hide the actual value. + * The function \ref pio_get can be called to get the actual pin output + * level. + * \note If pin is input: PIOx must be clocked to sample the signal. + * See PMC driver. + */ +uint32_t pio_get_pin_value(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1; +} + +/** + * \brief Drive a GPIO pin to 1. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called beforehand. + */ +void pio_set_pin_high(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = 1 << (ul_pin & 0x1F); +} + +/** + * \brief Drive a GPIO pin to 0. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called before. + */ +void pio_set_pin_low(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = 1 << (ul_pin & 0x1F); +} + +/** + * \brief Toggle a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called before. + */ +void pio_toggle_pin(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) { + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = 1 << (ul_pin & 0x1F); + } else { + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = 1 << (ul_pin & 0x1F); + } +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param ul_pin The pin index. + * \param ul_flags Pins attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + /* Configure pins */ + switch (ul_flags & PIO_TYPE_Msk) { + case PIO_TYPE_PIO_PERIPH_A: + pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_B: + pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + case PIO_TYPE_PIO_PERIPH_C: + pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_D: + pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags); + break; + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, (1 << (ul_pin & 0x1F)), + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, + (ul_flags & PIO_OPENDRAIN) ? 1 : 0, + (ul_flags & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Drive a GPIO port to 1. + * + * \param p_pio Base address of the PIO port. + * \param ul_mask Bitmask of one or more pin(s) to toggle. + */ +void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask) +{ + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = ul_mask; +} + +/** + * \brief Drive a GPIO port to 0. + * + * \param p_pio Base address of the PIO port. + * \param ul_mask Bitmask of one or more pin(s) to toggle. + */ +void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask) +{ + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = ul_mask; +} + +/** + * \brief Toggle a GPIO group. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask) +{ + if (p_pio->PIO_ODSR & ul_mask) { + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = ul_mask; + } else { + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = ul_mask; + } +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_flags Pin(s) attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure_pin_group(Pio *p_pio, + uint32_t ul_mask, const uint32_t ul_flags) +{ + /* Configure pins */ + switch (ul_flags & PIO_TYPE_Msk) { + case PIO_TYPE_PIO_PERIPH_A: + pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_B: + pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + case PIO_TYPE_PIO_PERIPH_C: + pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_D: + pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, ul_mask, ul_flags); + break; + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, ul_mask, + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, + (ul_flags & PIO_OPENDRAIN) ? 1 : 0, + (ul_flags & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Enable interrupt for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref gpio_configure_pin must be called before. + */ +void pio_enable_pin_interrupt(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + p_pio->PIO_IER = 1 << (ul_pin & 0x1F); +} + + +/** + * \brief Disable interrupt for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref gpio_configure_pin must be called before. + */ +void pio_disable_pin_interrupt(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + p_pio->PIO_IDR = 1 << (ul_pin & 0x1F); +} + + +/** + * \brief Return GPIO port for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return Pointer to \ref Pio struct for GPIO port. + */ +Pio *pio_get_pin_group(uint32_t ul_pin) +{ + Pio *p_pio; + +#if (SAM4C || SAM4CP) +# ifdef ID_PIOD + if (ul_pin > PIO_PC9_IDX) { + p_pio = PIOD; + } else if (ul_pin > PIO_PB31_IDX) { +# else + if (ul_pin > PIO_PB31_IDX) { +# endif + p_pio = PIOC; + } else { + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + } +#elif (SAM4CM) + if (ul_pin > PIO_PB21_IDX) { + p_pio = PIOC; + } else { + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + } +#else + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); +#endif + return p_pio; +} + +/** + * \brief Return GPIO port peripheral ID for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return GPIO port peripheral ID. + */ +uint32_t pio_get_pin_group_id(uint32_t ul_pin) +{ + uint32_t ul_id; + +#if (SAM4C || SAM4CP) +# ifdef ID_PIOD + if (ul_pin > PIO_PC9_IDX) { + ul_id = ID_PIOD; + } else if (ul_pin > PIO_PB31_IDX) { +# else + if (ul_pin > PIO_PB31_IDX) { +# endif + ul_id = ID_PIOC; + } else { + ul_id = ID_PIOA + (ul_pin >> 5); + } +#elif (SAM4CM) + if (ul_pin > PIO_PB21_IDX) { + ul_id = ID_PIOC; + } else { + ul_id = ID_PIOA + (ul_pin >> 5); + } +#elif (SAMV70 || SAMV71 || SAME70 || SAMS70) + ul_id = ID_PIOA + (ul_pin >> 5); + + #ifdef ID_PIOD + if (ul_pin >= PIO_PD0_IDX) ul_id = ID_PIOD; + #endif + + #ifdef ID_PIOE + if (ul_pin >= PIO_PE0_IDX) ul_id = ID_PIOE; + #endif +#else + ul_id = ID_PIOA + (ul_pin >> 5); +#endif + return ul_id; +} + + +/** + * \brief Return GPIO port pin mask for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return GPIO port pin mask. + */ +uint32_t pio_get_pin_group_mask(uint32_t ul_pin) +{ + uint32_t ul_mask = 1 << (ul_pin & 0x1F); + return ul_mask; +} + +#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70) +/* Capture mode enable flag */ +uint32_t pio_capture_enable_flag; + +/** + * \brief Configure PIO capture mode. + * \note PIO capture mode will be disabled automatically. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mode Bitmask of one or more modes. + */ +void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode) +{ + ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */ + p_pio->PIO_PCMR = ul_mode; +} + +/** + * \brief Enable PIO capture mode. + * + * \param p_pio Pointer to a PIO instance. + */ +void pio_capture_enable(Pio *p_pio) +{ + p_pio->PIO_PCMR |= PIO_PCMR_PCEN; + pio_capture_enable_flag = true; +} + +/** + * \brief Disable PIO capture mode. + * + * \param p_pio Pointer to a PIO instance. + */ +void pio_capture_disable(Pio *p_pio) +{ + p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN); + pio_capture_enable_flag = false; +} + +/** + * \brief Read from Capture Reception Holding Register. + * \note Data presence should be tested before any read attempt. + * + * \param p_pio Pointer to a PIO instance. + * \param pul_data Pointer to store the data. + * + * \retval 0 Success. + * \retval 1 I/O Failure, Capture data is not ready. + */ +uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data) +{ + /* Check if the data is ready */ + if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) { + return 1; + } + + /* Read data */ + *pul_data = p_pio->PIO_PCRHR; + return 0; +} + +/** + * \brief Enable the given interrupt source of PIO capture. The status + * register of the corresponding PIO capture controller is cleared prior + * to enabling the interrupt. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_PCISR; + p_pio->PIO_PCIER = ul_mask; +} + +/** + * \brief Disable a given interrupt source of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_PCIDR = ul_mask; +} + +/** + * \brief Read PIO interrupt status of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt status mask value. + */ +uint32_t pio_capture_get_interrupt_status(const Pio *p_pio) +{ + return p_pio->PIO_PCISR; +} + +/** + * \brief Read PIO interrupt mask of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt mask value. + */ +uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio) +{ + return p_pio->PIO_PCIMR; +} +#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Get PDC registers base address. + * + * \param p_pio Pointer to an PIO peripheral. + * + * \return PIOA PDC register base address. + */ +Pdc *pio_capture_get_pdc_base(const Pio *p_pio) +{ + UNUSED(p_pio); /* Stop warning */ + return PDC_PIOA; +} +#endif +#endif + +#if (SAM4C || SAM4CP || SAM4CM || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Set PIO IO drive. + * + * \param p_pio Pointer to an PIO peripheral. + * \param ul_line Line index (0..31). + * \param mode IO drive mode. + */ +void pio_set_io_drive(Pio *p_pio, uint32_t ul_line, + enum pio_io_drive_mode mode) +{ + p_pio->PIO_DRIVER &= ~(1 << ul_line); + p_pio->PIO_DRIVER |= mode << ul_line; +} +#endif + +//@} + diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio.h new file mode 100644 index 00000000..fedf3f58 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio.h @@ -0,0 +1,367 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) Controller driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef PIO_H_INCLUDED +#define PIO_H_INCLUDED + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Compute PIO register length */ +#define PIO_DELTA ((uint32_t) PIOB - (uint32_t) PIOA) + +/* GPIO Support */ +#define PIO_TYPE_Pos 27 +/* PIO Type Mask */ +#define PIO_TYPE_Msk (0xFu << PIO_TYPE_Pos) +/* The pin is not a function pin. */ +#define PIO_TYPE_NOT_A_PIN (0x0u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral A. */ +#define PIO_TYPE_PIO_PERIPH_A (0x1u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral B. */ +#define PIO_TYPE_PIO_PERIPH_B (0x2u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral C. */ +#define PIO_TYPE_PIO_PERIPH_C (0x3u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral D. */ +#define PIO_TYPE_PIO_PERIPH_D (0x4u << PIO_TYPE_Pos) +/* The pin is an input. */ +#define PIO_TYPE_PIO_INPUT (0x5u << PIO_TYPE_Pos) +/* The pin is an output and has a default level of 0. */ +#define PIO_TYPE_PIO_OUTPUT_0 (0x6u << PIO_TYPE_Pos) +/* The pin is an output and has a default level of 1. */ +#define PIO_TYPE_PIO_OUTPUT_1 (0x7u << PIO_TYPE_Pos) + +typedef enum _pio_type { + PIO_NOT_A_PIN = PIO_TYPE_NOT_A_PIN, + PIO_PERIPH_A = PIO_TYPE_PIO_PERIPH_A, + PIO_PERIPH_B = PIO_TYPE_PIO_PERIPH_B, +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + PIO_PERIPH_C = PIO_TYPE_PIO_PERIPH_C, + PIO_PERIPH_D = PIO_TYPE_PIO_PERIPH_D, +#endif + PIO_INPUT = PIO_TYPE_PIO_INPUT, + PIO_OUTPUT_0 = PIO_TYPE_PIO_OUTPUT_0, + PIO_OUTPUT_1 = PIO_TYPE_PIO_OUTPUT_1 +} pio_type_t; + +/* Default pin configuration (no attribute). */ +#define PIO_DEFAULT (0u << 0) +/* The internal pin pull-up is active. */ +#define PIO_PULLUP (1u << 0) +/* The internal glitch filter is active. */ +#define PIO_DEGLITCH (1u << 1) +/* The pin is open-drain. */ +#define PIO_OPENDRAIN (1u << 2) + +/* The internal debouncing filter is active. */ +#define PIO_DEBOUNCE (1u << 3) + +/* Enable additional interrupt modes. */ +#define PIO_IT_AIME (1u << 4) + +/* Interrupt High Level/Rising Edge detection is active. */ +#define PIO_IT_RE_OR_HL (1u << 5) +/* Interrupt Edge detection is active. */ +#define PIO_IT_EDGE (1u << 6) + +/* Low level interrupt is active */ +#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) +/* High level interrupt is active */ +#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) +/* Falling edge interrupt is active */ +#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) +/* Rising edge interrupt is active */ +#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) + +/* + * The #attribute# field is a bitmask that can either be set to PIO_DEFAULT, + * or combine (using bitwise OR '|') any number of the following constants: + * - PIO_PULLUP + * - PIO_DEGLITCH + * - PIO_DEBOUNCE + * - PIO_OPENDRAIN + * - PIO_IT_LOW_LEVEL + * - PIO_IT_HIGH_LEVEL + * - PIO_IT_FALL_EDGE + * - PIO_IT_RISE_EDGE + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable); +void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_cut_off); +void pio_set(Pio *p_pio, const uint32_t ul_mask); +void pio_clear(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask); +void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask); +void pio_set_input(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attribute); +void pio_set_output(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_default_level, + const uint32_t ul_multidrive_enable, + const uint32_t ul_pull_up_enable); +uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask, const uint32_t ul_attribute); +uint32_t pio_get_output_data_status(const Pio *p_pio, + const uint32_t ul_mask); +void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_multi_driver_enable); +uint32_t pio_get_multi_driver_status(const Pio *p_pio); + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_pull_down(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_down_enable); +#endif + +void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask); +void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_output_write_status(const Pio *p_pio); +void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask); + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_schmitt_trigger(const Pio *p_pio); +#endif + +void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attr); +void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask); +void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_interrupt_status(const Pio *p_pio); +uint32_t pio_get_interrupt_mask(const Pio *p_pio); +void pio_set_additional_interrupt_mode(Pio *p_pio, + const uint32_t ul_mask, const uint32_t ul_attribute); +void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable); +uint32_t pio_get_writeprotect_status(const Pio *p_pio); + +#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode); +void pio_capture_enable(Pio *p_pio); +void pio_capture_disable(Pio *p_pio); +uint32_t pio_capture_read(const Pio *p_pio, uint32_t * pul_data); +void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask); +void pio_capture_disable_interrupt(Pio * p_pio, const uint32_t ul_mask); +uint32_t pio_capture_get_interrupt_status(const Pio *p_pio); +uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio); +#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) +Pdc *pio_capture_get_pdc_base(const Pio *p_pio); +#endif +#endif + +/* GPIO Support */ +uint32_t pio_get_pin_value(uint32_t pin); +void pio_set_pin_high(uint32_t pin); +void pio_set_pin_low(uint32_t pin); +void pio_toggle_pin(uint32_t pin); +void pio_enable_pin_interrupt(uint32_t pin); +void pio_disable_pin_interrupt(uint32_t pin); +Pio *pio_get_pin_group(uint32_t pin); +uint32_t pio_get_pin_group_id(uint32_t pin); +uint32_t pio_get_pin_group_mask(uint32_t pin); +uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags); +void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask); +void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask); +void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask); +uint32_t pio_configure_pin_group(Pio *p_pio, uint32_t ul_mask, + const uint32_t ul_flags); + +#if (SAM4C || SAM4CP || SAM4CM || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +enum pio_io_drive_mode { + PIO_IO_DRIVE_LOW = 0, + PIO_IO_DRIVE_HIGH, +}; +void pio_set_io_drive(Pio *p_pio, uint32_t ul_line, + enum pio_io_drive_mode mode); +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_keypad_enable(Pio *p_pio); +void pio_keypad_disable(Pio *p_pio); +void pio_keypad_set_row_num(Pio *p_pio, uint8_t num); +uint8_t pio_keypad_get_row_num(const Pio *p_pio); +void pio_keypad_set_column_num(Pio *p_pio, uint8_t num); +uint8_t pio_keypad_get_column_num(const Pio *p_pio); +void pio_keypad_set_debouncing_value(Pio *p_pio, uint16_t value); +uint16_t pio_keypad_get_debouncing_value(const Pio *p_pio); +void pio_keypad_enable_interrupt(Pio *p_pio, uint32_t ul_mask); +void pio_keypad_disable_interrupt(Pio *p_pio, uint32_t ul_mask); +uint32_t pio_keypad_get_interrupt_mask(const Pio *p_pio); +uint32_t pio_keypad_get_press_status(const Pio *p_pio); +uint32_t pio_keypad_get_release_status(const Pio *p_pio); +uint8_t pio_keypad_get_simult_press_num(const Pio *p_pio); +uint8_t pio_keypad_get_simult_release_num(const Pio *p_pio); +uint8_t pio_keypad_get_press_row_index(const Pio *p_pio, uint8_t queue); +uint8_t pio_keypad_get_press_column_index(const Pio *p_pio, uint8_t queue); +uint8_t pio_keypad_get_release_row_index(const Pio *p_pio, uint8_t queue); +uint8_t pio_keypad_get_release_column_index(const Pio *p_pio, uint8_t queue); +#endif +/** + * \page sam_pio_quickstart Quick Start Guide for the SAM PIO driver + * + * This is the quick start guide for the \ref sam_drivers_pio_group "PIO Driver", + * with step-by-step instructions on how to configure and use the driver for + * specific use cases. + * + * The section described below can be compiled into e.g. the main application + * loop or any other function that will need to interface with the IO port. + * + * \section sam_pio_usecases PIO use cases + * - \ref sam_pio_quickstart_basic + * - \ref sam_pio_quickstart_use_case_2 + * + * \section sam_pio_quickstart_basic Basic usage of the PIO driver + * This section will present a basic use case for the PIO driver. This use case + * will configure pin 23 on port A as output and pin 16 as an input with pullup, + * and then toggle the output pin's value to match that of the input pin. + * + * \subsection sam_pio_quickstart_use_case_1_prereq Prerequisites + * - \ref group_pmc "Power Management Controller driver" + * + * \subsection sam_pio_quickstart_use_case_1_setup_steps Initialization code + * Add to the application initialization code: + * \code + pmc_enable_periph_clk(ID_PIOA); + + pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); + pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); +\endcode + * + * \subsection sam_pio_quickstart_use_case_1_setup_steps_workflow Workflow + * -# Enable the module clock to the PIOA peripheral: + * \code pmc_enable_periph_clk(ID_PIOA); \endcode + * -# Set pin 23 direction on PIOA as output, default low level: + * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode + * -# Set pin 16 direction on PIOA as input, with pullup: + * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode + * + * \subsection sam_pio_quickstart_use_case_1_example_code Example code + * Set the state of output pin 23 to match input pin 16: + * \code + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); +\endcode + * + * \subsection sam_pio_quickstart_use_case_1_example_workflow Workflow + * -# We check the value of the pin: + * \code + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) +\endcode + * -# Then we set the new output value based on the read pin value: + * \code + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); +\endcode + */ + +/** + * \page sam_pio_quickstart_use_case_2 Advanced use case - Interrupt driven edge detection + * + * \section sam_pio_quickstart_use_case_2 Advanced Use Case 1 + * This section will present a more advanced use case for the PIO driver. This use case + * will configure pin 23 on port A as output and pin 16 as an input with pullup, + * and then toggle the output pin's value to match that of the input pin using the interrupt + * controller within the device. + * + * \subsection sam_pio_quickstart_use_case_2_prereq Prerequisites + * - \ref group_pmc "Power Management Controller driver" + * + * \subsection sam_pio_quickstart_use_case_2_setup_steps Initialization code + * Add to the application initialization code: + * \code + pmc_enable_periph_clk(ID_PIOA); + + pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); + pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); + + pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); + pio_enable_interrupt(PIOA, PIO_PA16); + + NVIC_EnableIRQ(PIOA_IRQn); +\endcode + * + * \subsection sam_pio_quickstart_use_case_2_setup_steps_workflow Workflow + * -# Enable the module clock to the PIOA peripheral: + * \code pmc_enable_periph_clk(ID_PIOA); \endcode + * -# Set pin 23 direction on PIOA as output, default low level: + * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode + * -# Set pin 16 direction on PIOA as input, with pullup: + * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode + * -# Configure the input pin 16 interrupt mode and handler: + * \code pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); \endcode + * -# Enable the interrupt for the configured input pin: + * \code pio_enable_interrupt(PIOA, PIO_PA16); \endcode + * -# Enable interrupt handling from the PIOA module: + * \code NVIC_EnableIRQ(PIOA_IRQn); \endcode + * + * \subsection sam_pio_quickstart_use_case_2_example_code Example code + * Add the following function to your application: + * \code + void pin_edge_handler(const uint32_t id, const uint32_t index) + { + if ((id == ID_PIOA) && (index == PIO_PA16)){ + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); + } + } +\endcode + * + * \subsection sam_pio_quickstart_use_case_2_example_workflow Workflow + * -# We check the value of the pin: + * \code + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) +\endcode + * -# Then we set the new output value based on the read pin value: + * \code + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); +\endcode + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PIO_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio_handler.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio_handler.c new file mode 100644 index 00000000..ac40cfdb --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio_handler.c @@ -0,0 +1,286 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) interrupt handler for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "pio.h" +#include "pio_handler.h" + +/** + * Maximum number of interrupt sources that can be defined. This + * constant can be increased, but the current value is the smallest possible one + * that will be compatible with all existing projects. + */ +#define MAX_INTERRUPT_SOURCES 7 + +/** + * Describes a PIO interrupt source, including the PIO instance triggering the + * interrupt and the associated interrupt handler. + */ +struct s_interrupt_source { + uint32_t id; + uint32_t mask; + uint32_t attr; + + /* Interrupt handler. */ + void (*handler) (const uint32_t, const uint32_t); +}; + + +/* List of interrupt sources. */ +static struct s_interrupt_source gs_interrupt_sources[MAX_INTERRUPT_SOURCES]; + +/* Number of currently defined interrupt sources. */ +static uint32_t gs_ul_nb_sources = 0; + +#if (SAM3S || SAM4S || SAM4E) +/* PIO Capture handler */ +static void (*pio_capture_handler)(Pio *) = NULL; +extern uint32_t pio_capture_enable_flag; +#endif + +/** + * \brief Process an interrupt request on the given PIO controller. + * + * \param p_pio PIO controller base address. + * \param ul_id PIO controller ID. + */ +void pio_handler_process(Pio *p_pio, uint32_t ul_id) +{ + uint32_t status; + uint32_t i; + + /* Read PIO controller status */ + status = pio_get_interrupt_status(p_pio); + status &= pio_get_interrupt_mask(p_pio); + + /* Check pending events */ + if (status != 0) { + /* Find triggering source */ + i = 0; + while (status != 0) { + /* Source is configured on the same controller */ + if (gs_interrupt_sources[i].id == ul_id) { + /* Source has PIOs whose statuses have changed */ + if ((status & gs_interrupt_sources[i].mask) != 0) { + gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id, + gs_interrupt_sources[i].mask); + status &= ~(gs_interrupt_sources[i].mask); + } + } + i++; + if (i >= MAX_INTERRUPT_SOURCES) { + break; + } + } + } + + /* Check capture events */ +#if (SAM3S || SAM4S || SAM4E) + if (pio_capture_enable_flag) { + if (pio_capture_handler) { + pio_capture_handler(p_pio); + } + } +#endif +} + +/** + * \brief Set an interrupt handler for the provided pins. + * The provided handler will be called with the triggering pin as its parameter + * as soon as an interrupt is detected. + * + * \param p_pio PIO controller base address. + * \param ul_id PIO ID. + * \param ul_mask Pins (bit mask) to configure. + * \param ul_attr Pins attribute to configure. + * \param p_handler Interrupt handler function pointer. + * + * \return 0 if successful, 1 if the maximum number of sources has been defined. + */ +uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, + uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t)) +{ + uint8_t i; + struct s_interrupt_source *pSource; + + if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES) + return 1; + + /* Check interrupt for this pin, if already defined, redefine it. */ + for (i = 0; i <= gs_ul_nb_sources; i++) { + pSource = &(gs_interrupt_sources[i]); + if (pSource->id == ul_id && pSource->mask == ul_mask) { + break; + } + } + + /* Define new source */ + pSource->id = ul_id; + pSource->mask = ul_mask; + pSource->attr = ul_attr; + pSource->handler = p_handler; + if (i == gs_ul_nb_sources + 1) { + gs_ul_nb_sources++; + } + + /* Configure interrupt mode */ + pio_configure_interrupt(p_pio, ul_mask, ul_attr); + + return 0; +} + +#if (SAM3S || SAM4S || SAM4E) +/** + * \brief Set a capture interrupt handler for all PIO. + * + * The handler will be called with the triggering PIO as its parameter + * as soon as an interrupt is detected. + * + * \param p_handler Interrupt handler function pointer. + * + */ +void pio_capture_handler_set(void (*p_handler)(Pio *)) +{ + pio_capture_handler = p_handler; +} +#endif + +#ifdef ID_PIOA +/** + * \brief Set an interrupt handler for the specified pin. + * The provided handler will be called with the triggering pin as its parameter + * as soon as an interrupt is detected. + * + * \param ul_pin Pin index to configure. + * \param ul_flag Pin flag. + * \param p_handler Interrupt handler function pointer. + * + * \return 0 if successful, 1 if the maximum number of sources has been defined. + */ +uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, + void (*p_handler) (uint32_t, uint32_t)) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + uint32_t group_id = pio_get_pin_group_id(ul_pin); + uint32_t group_mask = pio_get_pin_group_mask(ul_pin); + + return pio_handler_set(p_pio, group_id, group_mask, ul_flag, p_handler); +} + +/** + * \brief Parallel IO Controller A interrupt handler. + * Redefined PIOA interrupt handler for NVIC interrupt table. + */ +void PIOA_Handler(void) +{ + pio_handler_process(PIOA, ID_PIOA); +} +#endif + +#ifdef ID_PIOB +/** + * \brief Parallel IO Controller B interrupt handler + * Redefined PIOB interrupt handler for NVIC interrupt table. + */ +void PIOB_Handler(void) +{ + pio_handler_process(PIOB, ID_PIOB); +} +#endif + +#ifdef ID_PIOC +/** + * \brief Parallel IO Controller C interrupt handler. + * Redefined PIOC interrupt handler for NVIC interrupt table. + */ +void PIOC_Handler(void) +{ + pio_handler_process(PIOC, ID_PIOC); +} +#endif + +#ifdef ID_PIOD +/** + * \brief Parallel IO Controller D interrupt handler. + * Redefined PIOD interrupt handler for NVIC interrupt table. + */ +void PIOD_Handler(void) +{ + pio_handler_process(PIOD, ID_PIOD); +} +#endif + +#ifdef ID_PIOE +/** + * \brief Parallel IO Controller E interrupt handler. + * Redefined PIOE interrupt handler for NVIC interrupt table. + */ +void PIOE_Handler(void) +{ + pio_handler_process(PIOE, ID_PIOE); +} +#endif + +#ifdef ID_PIOF +/** + * \brief Parallel IO Controller F interrupt handler. + * Redefined PIOF interrupt handler for NVIC interrupt table. + */ +void PIOF_Handler(void) +{ + pio_handler_process(PIOF, ID_PIOF); +} +#endif + +/** + * \brief Initialize PIO interrupt management logic. + * + * \param p_pio PIO controller base address. + * \param ul_irqn NVIC line number. + * \param ul_priority PIO controller interrupts priority. + */ +void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority) +{ + uint32_t bitmask = 0; + + bitmask = pio_get_interrupt_mask(p_pio); + pio_disable_interrupt(p_pio, 0xFFFFFFFF); + pio_get_interrupt_status(p_pio); + NVIC_DisableIRQ(ul_irqn); + NVIC_ClearPendingIRQ(ul_irqn); + NVIC_SetPriority(ul_irqn, ul_priority); + NVIC_EnableIRQ(ul_irqn); + pio_enable_interrupt(p_pio, bitmask); +} diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio_handler.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio_handler.h new file mode 100644 index 00000000..36518900 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pio/pio_handler.h @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) interrupt handler for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef PIO_HANDLER_H_INCLUDED +#define PIO_HANDLER_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void pio_handler_process(Pio *p_pio, uint32_t ul_id); +void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority); +uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, + uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t)); +uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, + void (*p_handler) (uint32_t, uint32_t)); + +#if (SAM3S || SAM4S || SAM4E) +void pio_capture_handler_set(void (*p_handler)(Pio *)); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PIO_HANDLER_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/pmc.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/pmc.c new file mode 100644 index 00000000..bc78ef5e --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/pmc.c @@ -0,0 +1,1723 @@ +/** + * \file + * + * \brief Power Management Controller (PMC) driver for SAM. + * + * Copyright (c) 2011-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "pmc.h" + +#if (SAM3N) +# define MAX_PERIPH_ID 31 +#elif (SAM3XA) +# define MAX_PERIPH_ID 44 +#elif (SAM3U) +# define MAX_PERIPH_ID 29 +#elif (SAM3S || SAM4S) +# define MAX_PERIPH_ID 34 +#elif (SAM4E) +# define MAX_PERIPH_ID 47 +#elif (SAMV71) +# define MAX_PERIPH_ID 63 +#elif (SAMV70) +# define MAX_PERIPH_ID 63 +#elif (SAME70) +# define MAX_PERIPH_ID 63 +#elif (SAMS70) +# define MAX_PERIPH_ID 63 +#elif (SAM4N) +# define MAX_PERIPH_ID 31 +#elif (SAM4C || SAM4CM || SAM4CP) +# define MAX_PERIPH_ID 43 +#elif (SAMG51) +# define MAX_PERIPH_ID 47 +#elif (SAMG53) +# define MAX_PERIPH_ID 47 +#elif (SAMG54) +# define MAX_PERIPH_ID 47 +#elif (SAMG55) +# define MAX_PERIPH_ID 50 +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_pmc_group Power Management Controller (PMC) + * + * \par Purpose + * + * The Power Management Controller (PMC) optimizes power consumption by + * controlling all system and user peripheral clocks. The PMC enables/disables + * the clock inputs to many of the peripherals and the Cortex-M Processor. + * + * @{ + */ + +/** + * \brief Set the prescaler of the MCK. + * + * \param ul_pres Prescaler value. + */ +void pmc_mck_set_prescaler(uint32_t ul_pres) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); +} + +#if SAMV71 || SAMV70 || SAME70 || SAMS70 +/** + * \brief Set the division of the MCK. + * + * \param ul_div Division value. + */ +void pmc_mck_set_division(uint32_t ul_div) +{ + switch (ul_div) { + case 1: + ul_div = PMC_MCKR_MDIV_EQ_PCK; + break; + case 2: + ul_div = PMC_MCKR_MDIV_PCK_DIV2; + break; + case 3: + ul_div = PMC_MCKR_MDIV_PCK_DIV3; + break; + case 4: + ul_div = PMC_MCKR_MDIV_PCK_DIV4; + break; + default: + ul_div = PMC_MCKR_MDIV_EQ_PCK; + break; + } + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); +} +#endif + +/** + * \brief Set the source of the MCK. + * + * \param ul_source Source selection value. + */ +void pmc_mck_set_source(uint32_t ul_source) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); +} + +/** + * \brief Switch master clock source selection to slow clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_SLOW_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch master clock source selection to main clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_MAIN_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch master clock source selection to PLLA clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_PLLA_CLK; + + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +/** + * \brief Switch master clock source selection to PLLB clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_PLLB_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch master clock source selection to UPLL clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_UPLL_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +/** + * \brief Switch slow clock source selection to external 32k (Xtal or Bypass). + * + * \note Switching SCLK back to 32krc is only possible by shutting down the + * VDDIO power supply. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + */ +void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass) +{ + /* Set Bypass mode if required */ + if (ul_bypass == 1) { + SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD | + SUPC_MR_OSCBYPASS; + } + + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; +} + +/** + * \brief Check if the external 32k Xtal is ready. + * + * \retval 1 External 32k Xtal is ready. + * \retval 0 External 32k Xtal is not ready. + */ +uint32_t pmc_osc_is_ready_32kxtal(void) +{ + return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) + && (PMC->PMC_SR & PMC_SR_OSCSELS)); +} + +/** + * \brief Switch main clock source selection to internal fast RC. + * + * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz). + * + * \retval 0 Success. + * \retval 1 Timeout error. + * \retval 2 Invalid frequency. + */ +void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf) +{ + /* Enable Fast RC oscillator but DO NOT switch to RC now */ + PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN); + + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Change Fast RC oscillator frequency */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | + CKGR_MOR_KEY_PASSWD | ul_moscrcf; + + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Switch to Fast RC */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | + CKGR_MOR_KEY_PASSWD; +} + +/** + * \brief Enable fast RC oscillator. + * + * \param ul_rc Fast RC oscillator(4/8/12Mhz). + */ +void pmc_osc_enable_fastrc(uint32_t ul_rc) +{ + /* Enable Fast RC oscillator but DO NOT switch to RC */ + PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN); + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Change Fast RC oscillator frequency */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | + CKGR_MOR_KEY_PASSWD | ul_rc; + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); +} + +/** + * \brief Disable the internal fast RC. + */ +void pmc_osc_disable_fastrc(void) +{ + /* Disable Fast RC oscillator */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & + ~CKGR_MOR_MOSCRCF_Msk) + | CKGR_MOR_KEY_PASSWD; +} + +/** + * \brief Check if the main fastrc is ready. + * + * \retval 0 Xtal is not ready, otherwise ready. + */ +uint32_t pmc_osc_is_ready_fastrc(void) +{ + return (PMC->PMC_SR & PMC_SR_MOSCRCS); +} + +/** + * \brief Enable main XTAL oscillator. + * + * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks. + */ +void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | + CKGR_MOR_MOSCXTST(ul_xtal_startup_time); + PMC->CKGR_MOR = mor; + /* Wait the main Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); +} + +/** + * \brief Bypass main XTAL. + */ +void pmc_osc_bypass_main_xtal(void) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY; + /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */ + PMC->CKGR_MOR = mor; + /* The MOSCXTS in PMC_SR is automatically set */ +} + +/** + * \brief Disable the main Xtal. + */ +void pmc_osc_disable_main_xtal(void) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor; +} + +/** + * \brief Check if the main crystal is bypassed. + * + * \retval 0 Xtal is bypassed, otherwise not. + */ +uint32_t pmc_osc_is_bypassed_main_xtal(void) +{ + return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY); +} + +/** + * \brief Check if the main crystal is ready. + * + * \note If main crystal is bypassed, it's always ready. + * + * \retval 0 main crystal is not ready, otherwise ready. + */ +uint32_t pmc_osc_is_ready_main_xtal(void) +{ + return (PMC->PMC_SR & PMC_SR_MOSCXTS); +} + +/** + * \brief Switch main clock source selection to external Xtal/Bypass. + * + * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid + * any system crash. + * + * \note If used in Xtal mode, the Xtal is automatically enabled. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, + uint32_t ul_xtal_startup_time) +{ + /* Enable Main Xtal oscillator */ + if (ul_bypass) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | + CKGR_MOR_MOSCSEL; + } else { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | + CKGR_MOR_MOSCXTST(ul_xtal_startup_time); + /* Wait the Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); + + PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; + } +} + +/** + * \brief Disable the external Xtal. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + */ +void pmc_osc_disable_xtal(uint32_t ul_bypass) +{ + /* Disable xtal oscillator */ + if (ul_bypass) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + CKGR_MOR_KEY_PASSWD; + } else { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD; + } +} + +/** + * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one + * of Xtal, bypass or internal RC. + * + * \retval 1 Xtal is ready. + * \retval 0 Xtal is not ready. + */ +uint32_t pmc_osc_is_ready_mainck(void) +{ + return PMC->PMC_SR & PMC_SR_MOSCSELS; +} + +/** + * \brief Select Main Crystal or internal RC as main clock source. + * + * \note This function will not enable/disable RC or Main Crystal. + * + * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal. + */ +void pmc_mainck_osc_select(uint32_t ul_xtal_rc) +{ + uint32_t mor = PMC->CKGR_MOR; + if (ul_xtal_rc) { + mor |= CKGR_MOR_MOSCSEL; + } else { + mor &= ~CKGR_MOR_MOSCSEL; + } + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor; +} + +/** + * \brief Enable PLLA clock. + * + * \param mula PLLA multiplier. + * \param pllacount PLLA counter. + * \param diva Divider. + */ +void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva) +{ + /* first disable the PLL to unlock the lock */ + pmc_disable_pllack(); + +#if (SAM4C || SAM4CM || SAM4CP || SAMG) + PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) | + CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); +#else + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) | + CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); +#endif + while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0); +} + +/** + * \brief Disable PLLA clock. + */ +void pmc_disable_pllack(void) +{ +#if (SAM4C || SAM4CM || SAM4CP || SAMG) + PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0); +#else + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0); +#endif +} + +/** + * \brief Is PLLA locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_pllack(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKA); +} + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +/** + * \brief Enable PLLB clock. + * + * \param mulb PLLB multiplier. + * \param pllbcount PLLB counter. + * \param divb Divider. + */ +void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb) +{ + /* first disable the PLL to unlock the lock */ + pmc_disable_pllbck(); + +#if SAMG55 + PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) | + CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb); +#else + PMC->CKGR_PLLBR = + CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount) + | CKGR_PLLBR_MULB(mulb); +#endif + while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0); +} + +/** + * \brief Disable PLLB clock. + */ +void pmc_disable_pllbck(void) +{ + PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0); +} + +/** + * \brief Is PLLB locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_pllbck(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKB); +} +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable UPLL clock. + */ +void pmc_enable_upll_clock(void) +{ + PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN; + + /* Wait UTMI PLL Lock Status */ + while (!(PMC->PMC_SR & PMC_SR_LOCKU)); +} + +/** + * \brief Disable UPLL clock. + */ +void pmc_disable_upll_clock(void) +{ + PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; +} + +/** + * \brief Is UPLL locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_upll(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKU); +} +#endif + +/** + * \brief Enable the specified peripheral clock. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_enable_periph_clk(uint32_t ul_id) +{ +#if defined(REG_PMC_PCR) && !SAMG55 + uint32_t pcr; + PMC->PMC_PCR = ul_id & 0x7F; + pcr = PMC->PMC_PCR | PMC_PCR_EN | PMC_PCR_CMD; + PMC->PMC_PCR = pcr; + return 0; +#else + if (ul_id > MAX_PERIPH_ID) { + return 1; + } + + if (ul_id < 32) { + if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) { + PMC->PMC_PCER0 = 1 << ul_id; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) { + PMC->PMC_PCER1 = 1 << ul_id; + } +#endif + } + + return 0; +#endif /* defined(REG_PMC_PCR) && !SAMG55 */ +} + +/** + * \brief Disable the specified peripheral clock. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_disable_periph_clk(uint32_t ul_id) +{ +#if defined(REG_PMC_PCR) && !SAMG55 + uint32_t pcr; + PMC->PMC_PCR = ul_id & 0x7F; + pcr = PMC->PMC_PCR | PMC_PCR_CMD; + PMC->PMC_PCR = pcr; + return 0; +#else + if (ul_id > MAX_PERIPH_ID) { + return 1; + } + + if (ul_id < 32) { + if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) { + PMC->PMC_PCDR0 = 1 << ul_id; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) { + PMC->PMC_PCDR1 = 1 << ul_id; + } +#endif + } + return 0; +#endif /* defined(REG_PMC_PCR) && !SAMG55 */ +} + +/** + * \brief Enable all peripheral clocks. + */ +void pmc_enable_all_periph_clk(void) +{ + PMC->PMC_PCER0 = PMC_MASK_STATUS0; + while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0); + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + PMC->PMC_PCER1 = PMC_MASK_STATUS1; + while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1); +#endif + +#if defined(REG_PMC_PCR) && !SAMG55 + for (uint32_t id = 64; id <= 0x7F; id ++) { + pmc_enable_periph_clk(id); + } +#endif +} + +/** + * \brief Disable all peripheral clocks. + */ +void pmc_disable_all_periph_clk(void) +{ + PMC->PMC_PCDR0 = PMC_MASK_STATUS0; + while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0); + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + PMC->PMC_PCDR1 = PMC_MASK_STATUS1; + while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0); +#endif + +#if defined(REG_PMC_PCR) && !SAMG55 + for (uint32_t id = 64; id <= 0x7F; id ++) { + pmc_disable_periph_clk(id); + } +#endif +} + +/** + * \brief Check if the specified peripheral clock is enabled. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Peripheral clock is disabled or unknown. + * \retval 1 Peripheral clock is enabled. + */ +uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id) +{ +#if defined(REG_PMC_PCR) && !SAMG55 + PMC->PMC_PCR = ul_id & 0x7F; + return (PMC->PMC_PCR & PMC_PCR_EN) ? 1 : 0; +#else + if (ul_id > MAX_PERIPH_ID) { + return 0; + } + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + if (ul_id < 32) { +#endif + if ((PMC->PMC_PCSR0 & (1u << ul_id))) { + return 1; + } else { + return 0; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id))) { + return 1; + } else { + return 0; + } + } +#endif +#endif /* defined(REG_PMC_PCR) && !SAMG55 */ +} + +/** + * \brief Set the prescaler for the specified programmable clock. + * + * \param ul_id Peripheral ID. + * \param ul_pres Prescaler value. + */ +void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres) +{ + PMC->PMC_PCK[ul_id] = + (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres; + while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) + && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); +} + +/** + * \brief Set the source oscillator for the specified programmable clock. + * + * \param ul_id Peripheral ID. + * \param ul_source Source selection value. + */ +void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source) +{ + PMC->PMC_PCK[ul_id] = + (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source; + while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) + && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); +} + +/** + * \brief Switch programmable clock source selection to slow clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch programmable clock source selection to main clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch programmable clock source selection to PLLA clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Get Slow clock source configuration. + * + * \retval Crystal Oscillator Select value. + */ +uint32_t pmc_get_slck_config(void) +{ + return (SUPC->SUPC_CR & SUPC_CR_XTALSEL); +} + +/** + * \brief Get Main clock source configuration. + * + * \retval Main Clock Source Oscillator Selection and Main RC Oscillator Frequency Selection values. + */ +uint32_t pmc_get_mainck_config(void) +{ + return (PMC->CKGR_MOR & (CKGR_MOR_MOSCSEL | CKGR_MOR_MOSCRCF_Msk)); +} + +/** + * \brief Get PLLA clock configuration. + * + * \retval PLLA Multiplier and PLLA Front End Divider values. + */ +uint32_t pmc_get_pllack_config(void) +{ + return (PMC->CKGR_PLLAR & (CKGR_PLLAR_DIVA_Msk | CKGR_PLLAR_MULA_Msk)); +} + +/** + * \brief Get UPLLCKDIV configuration. + * + * \retval UPLL Divider by 2 value. + */ +uint32_t pmc_get_upllckdiv_config(void) +{ + return (PMC->PMC_MCKR & PMC_MCKR_UPLLDIV2); +} +#endif + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +/** + * \brief Switch programmable clock source selection to PLLB clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch programmable clock source selection to UPLL clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +/** + * \brief Switch programmable clock source selection to mck. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Enable the specified programmable clock. + * + * \param ul_id Id of the programmable clock. + */ +void pmc_enable_pck(uint32_t ul_id) +{ + PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id; +} + +/** + * \brief Disable the specified programmable clock. + * + * \param ul_id Id of the programmable clock. + */ +void pmc_disable_pck(uint32_t ul_id) +{ + PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id; +} + +/** + * \brief Enable all programmable clocks. + */ +void pmc_enable_all_pck(void) +{ + PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2; +} + +/** + * \brief Disable all programmable clocks. + */ +void pmc_disable_all_pck(void) +{ + PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2; +} + +/** + * \brief Check if the specified programmable clock is enabled. + * + * \param ul_id Id of the programmable clock. + * + * \retval 0 Programmable clock is disabled or unknown. + * \retval 1 Programmable clock is enabled. + */ +uint32_t pmc_is_pck_enabled(uint32_t ul_id) +{ + if (ul_id > 2) { + return 0; + } + + return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id)); +} + +#if (SAM4C || SAM4CM || SAM4CP) +/** + * \brief Enable Coprocessor Clocks. + */ +void pmc_enable_cpck(void) +{ + PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD; +} + +/** + * \brief Disable Coprocessor Clocks. + */ +void pmc_disable_cpck(void) +{ + PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD; +} + +/** + * \brief Check if the Coprocessor Clocks is enabled. + * + * \retval 0 Coprocessor Clocks is disabled. + * \retval 1 Coprocessor Clocks is enabled. + */ +bool pmc_is_cpck_enabled(void) +{ + if(PMC->PMC_SCSR & PMC_SCSR_CPCK) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Enable Coprocessor Bus Master Clocks. + */ +void pmc_enable_cpbmck(void) +{ + PMC->PMC_SCER = PMC_SCER_CPBMCK | PMC_SCER_CPKEY_PASSWD; +} + +/** + * \brief Disable Coprocessor Bus Master Clocks. + */ +void pmc_disable_cpbmck(void) +{ + PMC->PMC_SCDR = PMC_SCDR_CPBMCK | PMC_SCDR_CPKEY_PASSWD; +} + +/** + * \brief Check if the Coprocessor Bus Master Clocks is enabled. + * + * \retval 0 Coprocessor Bus Master Clocks is disabled. + * \retval 1 Coprocessor Bus Master Clocks is enabled. + */ +bool pmc_is_cpbmck_enabled(void) +{ + if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Set the prescaler for the Coprocessor Master Clock. + * + * \param ul_pres Prescaler value. + */ +void pmc_cpck_set_prescaler(uint32_t ul_pres) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres); +} + +/** + * \brief Set the source for the Coprocessor Master Clock. + * + * \param ul_source Source selection value. + */ +void pmc_cpck_set_source(uint32_t ul_source) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source; +} +#endif + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch UDP (USB) clock source selection to PLLA clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); +} +#endif + +#if (SAM3S || SAM4S || SAMG55) +/** + * \brief Switch UDP (USB) clock source selection to PLLB clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; +} +#endif + +#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch UDP (USB) clock source selection to UPLL clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv); +} +#endif + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable UDP (USB) clock. + */ +void pmc_enable_udpck(void) +{ +#if (SAM3S || SAM4S || SAM4E || SAMG55) + PMC->PMC_SCER = PMC_SCER_UDP; +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) + PMC->PMC_SCER = PMC_SCER_USBCLK; +#else + PMC->PMC_SCER = PMC_SCER_UOTGCLK; +# endif +} + +/** + * \brief Disable UDP (USB) clock. + */ +void pmc_disable_udpck(void) +{ +#if (SAM3S || SAM4S || SAM4E || SAMG55) + PMC->PMC_SCDR = PMC_SCDR_UDP; +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) + PMC->PMC_SCDR = PMC_SCDR_USBCLK; +#else + PMC->PMC_SCDR = PMC_SCDR_UOTGCLK; +# endif +} +#endif + +#if SAMG55 +/** + * \brief Switch UHP (USB) clock source selection to PLLA clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); +} + +/** + * \brief Switch UHP (USB) clock source selection to PLLB clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; +} + +/** + * \brief Enable UHP (USB) clock. + */ +void pmc_enable_uhpck(void) +{ + PMC->PMC_SCER = PMC_SCER_UHP; +} +#endif + +/** + * \brief Enable PMC interrupts. + * + * \param ul_sources Interrupt sources bit map. + */ +void pmc_enable_interrupt(uint32_t ul_sources) +{ + PMC->PMC_IER = ul_sources; +} + +/** + * \brief Disable PMC interrupts. + * + * \param ul_sources Interrupt sources bit map. + */ +void pmc_disable_interrupt(uint32_t ul_sources) +{ + PMC->PMC_IDR = ul_sources; +} + +/** + * \brief Get PMC interrupt mask. + * + * \return The interrupt mask value. + */ +uint32_t pmc_get_interrupt_mask(void) +{ + return PMC->PMC_IMR; +} + +/** + * \brief Get current status. + * + * \return The current PMC status. + */ +uint32_t pmc_get_status(void) +{ + return PMC->PMC_SR; +} + +/** + * \brief Set the wake-up inputs for fast startup mode registers + * (event generation). + * + * \param ul_inputs Wake up inputs to enable. + */ +void pmc_set_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_FSMR |= ul_inputs; +} + +/** + * \brief Clear the wake-up inputs for fast startup mode registers + * (remove event generation). + * + * \param ul_inputs Wake up inputs to disable. + */ +void pmc_clr_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_FSMR &= ~ul_inputs; +} + +#if (SAM4C || SAM4CM || SAM4CP) +/** + * \brief Set the wake-up inputs of coprocessor for fast startup mode registers + * (event generation). + * + * \param ul_inputs Wake up inputs to enable. + */ +void pmc_cp_set_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_CPFSMR |= ul_inputs; +} + +/** + * \brief Clear the wake-up inputs of coprocessor for fast startup mode registers + * (remove event generation). + * + * \param ul_inputs Wake up inputs to disable. + */ +void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_CPFSMR &= ~ul_inputs; +} +#endif + +/** + * \brief Enable Sleep Mode. + * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0) + * + * \param uc_type 0 for wait for interrupt, 1 for wait for event. + * \note For SAM4S, SAM4C, SAM4CM, SAM4CP, SAMV71 and SAM4E series, + * since only WFI is effective, uc_type = 1 will be treated as uc_type = 0. + */ +void pmc_enable_sleepmode(uint8_t uc_type) +{ +#if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) + PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode +#endif + SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) + UNUSED(uc_type); + __DSB(); + __WFI(); +#else + if (uc_type == 0) { + __DSB(); + __WFI(); + } else { + __DSB(); + __WFE(); + } +#endif +} + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN; +/** + * \brief Set the embedded flash state in wait mode + * + * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode, + * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode. + */ +void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state) +{ + ul_flash_in_wait_mode = ul_flash_state; +} + +/** + * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + FLPM + * + * \note In this function, FLPM will retain, WAITMODE bit will be set, + * Generally, this function will be called by pmc_sleep() in order to + * complete all sequence entering wait mode. + * See \ref pmc_sleep() for entering different sleep modes. + */ +void pmc_enable_waitmode(void) +{ + uint32_t i; + + /* Flash in wait mode */ + i = PMC->PMC_FSMR; + i &= ~PMC_FSMR_FLPM_Msk; +#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) + i |= ul_flash_in_wait_mode; +#else + (void)ul_flash_in_wait_mode; + i |= PMC_WAIT_MODE_FLASH_IDLE; +#endif + PMC->PMC_FSMR = i; + + /* Set the WAITMODE bit = 1 */ + PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE; + + /* Waiting for Master Clock Ready MCKRDY = 1 */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + + /* Waiting for MOSCRCEN bit cleared is strongly recommended + * to ensure that the core will not execute undesired instructions + */ + for (i = 0; i < 500; i++) { + __NOP(); + } + while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); + +#if (!SAMG) + /* Restore Flash in idle mode */ + i = PMC->PMC_FSMR; + i &= ~PMC_FSMR_FLPM_Msk; + i |= PMC_WAIT_MODE_FLASH_IDLE; + PMC->PMC_FSMR = i; +#endif +} +#else +/** + * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) + + * (LPM bit = 1) + */ +void pmc_enable_waitmode(void) +{ + uint32_t i; + + PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */ + SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */ + + __DSB(); + __WFE(); + + /* Waiting for MOSCRCEN bit cleared is strongly recommended + * to ensure that the core will not execute undesired instructions + */ + for (i = 0; i < 500; i++) { + __NOP(); + } + while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); + +} +#endif + +#if (!(SAMG51 || SAMG53 || SAMG54)) +/** + * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) + + * (SLEEPDEEP bit = 1) + */ +void pmc_enable_backupmode(void) +{ +#if (SAM4C || SAM4CM || SAM4CP) + uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk); + SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD; + while (SUPC->SUPC_SR & SUPC_SR_BUPPORS); +#endif + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG; + uint32_t ul_dummy = SUPC->SUPC_MR; + UNUSED(ul_dummy); + __DSB(); + __WFE(); + __WFI(); +#else + __DSB(); + __WFE(); +#endif +} +#endif + +/** + * \brief Enable Clock Failure Detector. + */ +void pmc_enable_clock_failure_detector(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR; + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg; +} + +/** + * \brief Disable Clock Failure Detector. + */ +void pmc_disable_clock_failure_detector(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN); + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg; +} + +#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable Slow Crystal Oscillator Frequency Monitoring. + */ +void pmc_enable_sclk_osc_freq_monitor(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR; + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg; +} + +/** + * \brief Disable Slow Crystal Oscillator Frequency Monitoring. + */ +void pmc_disable_sclk_osc_freq_monitor(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME); + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg; +} +#endif + +/** + * \brief Enable or disable write protect of PMC registers. + * + * \param ul_enable 1 to enable, 0 to disable. + */ +void pmc_set_writeprotect(uint32_t ul_enable) +{ + if (ul_enable) { + PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN; + } else { + PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD; + } +} + +/** + * \brief Return write protect status. + * + * \return Return write protect status. + */ +uint32_t pmc_get_writeprotect_status(void) +{ + return PMC->PMC_WPSR; +} + +#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable the specified peripheral clock. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Fail. + */ +uint32_t pmc_enable_sleepwalking(uint32_t ul_id) +{ + uint32_t temp; +#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + if ((7 <= ul_id) && (ul_id<= 29)) { +#else + if ((8 <= ul_id) && (ul_id<= 29)) { +#endif + temp = pmc_get_active_status0(); + if (temp & (1 << ul_id)) { + return 1; + } + PMC->PMC_SLPWK_ER0 = 1 << ul_id; + temp = pmc_get_active_status0(); + if (temp & (1 << ul_id)) { + pmc_disable_sleepwalking(ul_id); + return 1; + } + return 0; + } +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) + else if ((32 <= ul_id) && (ul_id<= 60)) { + ul_id -= 32; + temp = pmc_get_active_status1(); + if (temp & (1 << ul_id)) { + return 1; + } + PMC->PMC_SLPWK_ER1 = 1 << ul_id; + temp = pmc_get_active_status1(); + if (temp & (1 << ul_id)) { + pmc_disable_sleepwalking(ul_id); + return 1; + } + return 0; + } +#endif + else { + return 1; + } +} + +/** + * \brief Disable the sleepwalking of specified peripheral. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_disable_sleepwalking(uint32_t ul_id) +{ +#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + if ((7 <= ul_id) && (ul_id<= 29)) { +#else + if ((8 <= ul_id) && (ul_id<= 29)) { +#endif + PMC->PMC_SLPWK_DR0 = 1 << ul_id; + return 0; + } +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) + else if ((32 <= ul_id) && (ul_id<= 60)) { + ul_id -= 32; + PMC->PMC_SLPWK_DR1 = 1 << ul_id; + return 0; + } +#endif + else { + return 1; + } +} + +/** + * \brief Return peripheral sleepwalking enable status. + * + * \return the status register value. + */ +uint32_t pmc_get_sleepwalking_status0(void) +{ + return PMC->PMC_SLPWK_SR0; +} + +/** + * \brief Return peripheral active status. + * + * \return the status register value. + */ +uint32_t pmc_get_active_status0(void) +{ + return PMC->PMC_SLPWK_ASR0; +} + +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Return peripheral sleepwalking enable status. + * + * \return the status register value. + */ +uint32_t pmc_get_sleepwalking_status1(void) +{ + return PMC->PMC_SLPWK_SR1; +} + +/** + * \brief Return peripheral active status. + * + * \return the status register value. + */ +uint32_t pmc_get_active_status1(void) +{ + return PMC->PMC_SLPWK_ASR1; +} +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/pmc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/pmc.h new file mode 100644 index 00000000..4fe59030 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/pmc.h @@ -0,0 +1,546 @@ +/** + * \file + * + * \brief Power Management Controller (PMC) driver for SAM. + * + * Copyright (c) 2011-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef PMC_H_INCLUDED +#define PMC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** Bit mask for peripheral clocks (PCER0) */ +#define PMC_MASK_STATUS0 (0xFFFFFFFC) + +/** Bit mask for peripheral clocks (PCER1) */ +#define PMC_MASK_STATUS1 (0xFFFFFFFF) + +/** Loop counter timeout value */ +#if !(SAME70) +#define PMC_TIMEOUT (2048) +#else +#define PMC_TIMEOUT (4096) +#endif + +/** Key to unlock CKGR_MOR register */ +#ifndef CKGR_MOR_KEY_PASSWD +#define CKGR_MOR_KEY_PASSWD CKGR_MOR_KEY(0x37U) +#endif + +/** Key used to write SUPC registers */ +#ifndef SUPC_CR_KEY_PASSWD +#define SUPC_CR_KEY_PASSWD SUPC_CR_KEY(0xA5U) +#endif + +#ifndef SUPC_MR_KEY_PASSWD +#define SUPC_MR_KEY_PASSWD SUPC_MR_KEY(0xA5U) +#endif + +/** Mask to access fast startup input */ +#define PMC_FAST_STARTUP_Msk (0x7FFFFu) + +/** PMC_WPMR Write Protect KEY, unlock it */ +#ifndef PMC_WPMR_WPKEY_PASSWD +#define PMC_WPMR_WPKEY_PASSWD PMC_WPMR_WPKEY((uint32_t) 0x504D43) +#endif + +/** Using external oscillator */ +#define PMC_OSC_XTAL 0 + +/** Oscillator in bypass mode */ +#define PMC_OSC_BYPASS 1 + +#define PMC_PCK_0 0 /* PCK0 ID */ +#define PMC_PCK_1 1 /* PCK1 ID */ +#define PMC_PCK_2 2 /* PCK2 ID */ +#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +#define PMC_PCK_3 3 /* PCK3 ID */ +#define PMC_PCK_4 4 /* PCK4 ID */ +#define PMC_PCK_5 5 /* PCK5 ID */ +#define PMC_PCK_6 6 /* PCK6 ID */ +#if SAMG55 +#define PMC_PCK_7 7 /* PCK7 ID */ +#endif +#endif + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** Flash state in Wait Mode */ +#define PMC_WAIT_MODE_FLASH_STANDBY PMC_FSMR_FLPM_FLASH_STANDBY +#define PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN +#define PMC_WAIT_MODE_FLASH_IDLE PMC_FSMR_FLPM_FLASH_IDLE +#endif + +/** Convert startup time from us to MOSCXTST */ +#define pmc_us_to_moscxtst(startup_us, slowck_freq) \ + ((startup_us * slowck_freq / 8 / 1000000) < 0x100 ? \ + (startup_us * slowck_freq / 8 / 1000000) : 0xFF) + +/** + * \name Master clock (MCK) Source and Prescaler configuration + * + * \note The following functions may be used to select the clock source and + * prescaler for the master clock. + */ +//@{ + +void pmc_mck_set_prescaler(uint32_t ul_pres); +#if SAMV71 || SAMV70 || SAME70 || SAMS70 +void pmc_mck_set_division(uint32_t ul_div); +#endif +void pmc_mck_set_source(uint32_t ul_source); +uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres); +uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres); +uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres); +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres); +#endif +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres); +#endif +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state); +#endif + + +//@} + +/** + * \name Slow clock (SLCK) oscillator and configuration + * + */ +//@{ + +void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass); +uint32_t pmc_osc_is_ready_32kxtal(void); + +//@} + +/** + * \name Main Clock (MAINCK) oscillator and configuration + * + */ +//@{ + +void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf); +void pmc_osc_enable_fastrc(uint32_t ul_rc); +void pmc_osc_disable_fastrc(void); +uint32_t pmc_osc_is_ready_fastrc(void); +void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time); +void pmc_osc_bypass_main_xtal(void); +void pmc_osc_disable_main_xtal(void); +uint32_t pmc_osc_is_bypassed_main_xtal(void); +uint32_t pmc_osc_is_ready_main_xtal(void); +void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, + uint32_t ul_xtal_startup_time); +void pmc_osc_disable_xtal(uint32_t ul_bypass); +uint32_t pmc_osc_is_ready_mainck(void); +void pmc_mainck_osc_select(uint32_t ul_xtal_rc); + +//@} + +/** + * \name PLL oscillator and configuration + * + */ +//@{ + +void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva); +void pmc_disable_pllack(void); +uint32_t pmc_is_locked_pllack(void); + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb); +void pmc_disable_pllbck(void); +uint32_t pmc_is_locked_pllbck(void); +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_enable_upll_clock(void); +void pmc_disable_upll_clock(void); +uint32_t pmc_is_locked_upll(void); +#endif + +//@} + +/** + * \name Peripherals clock configuration + * + */ +//@{ + +uint32_t pmc_enable_periph_clk(uint32_t ul_id); +uint32_t pmc_disable_periph_clk(uint32_t ul_id); +void pmc_enable_all_periph_clk(void); +void pmc_disable_all_periph_clk(void); +uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id); + +//@} + +/** + * \name Programmable clock Source and Prescaler configuration + * + * The following functions may be used to select the clock source and + * prescaler for the specified programmable clock. + */ +//@{ + +void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres); +void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source); +uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres); +uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres); +uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres); +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t pmc_get_slck_config(void); +uint32_t pmc_get_mainck_config(void); +uint32_t pmc_get_pllack_config(void); +uint32_t pmc_get_upllckdiv_config(void); +#endif +#if (SAM4C || SAM4CM || SAM4CP) +void pmc_enable_cpck(void); +void pmc_disable_cpck(void); +bool pmc_is_cpck_enabled(void); +void pmc_enable_cpbmck(void); +void pmc_disable_cpbmck(void); +bool pmc_is_cpbmck_enabled(void); +void pmc_cpck_set_prescaler(uint32_t ul_pres); +void pmc_cpck_set_source(uint32_t ul_source); +#endif +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres); +#endif +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres); +#endif +uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres); +void pmc_enable_pck(uint32_t ul_id); +void pmc_disable_pck(uint32_t ul_id); +void pmc_enable_all_pck(void); +void pmc_disable_all_pck(void); +uint32_t pmc_is_pck_enabled(uint32_t ul_id); + +//@} + +/** + * \name USB clock configuration + * + */ +//@{ + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv); +#endif +#if (SAM3S || SAM4S || SAMG55) +void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv); +#endif +#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv); +#endif +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_enable_udpck(void); +void pmc_disable_udpck(void); +#endif +#if SAMG55 +void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv); +void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv); +void pmc_enable_uhpck(void); +#endif + +//@} + +/** + * \name Interrupt and status management + * + */ +//@{ + +void pmc_enable_interrupt(uint32_t ul_sources); +void pmc_disable_interrupt(uint32_t ul_sources); +uint32_t pmc_get_interrupt_mask(void); +uint32_t pmc_get_status(void); + +//@} + +/** + * \name Power management + * + * The following functions are used to configure sleep mode and additional + * wake up inputs. + */ +//@{ + +void pmc_set_fast_startup_input(uint32_t ul_inputs); +void pmc_clr_fast_startup_input(uint32_t ul_inputs); +#if (SAM4C || SAM4CM || SAM4CP) +void pmc_cp_set_fast_startup_input(uint32_t ul_inputs); +void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs); +#endif +void pmc_enable_sleepmode(uint8_t uc_type); +void pmc_enable_waitmode(void); +#if (!(SAMG51 || SAMG53 || SAMG54)) +void pmc_enable_backupmode(void); +#endif +//@} + +/** + * \name Failure detector + * + */ +//@{ + +void pmc_enable_clock_failure_detector(void); +void pmc_disable_clock_failure_detector(void); + +//@} + +#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \name Slow Crystal Oscillator Frequency Monitoring + * + */ +//@{ + +void pmc_enable_sclk_osc_freq_monitor(void); +void pmc_disable_sclk_osc_freq_monitor(void); + +//@} +#endif + +/** + * \name Write protection + * + */ +//@{ + +void pmc_set_writeprotect(uint32_t ul_enable); +uint32_t pmc_get_writeprotect_status(void); + +//@} + +#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \name Sleepwalking configuration + * + */ +//@{ + +uint32_t pmc_enable_sleepwalking(uint32_t ul_id); +uint32_t pmc_disable_sleepwalking(uint32_t ul_id); +uint32_t pmc_get_sleepwalking_status0(void); +uint32_t pmc_get_active_status0(void); +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t pmc_get_sleepwalking_status1(void); +uint32_t pmc_get_active_status1(void); +#endif +//@} +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +//! @} + +/** + * \page sam_pmc_quickstart Quick start guide for the SAM PMC module + * + * This is the quick start guide for the \ref sam_drivers_pmc_group "PMC module", + * with step-by-step instructions on how to configure and use the driver in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section pmc_use_cases PMC use cases + * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources + * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks + * + * \section pmc_basic_use_case Basic use case - Switch Main Clock sources + * In this use case, the PMC module is configured for a variety of system clock + * sources and speeds. A LED is used to visually indicate the current clock + * speed as the source is switched. + * + * \section pmc_basic_use_case_setup Setup + * + * \subsection pmc_basic_use_case_setup_prereq Prerequisites + * -# \ref gpio_group "General Purpose I/O Management (gpio)" + * + * \subsection pmc_basic_use_case_setup_code Code + * The following function needs to be added to the user application, to flash a + * board LED a variable number of times at a rate given in CPU ticks. + * + * \code + #define FLASH_TICK_COUNT 0x00012345 + + void flash_led(uint32_t tick_count, uint8_t flash_count) + { + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; + SysTick->LOAD = tick_count; + + while (flash_count--) + { + gpio_toggle_pin(LED0_GPIO); + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); + gpio_toggle_pin(LED0_GPIO); + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); + } + } +\endcode + * + * \section pmc_basic_use_case_usage Use case + * + * \subsection pmc_basic_use_case_usage_code Example code + * Add to application C-file: + * \code + for (;;) + { + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + flash_led(FLASH_TICK_COUNT, 5); + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); + flash_led(FLASH_TICK_COUNT, 5); + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + flash_led(FLASH_TICK_COUNT, 5); + pmc_switch_mainck_to_xtal(0); + flash_led(FLASH_TICK_COUNT, 5); + } +\endcode + * + * \subsection pmc_basic_use_case_usage_flow Workflow + * -# Wrap the code in an infinite loop: + * \code + for (;;) +\endcode + * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * -# Switch the Master CPU frequency to the external crystal oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_xtal(0, BOARD_OSC_STARTUP_US); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * + * \section pmc_use_case_2 Use case #2 - Configure Programmable Clocks + * In this use case, the PMC module is configured to start the Slow Clock from + * an attached 32KHz crystal, and start one of the Programmable Clock modules + * sourced from the Slow Clock divided down with a prescale factor of 64. + * + * \section pmc_use_case_2_setup Setup + * + * \subsection pmc_use_case_2_setup_prereq Prerequisites + * -# \ref pio_group "Parallel Input/Output Controller (pio)" + * + * \subsection pmc_use_case_2_setup_code Code + * The following code must be added to the user application: + * \code + pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); +\endcode + * + * \subsection pmc_use_case_2_setup_code_workflow Workflow + * -# Configure the PCK1 pin to output on a specific port pin (in this case, + * PIOA pin 17) of the microcontroller. + * \code + pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); +\endcode + * \note The peripheral selection and pin will vary according to your selected + * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O + * Lines" of your device's datasheet. + * + * \section pmc_use_case_2_usage Use case + * The generated PCK1 clock output can be viewed on an oscilloscope attached to + * the correct pin of the microcontroller. + * + * \subsection pmc_use_case_2_usage_code Example code + * Add to application C-file: + * \code + pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); + pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); + pmc_enable_pck(PMC_PCK_1); + + for (;;) + { + // Do Nothing + } +\endcode + * + * \subsection pmc_use_case_2_usage_flow Workflow + * -# Switch the Slow Clock source input to an external 32KHz crystal: + * \code + pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); +\endcode + * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock, + * with a prescaler of 64: + * \code + pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); +\endcode + * -# Enable Programmable Clock module PCK1: + * \code + pmc_enable_pck(PMC_PCK_1); +\endcode + * -# Enter an infinite loop: + * \code + for (;;) + { + // Do Nothing + } +\endcode + */ + +#endif /* PMC_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/sleep.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/sleep.c new file mode 100644 index 00000000..33142b62 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/sleep.c @@ -0,0 +1,381 @@ +/** + * \file + * + * \brief Sleep mode access + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include "sleep.h" + +/* SAM3,SAM4,SAMG,SAMV,SAMS and SAME series */ +#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \ + SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAMS70 || SAME70) +# include "pmc.h" +# include "board.h" + +/* Checking board configuration of main clock xtal statup time */ +#if !defined(BOARD_OSC_STARTUP_US) +# warning The board main clock xtal statup time has not been defined. Using default settings. +# define BOARD_OSC_STARTUP_US (15625UL) +#endif + +#if !defined(EFC0) +# define EFC0 EFC +#endif + +/** + * Save clock settings and shutdown PLLs + */ +__always_inline static void pmc_save_clock_settings( + uint32_t *p_osc_setting, + uint32_t *p_pll0_setting, + uint32_t *p_pll1_setting, + uint32_t *p_mck_setting, + uint32_t *p_fmr_setting, +#if defined(EFC1) + uint32_t *p_fmr_setting1, +#endif + const bool disable_xtal) +{ + uint32_t mor = PMC->CKGR_MOR; + uint32_t mckr = PMC->PMC_MCKR; + uint32_t fmr = EFC0->EEFC_FMR; +# if defined(EFC1) + uint32_t fmr1 = EFC1->EEFC_FMR; +# endif + + if (p_osc_setting) { + *p_osc_setting = mor; + } + if (p_pll0_setting) { + *p_pll0_setting = PMC->CKGR_PLLAR; + } + if (p_pll1_setting) { +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + *p_pll1_setting = PMC->CKGR_PLLBR; +#elif (SAM3U || SAM3XA) + *p_pll1_setting = PMC->CKGR_UCKR; +#else + *p_pll1_setting = 0; +#endif + } + if (p_mck_setting) { + *p_mck_setting = mckr; + } + if (p_fmr_setting) { + *p_fmr_setting = fmr; + } +#if defined(EFC1) + if (p_fmr_setting1) { + *p_fmr_setting1 = fmr1; + } +#endif + + /* Enable FAST RC */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor | CKGR_MOR_MOSCRCEN; + /* if MCK source is PLL, switch to mainck */ + if ((mckr & PMC_MCKR_CSS_Msk) > PMC_MCKR_CSS_MAIN_CLK) { + /* MCK -> MAINCK */ + mckr = (mckr & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_MAIN_CLK; + PMC->PMC_MCKR = mckr; + while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + } + /* MCK prescale -> 1 */ + if (mckr & PMC_MCKR_PRES_Msk) { + mckr = (mckr & (~PMC_MCKR_PRES_Msk)); + PMC->PMC_MCKR = mckr; + while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + } + /* Disable PLLs */ + pmc_disable_pllack(); +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + pmc_disable_pllbck(); +#elif (SAM3U || SAM3XA) + pmc_disable_upll_clock(); +#endif + + /* Prepare for entering WAIT mode */ + /* Wait fast RC ready */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Switch mainck to FAST RC */ +#if SAMG + /** + * For the sleepwalking feature, we need an accurate RC clock. Only 24M and + * 16M are trimmed in production. Here we select the 24M. + * And so wait state need to be 1. + */ + EFC0->EEFC_FMR = (fmr & (~EEFC_FMR_FWS_Msk)) | EEFC_FMR_FWS(1); + + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_MOSCRCF_24_MHz | + CKGR_MOR_KEY_PASSWD; +#else + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | + CKGR_MOR_KEY_PASSWD; +#endif + while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)); + +#if (!SAMG) + /* FWS update */ + EFC0->EEFC_FMR = fmr & (~EEFC_FMR_FWS_Msk); +#if defined(EFC1) + EFC1->EEFC_FMR = fmr1 & (~EEFC_FMR_FWS_Msk); +#endif +#endif + + /* Disable XTALs */ + if (disable_xtal) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD; + } +} + +/** + * Restore clock settings + */ +__always_inline static void pmc_restore_clock_setting( + const uint32_t osc_setting, + const uint32_t pll0_setting, + const uint32_t pll1_setting, + const uint32_t mck_setting, + const uint32_t fmr_setting +#if defined(EFC1) + , const uint32_t fmr_setting1 +#endif + ) +{ + uint32_t mckr; + uint32_t pll_sr = 0; + + /* Switch mainck to external xtal */ + if (CKGR_MOR_MOSCXTBY == (osc_setting & CKGR_MOR_MOSCXTBY)) { + /* Bypass mode */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | + CKGR_MOR_MOSCSEL; + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & + ~CKGR_MOR_MOSCRCF_Msk) + | CKGR_MOR_KEY_PASSWD; + } else if (CKGR_MOR_MOSCXTEN == (osc_setting & CKGR_MOR_MOSCXTEN)) { + /* Enable External XTAL */ + if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN)) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN; + /* Wait the Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); + } + /* Select External XTAL */ + if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) { + PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; + while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)); + } + /* Disable Fast RC */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & + ~CKGR_MOR_MOSCRCF_Msk) + | CKGR_MOR_KEY_PASSWD; + } + + if (pll0_setting & CKGR_PLLAR_MULA_Msk) { +#if (SAM4C || SAM4CM || SAMG || SAM4CP) + PMC->CKGR_PLLAR = pll0_setting; +#else + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting; +#endif + pll_sr |= PMC_SR_LOCKA; + } +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + if (pll1_setting & CKGR_PLLBR_MULB_Msk) { + PMC->CKGR_PLLBR = pll1_setting; + pll_sr |= PMC_SR_LOCKB; + } +#elif (SAM3U || SAM3XA) + if (pll1_setting & CKGR_UCKR_UPLLEN) { + PMC->CKGR_UCKR = pll1_setting; + pll_sr |= PMC_SR_LOCKU; + } +#else + UNUSED(pll1_setting); +#endif + /* Wait MCK source ready */ + switch(mck_setting & PMC_MCKR_CSS_Msk) { + case PMC_MCKR_CSS_PLLA_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKA)); + break; +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + case PMC_MCKR_CSS_PLLB_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKB)); + break; +#elif (SAM3U || SAM3XA) + case PMC_MCKR_CSS_UPLL_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKU)); + break; +#endif + } + + /* Switch to faster clock */ + mckr = PMC->PMC_MCKR; + + /* Set PRES */ + PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk) + | (mck_setting & PMC_MCKR_PRES_Msk); + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + + /* Restore flash wait states */ + EFC0->EEFC_FMR = fmr_setting; +#if defined(EFC1) + EFC1->EEFC_FMR = fmr_setting1; +#endif + + /* Set CSS and others */ + PMC->PMC_MCKR = mck_setting; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + + /* Waiting all restored PLLs ready */ + while (!(PMC->PMC_SR & pll_sr)); +} + +/** If clocks are switched for some sleep mode */ +static volatile bool b_is_sleep_clock_used = false; +/** Callback invoked once when clocks are restored */ +static pmc_callback_wakeup_clocks_restored_t callback_clocks_restored = NULL; + +void pmc_sleep(int sleep_mode) +{ + switch (sleep_mode) { + case SAM_PM_SMODE_SLEEP_WFI: + case SAM_PM_SMODE_SLEEP_WFE: +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70) + SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; + cpu_irq_enable(); + __DSB(); + __WFI(); + break; +#else + PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM; + SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; + cpu_irq_enable(); + if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI) { + __DSB(); + __WFI(); + } else { + __DSB(); + __WFE(); + } + break; +#endif + + case SAM_PM_SMODE_WAIT_FAST: + case SAM_PM_SMODE_WAIT: { + uint32_t mor, pllr0, pllr1, mckr; + uint32_t fmr; +#if defined(EFC1) + uint32_t fmr1; +#endif +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70) + (sleep_mode == SAM_PM_SMODE_WAIT_FAST) ? + pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_STANDBY) : + pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN); +#endif + cpu_irq_disable(); + b_is_sleep_clock_used = true; + +#if (SAM4C || SAM4CM || SAM4CP) + /* Backup the sub-system 1 status and stop sub-system 1 */ + uint32_t cpclk_backup = PMC->PMC_SCSR & + (PMC_SCSR_CPCK | PMC_SCSR_CPBMCK); + PMC->PMC_SCDR = cpclk_backup | PMC_SCDR_CPKEY_PASSWD; +#endif + pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr, &fmr, +#if defined(EFC1) + &fmr1, +#endif + (sleep_mode == SAM_PM_SMODE_WAIT)); + + /* Enter wait mode */ + cpu_irq_enable(); + + pmc_enable_waitmode(); + + cpu_irq_disable(); + pmc_restore_clock_setting(mor, pllr0, pllr1, mckr, fmr +#if defined(EFC1) + , fmr1 +#endif + ); + +#if (SAM4C || SAM4CM || SAM4CP) + /* Restore the sub-system 1 */ + PMC->PMC_SCER = cpclk_backup | PMC_SCER_CPKEY_PASSWD; +#endif + b_is_sleep_clock_used = false; + if (callback_clocks_restored) { + callback_clocks_restored(); + callback_clocks_restored = NULL; + } + cpu_irq_enable(); + + break; + } +#if (!(SAMG51 || SAMG53 || SAMG54)) + case SAM_PM_SMODE_BACKUP: + SCB->SCR |= SCR_SLEEPDEEP; +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70) + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG; + cpu_irq_enable(); + __WFI() ; +#else + cpu_irq_enable(); + __WFE() ; +#endif + break; +#endif + } +} + +bool pmc_is_wakeup_clocks_restored(void) +{ + return !b_is_sleep_clock_used; +} + +void pmc_wait_wakeup_clocks_restore( + pmc_callback_wakeup_clocks_restored_t callback) +{ + if (b_is_sleep_clock_used) { + cpu_irq_disable(); + callback_clocks_restored = callback; + } else if (callback) { + callback(); + } +} + +#endif diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/sleep.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/sleep.h new file mode 100644 index 00000000..1a61237a --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/pmc/sleep.h @@ -0,0 +1,117 @@ +/** + * \file + * + * \brief Sleep mode access + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef SLEEP_H +#define SLEEP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \defgroup sleep_group Power Manager (PM) + * + * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr + * service. + * + * \note To minimize the code overhead, these functions do not feature + * interrupt-protected access since they are likely to be called inside + * interrupt handlers or in applications where such protection is not + * necessary. If such protection is needed, it must be ensured by the calling + * code. + * + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * \brief Sets the MCU in the specified sleep mode + * \param sleep_mode Sleep mode to set. + */ +#endif +/* SAM3,SAM4,SAMG,SAMV,SAME and SAMS series */ +#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \ + SAM4CM || SAM4CP || SAMG || SAMV71 || SAME70 || SAMS70) +# define SAM_PM_SMODE_ACTIVE 0 /**< Active */ +# define SAM_PM_SMODE_SLEEP_WFE 1 /**< Wait for Events */ +# define SAM_PM_SMODE_SLEEP_WFI 2 /**< Wait for Interrupts */ +# define SAM_PM_SMODE_WAIT_FAST 3 /**< Wait Mode, startup fast (in 3ms) */ +# define SAM_PM_SMODE_WAIT 4 /**< Wait Mode */ +#if (!(SAMG51 || SAMG53 || SAMG54)) +# define SAM_PM_SMODE_BACKUP 5 /**< Backup Mode */ +#endif + +/** (SCR) Sleep deep bit */ +#define SCR_SLEEPDEEP (0x1 << 2) + +/** + * Clocks restored callback function type. + * Registered by routine pmc_wait_wakeup_clocks_restore() + * Callback called when all clocks are restored. + */ +typedef void (*pmc_callback_wakeup_clocks_restored_t) (void); + +/** + * Enter sleep mode + * \param sleep_mode Sleep mode to enter + */ +void pmc_sleep(int sleep_mode); + +/** + * Check if clocks are restored after wakeup + * (For WAIT mode. In WAIT mode, clocks are switched to FASTRC. + * After wakeup clocks should be restored, before that some of the + * ISR should not be served, otherwise there may be timing or clock issue.) + */ +bool pmc_is_wakeup_clocks_restored(void); + +/** + * \return true if start waiting + */ +void pmc_wait_wakeup_clocks_restore( + pmc_callback_wakeup_clocks_restored_t callback); + +#endif + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* SLEEP_H */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/uart/uart.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/uart/uart.c new file mode 100644 index 00000000..888f2f88 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/uart/uart.c @@ -0,0 +1,552 @@ +/** + * \file + * + * \brief Universal Asynchronous Receiver Transceiver (UART) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "uart.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_uart_group Universal Asynchronous Receiver Transceiver (UART) + * + * The Universal Asynchronous Receiver Transmitter features a two-pin UART that + * can be used for communication and trace purposes and offers an ideal medium + * for in-situ programming solutions. Moreover, the association with two + * peripheral DMA controller (PDC) channels permits packet handling for these + * tasks with processor time reduced to a minimum. + * + * \par Usage + * + * -# Enable the UART peripheral clock in the PMC. + * -# Enable the required UART PIOs (see pio.h). + * -# Configure the UART by calling uart_init. + * -# Send data through the UART using the uart_write. + * -# Receive data from the UART using the uart_read; the availability of data + * can be polled with uart_is_rx_ready. + * -# Disable the transmitter and/or the receiver of the UART with + * uart_disable_tx and uart_disable_rx. + * + * @{ + */ + +/** + * \brief Configure UART with the specified parameters. + * + * \note The PMC and PIOs must be configured first. + * + * \param p_uart Pointer to a UART instance. + * \param p_uart_opt Pointer to sam_uart_opt_t instance. + * + * \retval 0 Success. + * \retval 1 Bad baud rate generator value. + */ +uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt) +{ + uint32_t cd = 0; + + /* Reset and disable receiver & transmitter */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS; + + /* Check and configure baudrate */ + /* Asynchronous, no oversampling */ + cd = (p_uart_opt->ul_mck / p_uart_opt->ul_baudrate) / UART_MCK_DIV; + if (cd < UART_MCK_DIV_MIN_FACTOR || cd > UART_MCK_DIV_MAX_FACTOR) + return 1; + + p_uart->UART_BRGR = cd; + /* Configure mode */ + p_uart->UART_MR = p_uart_opt->ul_mode; + +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) + /* Disable PDC channel */ + p_uart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; +#endif + + /* Enable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; + + return 0; +} + +/** + * \brief Enable UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable_tx(Uart *p_uart) +{ + /* Enable transmitter */ + p_uart->UART_CR = UART_CR_TXEN; +} + +/** + * \brief Disable UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable_tx(Uart *p_uart) +{ + /* Disable transmitter */ + p_uart->UART_CR = UART_CR_TXDIS; +} + +/** + * \brief Reset UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset_tx(Uart *p_uart) +{ + /* Reset transmitter */ + p_uart->UART_CR = UART_CR_RSTTX | UART_CR_TXDIS; +} + +/** + * \brief Enable UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable_rx(Uart *p_uart) +{ + /* Enable receiver */ + p_uart->UART_CR = UART_CR_RXEN; +} + +/** + * \brief Disable UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable_rx(Uart *p_uart) +{ + /* Disable receiver */ + p_uart->UART_CR = UART_CR_RXDIS; +} + +/** + * \brief Reset UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset_rx(Uart *p_uart) +{ + /* Reset receiver */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RXDIS; +} + +/** + * \brief Enable UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable(Uart *p_uart) +{ + /* Enable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; +} + +/** + * \brief Disable UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable(Uart *p_uart) +{ + /* Disable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXDIS | UART_CR_TXDIS; +} + +/** + * \brief Reset UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset(Uart *p_uart) +{ + /* Reset and disable receiver & transmitter */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS; +} + +/** \brief Enable UART interrupts. + * + * \param p_uart Pointer to a UART instance. + * \param ul_sources Interrupts to be enabled. + */ +void uart_enable_interrupt(Uart *p_uart, uint32_t ul_sources) +{ + p_uart->UART_IER = ul_sources; +} + +/** \brief Disable UART interrupts. + * + * \param p_uart Pointer to a UART instance. + * \param ul_sources Interrupts to be disabled. + */ +void uart_disable_interrupt(Uart *p_uart, uint32_t ul_sources) +{ + p_uart->UART_IDR = ul_sources; +} + +/** \brief Read UART interrupt mask. + * + * \param p_uart Pointer to a UART instance. + * + * \return The interrupt mask value. + */ +uint32_t uart_get_interrupt_mask(Uart *p_uart) +{ + return p_uart->UART_IMR; +} + +/** + * \brief Get current status. + * + * \param p_uart Pointer to a UART instance. + * + * \return The current UART status. + */ +uint32_t uart_get_status(Uart *p_uart) +{ + return p_uart->UART_SR; +} + +/** + * \brief Reset status bits. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset_status(Uart *p_uart) +{ + p_uart->UART_CR = UART_CR_RSTSTA; +} + +/** + * \brief Check if Transmit is Ready. + * Check if data has been loaded in UART_THR and is waiting to be loaded in the + * Transmit Shift Register (TSR). + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Data has been transmitted. + * \retval 0 Transmit is not ready, data pending. + */ +uint32_t uart_is_tx_ready(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXRDY) > 0; +} + +/** + * \brief Check if Transmit Hold Register is empty. + * Check if the last data written in UART_THR has been loaded in TSR and the + * last data loaded in TSR has been transmitted. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmitter is empty. + * \retval 0 Transmitter is not empty. + */ +uint32_t uart_is_tx_empty(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXEMPTY) > 0; +} + +/** + * \brief Check if Received data is ready. + * Check if data has been received and loaded in UART_RHR. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 One data has been received. + * \retval 0 No data has been received. + */ +uint32_t uart_is_rx_ready(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_RXRDY) > 0; +} + +/** + * \brief Check if both transmit buffers are sent out. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmit buffer is empty. + * \retval 0 Transmit buffer is not empty. + */ +uint32_t uart_is_tx_buf_empty(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXEMPTY) > 0; +} + +/** + * \brief Set UART clock divisor value + * + * \param p_uart Pointer to a UART instance. + * \param us_divisor Value to be set. + * + */ +void uart_set_clock_divisor(Uart *p_uart, uint16_t us_divisor) +{ + p_uart->UART_BRGR = us_divisor; +} + +/** + * \brief Write to UART Transmit Holding Register + * Before writing user should check if tx is ready (or empty). + * + * \param p_uart Pointer to a UART instance. + * \param data Data to be sent. + * + * \retval 0 Success. + * \retval 1 I/O Failure, UART is not ready. + */ +uint32_t uart_write(Uart *p_uart, const uint8_t uc_data) +{ + /* Check if the transmitter is ready */ + if (!(p_uart->UART_SR & UART_SR_TXRDY)) + return 1; + + /* Send character */ + p_uart->UART_THR = uc_data; + return 0; +} + +/** + * \brief Read from UART Receive Holding Register. + * Before reading user should check if rx is ready. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 0 Success. + * \retval 1 I/O Failure, UART is not ready. + */ +uint32_t uart_read(Uart *p_uart, uint8_t *puc_data) +{ + /* Check if the receiver is ready */ + if ((p_uart->UART_SR & UART_SR_RXRDY) == 0) + return 1; + + /* Read character */ + *puc_data = (uint8_t) p_uart->UART_RHR; + return 0; +} + +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Check if one receive buffer is filled. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Receive is completed. + * \retval 0 Receive is still pending. + */ +uint32_t uart_is_rx_buf_end(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_ENDRX) > 0; +} + +/** + * \brief Check if one transmit buffer is sent out. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmit is completed. + * \retval 0 Transmit is still pending. + */ +uint32_t uart_is_tx_buf_end(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_ENDTX) > 0; +} + +/** + * \brief Check if both receive buffers are full. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Receive buffers are full. + * \retval 0 Receive buffers are not full. + */ +uint32_t uart_is_rx_buf_full(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_RXBUFF) > 0; +} + +/** + * \brief Get UART PDC base address. + * + * \param p_uart Pointer to a UART instance. + * + * \return UART PDC registers base for PDC driver to access. + */ +Pdc *uart_get_pdc_base(Uart *p_uart) +{ + Pdc *p_pdc_base; + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) + if (p_uart == UART0) + p_pdc_base = PDC_UART0; +#elif (SAM3XA || SAM3U) + if (p_uart == UART) + p_pdc_base = PDC_UART; +#else +#error "Unsupported device" +#endif + +#if (SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) + if (p_uart == UART1) + p_pdc_base = PDC_UART1; +#endif + +#if (SAM4N) + if (p_uart == UART2) + p_pdc_base = PDC_UART2; +#endif + + return p_pdc_base; +} +#endif + +#if (SAM4C || SAM4CP || SAM4CM) +/** + * \brief Enable UART optical interface. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable_optical_interface(Uart *p_uart) +{ + Assert(p_uart == UART1); + p_uart->UART_MR |= UART_MR_OPT_EN; +} + +/** + * \brief Disable UART optical interface. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable_optical_interface(Uart *p_uart) +{ + Assert(p_uart == UART1); + p_uart->UART_MR &= ~UART_MR_OPT_EN; +} + +/** + * \brief Enable UART optical interface. + * + * \param p_uart Pointer to a UART instance. + * \param cfg Pointer to a UART optical interface configuration. + */ +void uart_config_optical_interface(Uart *p_uart, + struct uart_config_optical *cfg) +{ + Assert(p_uart == UART1); + uint32_t reg = p_uart->UART_MR; + + reg &= ~(UART_MR_OPT_RXINV | UART_MR_OPT_MDINV | UART_MR_FILTER + | UART_MR_OPT_CLKDIV_Msk | UART_MR_OPT_DUTY_Msk + | UART_MR_OPT_CMPTH_Msk); + reg |= (cfg->rx_inverted ? UART_MR_OPT_RXINV : 0) + | (cfg->tx_inverted ? UART_MR_OPT_MDINV : 0) + | (cfg->rx_filter ? UART_MR_FILTER : 0) + | UART_MR_OPT_CLKDIV(cfg->clk_div) + | cfg->duty | cfg->threshold; + + p_uart->UART_MR = reg; +} +#endif + +#if (SAMG53 || SAMG54 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Set sleepwalking match mode. + * + * \param p_uart Pointer to a UART instance. + * \param ul_low_value First comparison value for received character. + * \param ul_high_value Second comparison value for received character. + * \param cmpmode ture for start condition, false for flag only. + * \param cmppar ture for parity check, false for no. + */ +void uart_set_sleepwalking(Uart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value) +{ + Assert(ul_low_value <= ul_high_value); + + uint32_t temp = 0; + + if (cmpmode) { + temp |= UART_CMPR_CMPMODE_START_CONDITION; + } + + if (cmppar) { + temp |= UART_CMPR_CMPPAR; + } + + temp |= UART_CMPR_VAL1(ul_low_value); + + temp |= UART_CMPR_VAL2(ul_high_value); + + p_uart->UART_CMPR= temp; +} + +/** + * \brief Enables/Disables write protection mode. + * + * \param p_uart Pointer to a UART instance. + * \param flag ture for enable, false for disable. + */ +void uart_set_write_protection(Uart *p_uart, bool flag) +{ + if (flag) { + p_uart->UART_WPMR = UART_WPMR_WPKEY_PASSWD | UART_WPMR_WPEN; + } else { + p_uart->UART_WPMR = UART_WPMR_WPKEY_PASSWD; + } +} +#endif + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/uart/uart.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/uart/uart.h new file mode 100644 index 00000000..ebac3cf0 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/uart/uart.h @@ -0,0 +1,150 @@ +/** + * \file + * + * \brief Universal Asynchronous Receiver Transceiver (UART) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef UART_H_INCLUDED +#define UART_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/* UART internal div factor for sampling */ +#define UART_MCK_DIV 16 +/* Div factor to get the maximum baud rate */ +#define UART_MCK_DIV_MIN_FACTOR 1 +/* Div factor to get the minimum baud rate */ +#define UART_MCK_DIV_MAX_FACTOR 65535 + +/*! \brief Option list for UART peripheral initialization */ +typedef struct sam_uart_opt { + /** MCK for UART */ + uint32_t ul_mck; + /** Expected baud rate */ + uint32_t ul_baudrate; + /** Initialize value for UART mode register */ + uint32_t ul_mode; +} sam_uart_opt_t; + +uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt); +void uart_enable_tx(Uart *p_uart); +void uart_disable_tx(Uart *p_uart); +void uart_reset_tx(Uart *p_uart); +void uart_enable_rx(Uart *p_uart); +void uart_disable_rx(Uart *p_uart); +void uart_reset_rx(Uart *p_uart); +void uart_enable(Uart *p_uart); +void uart_disable(Uart *p_uart); +void uart_reset(Uart *p_uart); +void uart_enable_interrupt(Uart *p_uart, uint32_t ul_sources); +void uart_disable_interrupt(Uart *p_uart, uint32_t ul_sources); +uint32_t uart_get_interrupt_mask(Uart *p_uart); +uint32_t uart_get_status(Uart *p_uart); +void uart_reset_status(Uart *p_uart); +uint32_t uart_is_tx_ready(Uart *p_uart); +uint32_t uart_is_tx_empty(Uart *p_uart); +uint32_t uart_is_rx_ready(Uart *p_uart); +uint32_t uart_is_tx_buf_empty(Uart *p_uart); +void uart_set_clock_divisor(Uart *p_uart, uint16_t us_divisor); +uint32_t uart_write(Uart *p_uart, const uint8_t uc_data); +uint32_t uart_read(Uart *p_uart, uint8_t *puc_data); +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +uint32_t uart_is_rx_buf_end(Uart *p_uart); +uint32_t uart_is_tx_buf_end(Uart *p_uart); +uint32_t uart_is_rx_buf_full(Uart *p_uart); +Pdc *uart_get_pdc_base(Uart *p_uart); +#endif +#if (SAMG53 || SAMG54 || SAMV71 || SAMV70 || SAME70 || SAMS70) +void uart_set_sleepwalking(Uart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value); +void uart_set_write_protection(Uart *p_uart, bool flag); +#endif + +#if (SAM4C || SAM4CP || SAM4CM) +enum uart_optical_duty_cycle { + UART_MOD_CLK_DUTY_50_00 = UART_MR_OPT_DUTY_DUTY_50, + UART_MOD_CLK_DUTY_43_75 = UART_MR_OPT_DUTY_DUTY_43P75, + UART_MOD_CLK_DUTY_37_50 = UART_MR_OPT_DUTY_DUTY_37P5, + UART_MOD_CLK_DUTY_31_25 = UART_MR_OPT_DUTY_DUTY_31P25, + UART_MOD_CLK_DUTY_25_00 = UART_MR_OPT_DUTY_DUTY_25, + UART_MOD_CLK_DUTY_18_75 = UART_MR_OPT_DUTY_DUTY_18P75, + UART_MOD_CLK_DUTY_12_50 = UART_MR_OPT_DUTY_DUTY_12P5, + UART_MOD_CLK_DUTY_06_25 = UART_MR_OPT_DUTY_DUTY_6P25, +}; + +enum uart_optical_cmp_threshold { + UART_RX_CMP_THRESHOLD_VDDIO_DIV_10_0 = UART_MR_OPT_CMPTH_VDDIO_DIV10, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_5_0 = UART_MR_OPT_CMPTH_VDDIO_DIV5, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_3_3 = UART_MR_OPT_CMPTH_VDDIO_DIV3P3, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_2_5 = UART_MR_OPT_CMPTH_VDDIO_DIV2P5, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_2_0 = UART_MR_OPT_CMPTH_VDDIO_DIV2, +}; + +struct uart_config_optical { + /* UART Receive Data Inverted */ + bool rx_inverted; + /* UART Modulated Data Inverted */ + bool tx_inverted; + /* UART Receiver Digital Filter */ + bool rx_filter; + /* Optical Link Clock Divider */ + uint8_t clk_div; + /* Optical Link Modulation Clock Duty Cycle */ + enum uart_optical_duty_cycle duty; + /* Receive Path Comparator Threshold */ + enum uart_optical_cmp_threshold threshold; +}; + +void uart_enable_optical_interface(Uart *p_uart); +void uart_disable_optical_interface(Uart *p_uart); +void uart_config_optical_interface(Uart *p_uart, + struct uart_config_optical *cfg); +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* UART_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/usart/usart.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/usart/usart.c new file mode 100644 index 00000000..34680b24 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/usart/usart.c @@ -0,0 +1,2094 @@ +/** + * \file + * + * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver + * for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "usart.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_usart_group Universal Synchronous Asynchronous + * Receiver Transmitter (USART) + * + * The Universal Synchronous Asynchronous Receiver Transceiver (USART) + * provides one full duplex universal synchronous asynchronous serial link. + * Data frame format is widely programmable (data length, parity, number of + * stop bits) to support a maximum of standards. The receiver implements + * parity error, framing error and overrun error detection. The receiver + * time-out enables handling variable-length frames and the transmitter + * timeguard facilitates communications with slow remote devices. Multidrop + * communications are also supported through address bit handling in reception + * and transmission. The driver supports the following modes: + * RS232, RS485, SPI, IrDA, ISO7816, MODEM, Hardware handshaking and LIN. + * + * @{ + */ + +/* The write protect key value. */ +#ifndef US_WPMR_WPKEY_PASSWD +#define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(0x555341U) +#endif + +#ifndef US_WPMR_WPKEY_PASSWD +# define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(US_WPKEY_VALUE) +#endif + +/* The CD value scope programmed in MR register. */ +#define MIN_CD_VALUE 0x01 +#define MIN_CD_VALUE_SPI 0x04 +#define MAX_CD_VALUE US_BRGR_CD_Msk + +/* The receiver sampling divide of baudrate clock. */ +#define HIGH_FRQ_SAMPLE_DIV 16 +#define LOW_FRQ_SAMPLE_DIV 8 + +/* Max transmitter timeguard. */ +#define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk + +/* The non-existent parity error number. */ +#define USART_PARITY_ERROR 5 + +/* ISO7816 protocol type. */ +#define ISO7816_T_0 0 +#define ISO7816_T_1 1 + +/** + * \brief Calculate a clock divider(CD) and a fractional part (FP) for the + * USART asynchronous modes to generate a baudrate as close as possible to + * the baudrate set point. + * + * \note Baud rate calculation: Baudrate = ul_mck/(Over * (CD + FP/8)) + * (Over being 16 or 8). The maximal oversampling is selected if it allows to + * generate a baudrate close to the set point. + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +uint32_t usart_set_async_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t over; + uint32_t cd_fp; + uint32_t cd; + uint32_t fp; + + /* Calculate the receiver sampling divide of baudrate clock. */ + if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) { + over = HIGH_FRQ_SAMPLE_DIV; + } else { + over = LOW_FRQ_SAMPLE_DIV; + } + + /* Calculate clock divider according to the fraction calculated formula. */ + cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate); + cd = cd_fp >> 3; + fp = cd_fp & 0x07; + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + /* Configure the OVER bit in MR register. */ + if (over == 8) { + p_usart->US_MR |= US_MR_OVER; + } + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos); + + return 0; +} + +/** + * \brief Calculate a clock divider for the USART synchronous master modes + * to generate a baudrate as close as possible to the baudrate set point. + * + * \note Synchronous baudrate calculation: baudrate = ul_mck / cd + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_sync_master_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate clock divider according to the formula in synchronous mode. */ + cd = (ul_mck + baudrate / 2) / baudrate; + + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | + US_MR_USCLKS_MCK | US_MR_SYNC; + return 0; +} + +/** + * \brief Select the SCK pin as the source of baud rate for the USART + * synchronous slave modes. + * + * \param p_usart Pointer to a USART instance. + */ +static void usart_set_sync_slave_baudrate(Usart *p_usart) +{ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | + US_MR_USCLKS_SCK | US_MR_SYNC; +} + +/** + * \brief Calculate a clock divider (\e CD) for the USART SPI master mode to + * generate a baud rate as close as possible to the baud rate set point. + * + * \note Baud rate calculation: + * \f$ Baudrate = \frac{SelectedClock}{CD} \f$. + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_spi_master_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate the clock divider according to the formula in SPI mode. */ + cd = (ul_mck + baudrate / 2) / baudrate; + + if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) { + return 1; + } + + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + return 0; +} + +/** + * \brief Select the SCK pin as the source of baudrate for the USART SPI slave + * mode. + * + * \param p_usart Pointer to a USART instance. + */ +static void usart_set_spi_slave_baudrate(Usart *p_usart) +{ + p_usart->US_MR &= ~US_MR_USCLKS_Msk; + p_usart->US_MR |= US_MR_USCLKS_SCK; +} + +/** + * \brief Reset the USART and disable TX and RX. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset(Usart *p_usart) +{ + /* Disable the Write Protect. */ + usart_disable_writeprotect(p_usart); + + /* Reset registers that could cause unpredictable behavior after reset. */ + p_usart->US_MR = 0; + p_usart->US_RTOR = 0; + p_usart->US_TTGR = 0; + + /* Disable TX and RX. */ + usart_reset_tx(p_usart); + usart_reset_rx(p_usart); + /* Reset status bits. */ + usart_reset_status(p_usart); + /* Turn off RTS and DTR if exist. */ + usart_drive_RTS_pin_high(p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + usart_drive_DTR_pin_high(p_usart); +#endif +} + +/** + * \brief Configure USART to work in RS232 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_rs232(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || usart_set_async_baudrate(p_usart, + p_usart_opt->baudrate, ul_mck)) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Configure the USART mode as normal mode. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL; + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in hardware handshaking mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_hw_handshaking(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set hardware handshaking mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_HW_HANDSHAKING; + + return 0; +} + +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + +/** + * \brief Configure USART to work in modem mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_modem(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* + * SAM3S, SAM4S and SAM4E series support MODEM mode only on USART1, + * SAM3U and SAM4L series support MODEM mode only on USART0. + */ +#if (SAM3S || SAM4S || SAM4E) +#ifdef USART1 + if (p_usart != USART1) { + return 1; + } +#endif +#elif (SAM3U || SAM4L) + if (p_usart != USART0) { + return 1; + } +#endif + + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set MODEM mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_MODEM; + + return 0; +} +#endif + +/** + * \brief Configure USART to work in SYNC mode and act as a master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_sync_master(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || usart_set_sync_master_baudrate(p_usart, + p_usart_opt->baudrate, ul_mck)) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Set normal mode and output clock as synchronous master. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO; + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in SYNC mode and act as a slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_sync_slave(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + usart_set_sync_slave_baudrate(p_usart); + + /* Check whether the input values are legal. */ + if (!p_usart_opt) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Set normal mode. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL; + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in RS485 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_rs485(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set RS485 mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_RS485; + + return 0; +} + +#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Configure USART to work in IrDA mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_irda(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set IrDA filter. */ + p_usart->US_IF = p_usart_opt->irda_filter; + + /* Set IrDA mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_IRDA; + + return 0; +} +#endif + +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Calculate a clock divider (\e CD) for the USART ISO7816 mode to + * generate an ISO7816 clock as close as possible to the clock set point. + * + * \note ISO7816 clock calculation: Clock = ul_mck / cd + * + * \param p_usart Pointer to a USART instance. + * \param clock ISO7816 clock set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 ISO7816 clock is successfully initialized. + * \retval 1 ISO7816 clock set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_iso7816_clock(Usart *p_usart, + uint32_t clock, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate clock divider according to the formula in ISO7816 mode. */ + cd = (ul_mck + clock / 2) / clock; + + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC | + US_MR_OVER)) | US_MR_USCLKS_MCK | US_MR_CLKO; + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + return 0; +} + +/** + * \brief Configure USART to work in ISO7816 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_iso7816(Usart *p_usart, + const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + + /* Check whether the input values are legal. */ + if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) && + (p_usart_opt->parity_type != US_MR_PAR_ODD))) { + return 1; + } + + if (p_usart_opt->protocol_type == ISO7816_T_0) { + ul_reg_val |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT | + (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos); + + if (p_usart_opt->bit_order) { + ul_reg_val |= US_MR_MSBF; + } + } else if (p_usart_opt->protocol_type == ISO7816_T_1) { + /* + * Only LSBF is used in the T=1 protocol, and max_iterations field + * is only used in T=0 mode. + */ + if (p_usart_opt->bit_order || p_usart_opt->max_iterations) { + return 1; + } + + /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */ + ul_reg_val |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT; + } else { + return 1; + } + + /* Set up the baudrate. */ + if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) { + return 1; + } + + /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */ + p_usart->US_FIDI = p_usart_opt->fidi_ratio; + + /* Set ISO7816 parity type in the MODE register. */ + ul_reg_val |= p_usart_opt->parity_type; + + if (p_usart_opt->inhibit_nack) { + ul_reg_val |= US_MR_INACK; + } + if (p_usart_opt->dis_suc_nack) { + ul_reg_val |= US_MR_DSNACK; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_iterations(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTIT; +} + +/** + * \brief Reset NACK in US_CSR. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_nack(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTNACK; +} + +/** + * \brief Check if both receive buffers are full. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Receive buffers are full. + * \retval 0 Receive buffers are not full. + */ +uint32_t usart_is_rx_buf_full(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_RXBUFF) > 0; +} + +#if (!SAM4L) +/** + * \brief Check if one receive buffer is filled. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Receive is complete. + * \retval 0 Receive is still pending. + */ +uint32_t usart_is_rx_buf_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_ENDRX) > 0; +} + +/** + * \brief Check if one transmit buffer is empty. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmit is complete. + * \retval 0 Transmit is still pending. + */ +uint32_t usart_is_tx_buf_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_ENDTX) > 0; +} + +/** + * \brief Check if both transmit buffers are empty. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmit buffers are empty. + * \retval 0 Transmit buffers are not empty. + */ +uint32_t usart_is_tx_buf_empty(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXBUFE) > 0; +} +#endif + +/** + * \brief Get the total number of errors that occur during an ISO7816 transfer. + * + * \param p_usart Pointer to a USART instance. + * + * \return The number of errors that occurred. + */ +uint8_t usart_get_error_number(Usart *p_usart) +{ + return (p_usart->US_NER & US_NER_NB_ERRORS_Msk); +} + +#endif + +/** + * \brief Configure USART to work in SPI mode and act as a master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_spi_master(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || (p_usart_opt->spi_mode > SPI_MODE_3) || + usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate, + ul_mck)) { + return 1; + } + + /* Configure the character length bit in MR register. */ + ul_reg_val |= p_usart_opt->char_length; + + /* Set SPI master mode and channel mode. */ + ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO | + p_usart_opt->channel_mode; + + switch (p_usart_opt->spi_mode) { + case SPI_MODE_0: + ul_reg_val |= US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_1: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_2: + ul_reg_val |= US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + case SPI_MODE_3: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + default: + break; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in SPI mode and act as a slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_spi_slave(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + usart_set_spi_slave_baudrate(p_usart); + + /* Check whether the input values are legal. */ + if (!p_usart_opt || p_usart_opt->spi_mode > SPI_MODE_3) { + return 1; + } + + /* Configure the character length bit in MR register. */ + ul_reg_val |= p_usart_opt->char_length; + + /* Set SPI slave mode and channel mode. */ + ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode; + + switch (p_usart_opt->spi_mode) { + case SPI_MODE_0: + ul_reg_val |= US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_1: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_2: + ul_reg_val |= US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + case SPI_MODE_3: + ul_reg_val |= US_MR_CPOL; + ul_reg_val &= ~US_MR_CPHA; + break; + + default: + break; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +#if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + +/** + * \brief Configure USART to work in LIN mode and act as a LIN master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param ul_baudrate Baudrate to be used. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_lin_master(Usart *p_usart,uint32_t ul_baudrate, + uint32_t ul_mck) +{ + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + /* Set up the baudrate. */ + if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { + return 1; + } + + /* Set LIN master mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_LIN_MASTER; + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); + + return 0; +} + +/** + * \brief Configure USART to work in LIN mode and act as a LIN slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param ul_baudrate Baudrate to be used. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck) +{ + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); + + /* Set LIN slave mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_LIN_SLAVE; + + /* Set up the baudrate. */ + if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { + return 1; + } + + return 0; +} + +/** + * \brief Abort the current LIN transmission. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_abort_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_LINABT; +} + +/** + * \brief Send a wakeup signal on the LIN bus. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_send_wakeup_signal(Usart *p_usart) +{ + p_usart->US_CR = US_CR_LINWKUP; +} + +/** + * \brief Configure the LIN node action, which should be one of PUBLISH, + * SUBSCRIBE or IGNORE. + * + * \param p_usart Pointer to a USART instance. + * \param uc_action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE. + */ +void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) | + (uc_action << US_LINMR_NACT_Pos); +} + +/** + * \brief Disable the parity check during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_parity(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_PARDIS; +} + +/** + * \brief Enable the parity check during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_parity(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_PARDIS; +} + +/** + * \brief Disable the checksum during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_checksum(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_CHKDIS; +} + +/** + * \brief Enable the checksum during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_checksum(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_CHKDIS; +} + +/** + * \brief Configure the checksum type during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic + * checksum. + */ +void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) | + (uc_type << 4); +} + +/** + * \brief Configure the data length mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_mode Indicate the data length type: 0 if the data length is + * defined by the DLC of LIN mode register or 1 if the data length is defined + * by the bit 5 and 6 of the identifier. + */ +void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) | + (uc_mode << 5); +} + +/** + * \brief Disable the frame slot mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_frame_slot(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_FSDIS; +} + +/** + * \brief Enable the frame slot mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_frame_slot(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_FSDIS; +} + +/** + * \brief Configure the wakeup signal type during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type Indicate the checksum type: 0 if the wakeup signal is a + * LIN 2.0 wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal. + */ +void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) | + (uc_type << 7); +} + +/** + * \brief Configure the response data length if the data length is defined by + * the DLC field during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len Indicate the response data length. + */ +void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) | + ((uc_len - 1) << US_LINMR_DLC_Pos); +} + +/** + * \brief The LIN mode register is not written by the PDC. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_pdc_mode(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_PDCM; +} + +/** + * \brief The LIN mode register (except this flag) is written by the PDC. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_pdc_mode(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_PDCM; +} + +/** + * \brief Configure the LIN identifier when USART works in LIN master mode. + * + * \param p_usart Pointer to a USART instance. + * \param uc_id The identifier to be transmitted. + */ +void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id) +{ + p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) | + US_LINIR_IDCHR(uc_id); +} + +/** + * \brief Read the identifier when USART works in LIN mode. + * + * \param p_usart Pointer to a USART instance. + * + * \return The last identifier received in LIN slave mode or the last + * identifier transmitted in LIN master mode. + */ +uint8_t usart_lin_read_identifier(Usart *p_usart) +{ + return (p_usart->US_LINIR & US_LINIR_IDCHR_Msk); +} + +/** + * \brief Get data length. + * + * \param p_usart Pointer to a USART instance. + * + * \return Data length. + */ +uint8_t usart_lin_get_data_length(Usart *usart) +{ + if (usart->US_LINMR & US_LINMR_DLM) { + uint8_t data_length = 1 << ((usart->US_LINIR >> + (US_LINIR_IDCHR_Pos + 4)) & 0x03); + return data_length; + } else { + return ((usart->US_LINMR & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos) + 1; + } +} + +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Get identifier send status. + * + * \param p_usart Pointer to a USART instance. + * + * \return + * 0: No LIN identifier has been sent since the last RSTSTA. + * 1: :At least one LIN identifier has been sent since the last RSTSTA. + */ +uint8_t usart_lin_identifier_send_complete(Usart *usart) +{ + return (usart->US_CSR & US_CSR_LINID) > 0; +} + +/** + * \brief Get identifier received status. + * + * \param p_usart Pointer to a USART instance. + * + * \return + * 0: No LIN identifier has been reveived since the last RSTSTA. + * 1: At least one LIN identifier has been received since the last RSTSTA. + */ +uint8_t usart_lin_identifier_reception_complete(Usart *usart) +{ + return (usart->US_CSR & US_CSR_LINID) > 0; +} + +/** + * \brief Get transmission status. + * + * \param p_usart Pointer to a USART instance. + * + * \return + * 0: The USART is idle or a LIN transfer is ongoing. + * 1: A LIN transfer has been completed since the last RSTSTA. + */ +uint8_t usart_lin_tx_complete(Usart *usart) +{ + return (usart->US_CSR & US_CSR_LINTC) > 0; +} + +/** + * \brief Configure USART to work in LON mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param ul_baudrate Baudrate to be used. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_lon(Usart *p_usart,uint32_t ul_baudrate, + uint32_t ul_mck) +{ + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + /* Set up the baudrate. */ + if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { + return 1; + } + + /* Set LIN master mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_LON; + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); + + return 0; +} + +/** + * \brief set LON parameter value. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: LON comm_type = 1 mode, + * 1: LON comm_type = 2 mode + */ +void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_COMMT) | + (uc_type << 0); +} + +/** + * \brief Disable LON Collision Detection Feature. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lon_disable_coll_detection(Usart *p_usart) +{ + p_usart->US_LONMR |= US_LONMR_COLDET; +} + +/** + * \brief Enable LON Collision Detection Feature. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lon_enable_coll_detection(Usart *p_usart) +{ + p_usart->US_LONMR &= ~US_LONMR_COLDET; +} + +/** + * \brief set Terminate Frame upon Collision Notification. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: Do not terminate the frame in LON comm_type = 1 mode upon collision detection. + * 1:Terminate the frame in LON comm_type = 1 mode upon collision detection if possible. + */ +void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_TCOL) | + (uc_type << 2); +} + +/** + * \brief set LON Collision Detection on Frame Tail. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: Detect collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode. + * 1: Ignore collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode. + */ +void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_CDTAIL) | + (uc_type << 3); +} + +/** + * \brief set LON DMA Mode. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: The LON data length register US_LONDL is not written by the DMA. + * 1: The LON data length register US_LONDL is written by the DMA. + */ +void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_DMAM) | + (uc_type << 4); +} + +/** + * \brief set LON Beta1 Length after Transmission. + * + * \param p_usart Pointer to a USART instance. + * \param ul_len 1-16777215: LON beta1 length after transmission in tbit + */ +void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len) +{ + p_usart->US_LONB1TX = US_LONB1TX_BETA1TX(ul_len); +} + +/** + * \brief set LON Beta1 Length after Reception. + * + * \param p_usart Pointer to a USART instance. + * \param ul_len 1-16777215: LON beta1 length after reception in tbit. + */ +void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len) +{ + p_usart->US_LONB1RX = US_LONB1RX_BETA1RX(ul_len); +} + +/** + * \brief set LON Priority. + * + * \param p_usart Pointer to a USART instance. + * \param uc_psnb 0 -127: LON Priority Slot Number. + * \param uc_nps 0 -127: LON Node Priority Slot. + */ +void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps) +{ + p_usart->US_LONPRIO = US_LONPRIO_PSNB(uc_psnb) | US_LONPRIO_NPS(uc_nps); +} + +/** + * \brief set LON Indeterminate Time after Transmission. + * + * \param p_usart Pointer to a USART instance. + * \param ul_time 1-16777215: LON Indeterminate Time after Transmission (comm_type = 1 mode only). + */ +void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time) +{ + p_usart->US_IDTTX = US_IDTTX_IDTTX(ul_time); +} + +/** + * \brief set LON Indeterminate Time after Reception. + * + * \param p_usart Pointer to a USART instance. + * \param ul_time 1-16777215: LON Indeterminate Time after Reception (comm_type = 1 mode only). + */ +void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time) +{ + p_usart->US_IDTRX = US_IDTRX_IDTRX(ul_time); +} + +/** + * \brief set LON Preamble Length. + * + * \param p_usart Pointer to a USART instance. + * \param ul_len 1-16383: LON preamble length in tbit(without byte-sync). + */ +void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len) +{ + p_usart->US_LONPR = US_LONPR_LONPL(ul_len); +} + +/** + * \brief set LON Data Length. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len 0-255: LON data length is LONDL+1 bytes. + */ +void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_LONDL = US_LONDL_LONDL(uc_len); +} + +/** + * \brief set LON Priority. + * + * \param p_usart Pointer to a USART instance. + * \param uc_bli LON Backlog Increment. + * \param uc_altp LON Alternate Path Bit. + * \param uc_pb LON Priority Bit. + */ +void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb) +{ + p_usart->US_LONL2HDR = US_LONL2HDR_BLI(uc_bli) | (uc_altp << 6) | (uc_pb << 7); +} + +/** + * \brief Check if LON Transmission End. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 At least one transmission has been performed since the last RSTSTA. + * \retval 0 Transmission on going or no transmission occurred since the last RSTSTA. + */ +uint32_t usart_lon_is_tx_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_LTXD) > 0; +} + +/** + * \brief Check if LON Reception End. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 At least one Reception has been performed since the last RSTSTA. + * \retval 0 Reception on going or no Reception occurred since the last RSTSTA. + */ +uint32_t usart_lon_is_rx_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_LRXD) > 0; +} +#endif + +/** + * \brief Enable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_TXEN; +} + +/** + * \brief Disable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_TXDIS; +} + +/** + * \brief Immediately stop and disable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_tx(Usart *p_usart) +{ + /* Reset transmitter */ + p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS; +} + +/** + * \brief Configure the transmit timeguard register. + * + * \param p_usart Pointer to a USART instance. + * \param timeguard The value of transmit timeguard. + */ +void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard) +{ + p_usart->US_TTGR = timeguard; +} + +/** + * \brief Enable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_rx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RXEN; +} + +/** + * \brief Disable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_rx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RXDIS; +} + +/** + * \brief Immediately stop and disable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_rx(Usart *p_usart) +{ + /* Reset Receiver */ + p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS; +} + +/** + * \brief Configure the receive timeout register. + * + * \param p_usart Pointer to a USART instance. + * \param timeout The value of receive timeout. + */ +void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout) +{ + p_usart->US_RTOR = timeout; +} + +/** + * \brief Enable USART interrupts. + * + * \param p_usart Pointer to a USART peripheral. + * \param ul_sources Interrupt sources bit map. + */ +void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources) +{ + p_usart->US_IER = ul_sources; +} + +/** + * \brief Disable USART interrupts. + * + * \param p_usart Pointer to a USART peripheral. + * \param ul_sources Interrupt sources bit map. + */ +void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources) +{ + p_usart->US_IDR = ul_sources; +} + +/** + * \brief Read USART interrupt mask. + * + * \param p_usart Pointer to a USART peripheral. + * + * \return The interrupt mask value. + */ +uint32_t usart_get_interrupt_mask(Usart *p_usart) +{ + return p_usart->US_IMR; +} + +/** + * \brief Get current status. + * + * \param p_usart Pointer to a USART instance. + * + * \return The current USART status. + */ +uint32_t usart_get_status(Usart *p_usart) +{ + return p_usart->US_CSR; +} + +/** + * \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR). + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_status(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTSTA; +} + +/** + * \brief Start transmission of a break. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_start_tx_break(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STTBRK; +} + +/** + * \brief Stop transmission of a break. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_stop_tx_break(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STPBRK; +} + +/** + * \brief Start waiting for a character before clocking the timeout count. + * Reset the status bit TIMEOUT in US_CSR. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_start_rx_timeout(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STTTO; +} + +/** + * \brief In Multidrop mode only, the next character written to the US_THR + * is sent with the address bit set. + * + * \param p_usart Pointer to a USART instance. + * \param ul_addr The address to be sent out. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr) +{ + if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) { + return 1; + } + + p_usart->US_CR = US_CR_SENDA; + + if (usart_write(p_usart, ul_addr)) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Restart the receive timeout. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_restart_rx_timeout(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RETTO; +} + +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + +/** + * \brief Drive the pin DTR to 0. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_DTR_pin_low(Usart *p_usart) +{ + p_usart->US_CR = US_CR_DTREN; +} + +/** + * \brief Drive the pin DTR to 1. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_DTR_pin_high(Usart *p_usart) +{ + p_usart->US_CR = US_CR_DTRDIS; +} + +#endif + +/** + * \brief Drive the pin RTS to 0. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_RTS_pin_low(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RTSEN; +} + +/** + * \brief Drive the pin RTS to 1. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_RTS_pin_high(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RTSDIS; +} + +/** + * \brief Drive the slave select line NSS (RTS pin) to 0 in SPI master mode. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_spi_force_chip_select(Usart *p_usart) +{ + p_usart->US_CR = US_CR_FCS; +} + +/** + * \brief Drive the slave select line NSS (RTS pin) to 1 in SPI master mode. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_spi_release_chip_select(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RCS; +} + +/** + * \brief Check if Transmit is Ready. + * Check if data have been loaded in USART_THR and are waiting to be loaded + * into the Transmit Shift Register (TSR). + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 No data is in the Transmit Holding Register. + * \retval 0 There is data in the Transmit Holding Register. + */ +uint32_t usart_is_tx_ready(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXRDY) > 0; +} + +/** + * \brief Check if Transmit Holding Register is empty. + * Check if the last data written in USART_THR have been loaded in TSR and the + * last data loaded in TSR have been transmitted. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmitter is empty. + * \retval 0 Transmitter is not empty. + */ +uint32_t usart_is_tx_empty(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0; +} + +/** + * \brief Check if the received data are ready. + * Check if Data have been received and loaded into USART_RHR. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Some data has been received. + * \retval 0 No data has been received. + */ +uint32_t usart_is_rx_ready(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_RXRDY) > 0; +} + +/** + * \brief Write to USART Transmit Holding Register. + * + * \note Before writing user should check if tx is ready (or empty). + * + * \param p_usart Pointer to a USART instance. + * \param c Data to be sent. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_write(Usart *p_usart, uint32_t c) +{ + if (!(p_usart->US_CSR & US_CSR_TXRDY)) { + return 1; + } + + p_usart->US_THR = US_THR_TXCHR(c); + return 0; +} + +/** + * \brief Write to USART Transmit Holding Register. + * + * \note Before writing user should check if tx is ready (or empty). + * + * \param p_usart Pointer to a USART instance. + * \param c Data to be sent. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_putchar(Usart *p_usart, uint32_t c) +{ + while (!(p_usart->US_CSR & US_CSR_TXRDY)) { + } + + p_usart->US_THR = US_THR_TXCHR(c); + + return 0; +} + +/** + * \brief Write one-line string through USART. + * + * \param p_usart Pointer to a USART instance. + * \param string Pointer to one-line string to be sent. + */ +void usart_write_line(Usart *p_usart, const char *string) +{ + while (*string != '\0') { + usart_putchar(p_usart, *string++); + } +} + +/** + * \brief Read from USART Receive Holding Register. + * + * \note Before reading user should check if rx is ready. + * + * \param p_usart Pointer to a USART instance. + * \param c Pointer where the one-byte received data will be stored. + * + * \retval 0 on success. + * \retval 1 if no data is available or errors. + */ +uint32_t usart_read(Usart *p_usart, uint32_t *c) +{ + if (!(p_usart->US_CSR & US_CSR_RXRDY)) { + return 1; + } + + /* Read character */ + *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; + + return 0; +} + +/** + * \brief Read from USART Receive Holding Register. + * Before reading user should check if rx is ready. + * + * \param p_usart Pointer to a USART instance. + * \param c Pointer where the one-byte received data will be stored. + * + * \retval 0 Data has been received. + * \retval 1 on failure. + */ +uint32_t usart_getchar(Usart *p_usart, uint32_t *c) +{ + /* Wait until it's not empty or timeout has reached. */ + while (!(p_usart->US_CSR & US_CSR_RXRDY)) { + } + + /* Read character */ + *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; + + return 0; +} + +#if (SAM3XA || SAM3U) +/** + * \brief Get Transmit address for DMA operation. + * + * \param p_usart Pointer to a USART instance. + * + * \return Transmit address for DMA access. + */ +uint32_t *usart_get_tx_access(Usart *p_usart) +{ + return (uint32_t *)&(p_usart->US_THR); +} + +/** + * \brief Get Receive address for DMA operation. + * + * \param p_usart Pointer to a USART instance. + * + * \return Receive address for DMA access. + */ +uint32_t *usart_get_rx_access(Usart *p_usart) +{ + return (uint32_t *)&(p_usart->US_RHR); +} +#endif + +#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Get USART PDC base address. + * + * \param p_usart Pointer to a UART instance. + * + * \return USART PDC registers base for PDC driver to access. + */ +Pdc *usart_get_pdc_base(Usart *p_usart) +{ + Pdc *p_pdc_base; + + p_pdc_base = (Pdc *)NULL; + +#ifdef PDC_USART + if (p_usart == USART) { + p_pdc_base = PDC_USART; + return p_pdc_base; + } +#endif +#ifdef PDC_USART0 + if (p_usart == USART0) { + p_pdc_base = PDC_USART0; + return p_pdc_base; + } +#endif +#ifdef PDC_USART1 + else if (p_usart == USART1) { + p_pdc_base = PDC_USART1; + return p_pdc_base; + } +#endif +#ifdef PDC_USART2 + else if (p_usart == USART2) { + p_pdc_base = PDC_USART2; + return p_pdc_base; + } +#endif +#ifdef PDC_USART3 + else if (p_usart == USART3) { + p_pdc_base = PDC_USART3; + return p_pdc_base; + } +#endif +#ifdef PDC_USART4 + else if (p_usart == USART4) { + p_pdc_base = PDC_USART4; + return p_pdc_base; + } +#endif +#ifdef PDC_USART5 + else if (p_usart == USART5) { + p_pdc_base = PDC_USART5; + return p_pdc_base; + } +#endif +#ifdef PDC_USART6 + else if (p_usart == USART6) { + p_pdc_base = PDC_USART6; + return p_pdc_base; + } +#endif +#ifdef PDC_USART7 + else if (p_usart == USART7) { + p_pdc_base = PDC_USART7; + return p_pdc_base; + } +#endif + + return p_pdc_base; +} +#endif + +/** + * \brief Enable write protect of USART registers. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_writeprotect(Usart *p_usart) +{ + p_usart->US_WPMR = US_WPMR_WPEN | US_WPMR_WPKEY_PASSWD; +} + +/** + * \brief Disable write protect of USART registers. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_writeprotect(Usart *p_usart) +{ + p_usart->US_WPMR = US_WPMR_WPKEY_PASSWD; +} + +/** + * \brief Get write protect status. + * + * \param p_usart Pointer to a USART instance. + * + * \return 0 if no write protect violation occurred, or 16-bit write protect + * violation source. + */ +uint32_t usart_get_writeprotect_status(Usart *p_usart) +{ + uint32_t reg_value; + + reg_value = p_usart->US_WPSR; + if (reg_value & US_WPSR_WPVS) { + return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos; + } else { + return 0; + } +} + +#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM) + +/** + * \brief Configure the transmitter preamble length when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len The transmitter preamble length, which should be 0 ~ 15. + */ +void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) | + US_MAN_TX_PL(uc_len); +} + +/** + * \brief Configure the transmitter preamble pattern when the Manchester + * encode/decode is enabled, which should be 0 ~ 3. + * + * \param p_usart Pointer to a USART instance. + * \param uc_pattern 0 if the preamble is composed of '1's; + * 1 if the preamble is composed of '0's; + * 2 if the preamble is composed of '01's; + * 3 if the preamble is composed of '10's. + */ +void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) | + (uc_pattern << US_MAN_TX_PP_Pos); +} + +/** + * \brief Configure the transmitter Manchester polarity when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_polarity Indicate the transmitter Manchester polarity, which + * should be 0 or 1. + */ +void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) | + (uc_polarity << 12); +} + +/** + * \brief Configure the detected receiver preamble length when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len The detected receiver preamble length, which should be 0 ~ 15. + */ +void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) | + US_MAN_RX_PL(uc_len); +} + +/** + * \brief Configure the detected receiver preamble pattern when the Manchester + * encode/decode is enabled, which should be 0 ~ 3. + * + * \param p_usart Pointer to a USART instance. + * \param uc_pattern 0 if the preamble is composed of '1's; + * 1 if the preamble is composed of '0's; + * 2 if the preamble is composed of '01's; + * 3 if the preamble is composed of '10's. + */ +void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) | + (uc_pattern << US_MAN_RX_PP_Pos); +} + +/** + * \brief Configure the receiver Manchester polarity when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_polarity Indicate the receiver Manchester polarity, which should + * be 0 or 1. + */ +void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) | + (uc_polarity << 28); +} + +/** + * \brief Enable drift compensation. + * + * \note The 16X clock mode must be enabled. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_man_enable_drift_compensation(Usart *p_usart) +{ + p_usart->US_MAN |= US_MAN_DRIFT; +} + +/** + * \brief Disable drift compensation. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_man_disable_drift_compensation(Usart *p_usart) +{ + p_usart->US_MAN &= ~US_MAN_DRIFT; +} + +#endif + +#if SAM4L + +uint32_t usart_get_version(Usart *p_usart) +{ + return p_usart->US_VERSION; +} + +#endif + +#if SAMG55 +/** + * \brief Set sleepwalking match mode. + * + * \param p_uart Pointer to a USART instance. + * \param ul_low_value First comparison value for received character. + * \param ul_high_value Second comparison value for received character. + * \param cmpmode ture for start condition, false for flag only. + * \param cmppar ture for parity check, false for no. + */ +void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value) +{ + Assert(ul_low_value <= ul_high_value); + + uint32_t temp = 0; + + if (cmpmode) { + temp |= US_CMPR_CMPMODE_START_CONDITION; + } + + if (cmppar) { + temp |= US_CMPR_CMPPAR; + } + + temp |= US_CMPR_VAL1(ul_low_value); + + temp |= US_CMPR_VAL2(ul_high_value); + + p_uart->US_CMPR= temp; +} +#endif + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/usart/usart.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/usart/usart.h new file mode 100644 index 00000000..8b205fde --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/drivers/usart/usart.h @@ -0,0 +1,773 @@ +/** + * \file + * + * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver + * for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef USART_H_INCLUDED +#define USART_H_INCLUDED + +#include "compiler.h" + +/** + * \defgroup group_sam_drivers_usart Universal Synchronous Asynchronous Receiver + * Transmitter (USART). + * + * See \ref sam_usart_quickstart. + * + * This is a low-level driver implementation for the SAM Universal + * Synchronous/Asynchronous Receiver/Transmitter. + * + * @{ + */ + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** Clock phase. */ +#define SPI_CPHA (1 << 0) + +/** Clock polarity. */ +#define SPI_CPOL (1 << 1) + +/** SPI mode definition. */ +#define SPI_MODE_0 0 +#define SPI_MODE_1 (SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL) +#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA) + +/**micro definition for LIN mode of SAMV71*/ +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +#ifndef US_MR_USART_MODE_LIN_MASTER +#define US_MR_USART_MODE_LIN_MASTER 0x0A +#endif +#ifndef US_MR_USART_MODE_LIN_SLAVE +#define US_MR_USART_MODE_LIN_SLAVE 0x0B +#endif +#endif +/* Input parameters when initializing RS232 and similar modes. */ +typedef struct { + /* Set baud rate of the USART (unused in slave modes). */ + uint32_t baudrate; + + /* + * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT, + * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or + * US_MR_MODE9. + */ + uint32_t char_length; + + /* + * Parity type, which should be one of the following: US_MR_PAR_EVEN, + * US_MR_PAR_ODD, US_MR_PAR_SPACE, US_MR_PAR_MARK, US_MR_PAR_NO + * or US_MR_PAR_MULTIDROP. + */ + uint32_t parity_type; + + /* + * Number of stop bits between two characters: US_MR_NBSTOP_1_BIT, + * US_MR_NBSTOP_1_5_BIT, US_MR_NBSTOP_2_BIT. + * \note US_MR_NBSTOP_1_5_BIT is supported in asynchronous modes only. + */ + uint32_t stop_bits; + + /* + * Run the channel in test mode, which should be one of following: + * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC, + * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK. + */ + uint32_t channel_mode; + + /* Filter of IrDA mode, useless in other modes. */ + uint32_t irda_filter; +} sam_usart_opt_t; + +/* Input parameters when initializing ISO7816 mode. */ +typedef struct { + /* Set the frequency of the ISO7816 clock. */ + uint32_t iso7816_hz; + + /* + * The number of ISO7816 clock ticks in every bit period (1 to 2047, + * 0 = disable clock). Baudrate rate = iso7816_hz / fidi_ratio. + */ + uint32_t fidi_ratio; + + /* + * How to calculate the parity bit: US_MR_PAR_EVEN for normal mode or + * US_MR_PAR_ODD for inverse mode. + */ + uint32_t parity_type; + + /* + * Inhibit Non Acknowledge: + * - 0: the NACK is generated; + * - 1: the NACK is not generated. + * + * \note This bit will be used only in ISO7816 mode, protocol T = 0 + * receiver. + */ + uint32_t inhibit_nack; + + /* + * Disable successive NACKs. + * - 0: NACK is sent on the ISO line as soon as a parity error occurs + * in the received character. Successive parity errors are counted up to + * the value in the max_iterations field. These parity errors generate + * a NACK on the ISO line. As soon as this value is reached, no additional + * NACK is sent on the ISO line. The ITERATION flag is asserted. + */ + uint32_t dis_suc_nack; + + /* Max number of repetitions (0 to 7). */ + uint32_t max_iterations; + + /* + * Bit order in transmitted characters: + * - 0: LSB first; + * - 1: MSB first. + */ + uint32_t bit_order; + + /* + * Which protocol is used: + * - 0: T = 0; + * - 1: T = 1. + */ + uint32_t protocol_type; +} usart_iso7816_opt_t; + +/* Input parameters when initializing SPI mode. */ +typedef struct { + /* Set the frequency of the SPI clock (unused in slave mode). */ + uint32_t baudrate; + + /* + * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT, + * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or + * US_MR_MODE9. + */ + uint32_t char_length; + + /* + * Which SPI mode to use, which should be one of the following: + * SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3. + */ + uint32_t spi_mode; + + /* + * Run the channel in test mode, which should be one of following: + * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC, + * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK. + */ + uint32_t channel_mode; +} usart_spi_opt_t; + +void usart_reset(Usart *p_usart); +uint32_t usart_set_async_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck); +uint32_t usart_init_rs232(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_hw_handshaking(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) +uint32_t usart_init_modem(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#endif +uint32_t usart_init_sync_master(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_sync_slave(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt); +uint32_t usart_init_rs485(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +uint32_t usart_init_irda(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#endif +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +uint32_t usart_init_iso7816(Usart *p_usart, + const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck); +void usart_reset_iterations(Usart *p_usart); +void usart_reset_nack(Usart *p_usart); +uint32_t usart_is_rx_buf_end(Usart *p_usart); +uint32_t usart_is_tx_buf_end(Usart *p_usart); +uint32_t usart_is_rx_buf_full(Usart *p_usart); +uint32_t usart_is_tx_buf_empty(Usart *p_usart); +uint8_t usart_get_error_number(Usart *p_usart); +#endif +uint32_t usart_init_spi_master(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_spi_slave(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt); +#if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t usart_init_lin_master(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck); +uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck); +void usart_lin_abort_tx(Usart *p_usart); +void usart_lin_send_wakeup_signal(Usart *p_usart); +void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action); +void usart_lin_disable_parity(Usart *p_usart); +void usart_lin_enable_parity(Usart *p_usart); +void usart_lin_disable_checksum(Usart *p_usart); +void usart_lin_enable_checksum(Usart *p_usart); +void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type); +void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode); +void usart_lin_disable_frame_slot(Usart *p_usart); +void usart_lin_enable_frame_slot(Usart *p_usart); +void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type); +void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len); +void usart_lin_disable_pdc_mode(Usart *p_usart); +void usart_lin_enable_pdc_mode(Usart *p_usart); +void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id); +uint8_t usart_lin_read_identifier(Usart *p_usart); +uint8_t usart_lin_get_data_length(Usart *usart); +#endif +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +uint8_t usart_lin_identifier_send_complete(Usart *usart); +uint8_t usart_lin_identifier_reception_complete(Usart *usart); +uint8_t usart_lin_tx_complete(Usart *usart); +uint32_t usart_init_lon(Usart *p_usart, uint32_t ul_baudrate, uint32_t ul_mck); +void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type); +void usart_lon_disable_coll_detection(Usart *p_usart); +void usart_lon_enable_coll_detection(Usart *p_usart); +void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type); +void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type); +void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type); +void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len); +void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len); +void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps); +void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time); +void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time); +void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len); +void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len); +void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb); +uint32_t usart_lon_is_tx_end(Usart *p_usart); +uint32_t usart_lon_is_rx_end(Usart *p_usart); +#endif +void usart_enable_tx(Usart *p_usart); +void usart_disable_tx(Usart *p_usart); +void usart_reset_tx(Usart *p_usart); +void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard); +void usart_enable_rx(Usart *p_usart); +void usart_disable_rx(Usart *p_usart); +void usart_reset_rx(Usart *p_usart); +void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout); +void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources); +void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources); +uint32_t usart_get_interrupt_mask(Usart *p_usart); +uint32_t usart_get_status(Usart *p_usart); +void usart_reset_status(Usart *p_usart); +void usart_start_tx_break(Usart *p_usart); +void usart_stop_tx_break(Usart *p_usart); +void usart_start_rx_timeout(Usart *p_usart); +uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr); +void usart_restart_rx_timeout(Usart *p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) +void usart_drive_DTR_pin_low(Usart *p_usart); +void usart_drive_DTR_pin_high(Usart *p_usart); +#endif +void usart_drive_RTS_pin_low(Usart *p_usart); +void usart_drive_RTS_pin_high(Usart *p_usart); +void usart_spi_force_chip_select(Usart *p_usart); +void usart_spi_release_chip_select(Usart *p_usart); +uint32_t usart_is_tx_ready(Usart *p_usart); +uint32_t usart_is_tx_empty(Usart *p_usart); +uint32_t usart_is_rx_ready(Usart *p_usart); +uint32_t usart_write(Usart *p_usart, uint32_t c); +uint32_t usart_putchar(Usart *p_usart, uint32_t c); +void usart_write_line(Usart *p_usart, const char *string); +uint32_t usart_read(Usart *p_usart, uint32_t *c); +uint32_t usart_getchar(Usart *p_usart, uint32_t *c); +#if (SAM3XA || SAM3U) +uint32_t *usart_get_tx_access(Usart *p_usart); +uint32_t *usart_get_rx_access(Usart *p_usart); +#endif +#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +Pdc *usart_get_pdc_base(Usart *p_usart); +#endif +void usart_enable_writeprotect(Usart *p_usart); +void usart_disable_writeprotect(Usart *p_usart); +uint32_t usart_get_writeprotect_status(Usart *p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM || SAMV70 || SAMV71 || SAMS70 || SAME70) +void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len); +void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern); +void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity); +void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len); +void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern); +void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity); +void usart_man_enable_drift_compensation(Usart *p_usart); +void usart_man_disable_drift_compensation(Usart *p_usart); +#endif + +#if SAM4L +uint32_t usart_get_version(Usart *p_usart); +#endif + +#if SAMG55 +void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value); +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +//! @} + +/** + * \page sam_usart_quickstart Quick start guide for the SAM USART module + * + * This is the quick start guide for the \ref group_sam_drivers_usart + * "USART module", with step-by-step instructions on how to configure and + * use the driver in a selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \note Some SAM devices contain both USART and UART modules, with the latter + * being a subset in functionality of the former but physically separate + * peripherals. UART modules are compatible with the USART driver, but + * only for the functions and modes supported by the base UART driver. + * + * \section usart_use_cases USART use cases + * - \ref usart_basic_use_case + * - \subpage usart_use_case_1 + * - \subpage usart_use_case_2 + * + * \note The USART pins configuration are not included here. Please refer + * the related code in board_init() function. + * + * \section usart_basic_use_case Basic use case - transmit a character + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * \section usart_basic_use_case_setup Setup steps + * + * \subsection usart_basic_use_case_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref ioport_group "Common IOPORT API (ioport)" + * + * \subsection usart_basic_use_case_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.) + * \code + #define USART_SERIAL USART0 + #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + board_init(); + + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \subsection usart_basic_use_case_setup_flow Workflow + * -# Initialize system clock: + * \code + sysclk_init(); +\endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + board_init(); +\endcode + * \note Set the following define in conf_board.h file to enable COM port,it will be used in + * board_init() function to set up IOPorts for the USART pins. + * For SAM4L: + * \code + #define CONF_BOARD_COM_PORT +\endcode + * For other SAM devices: + * \code + #define CONF_BOARD_UART_CONSOLE +\endcode + * -# Create USART options struct: + * \code + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; +\endcode + * -# Enable the clock to the USART module: + * \code + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif +\endcode + * -# Initialize the USART module in RS232 mode: + * \code + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); +\endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \section usart_basic_use_case_usage Usage steps + * + * \subsection usart_basic_use_case_usage_code Example code + * Add to application C-file: + * \code + usart_putchar(USART_SERIAL, 'a'); +\endcode + * + * \subsection usart_basic_use_case_usage_flow Workflow + * -# Send an 'a' character via USART + * \code usart_putchar(USART_SERIAL, 'a'); \endcode + */ + +/** + * \page usart_use_case_1 USART receive character and echo back + * + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case waits for a received character on the configured USART and + * echoes the character back to the same USART. + * + * \section usart_use_case_1_setup Setup steps + * + * \subsection usart_use_case_1_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref ioport_group "Common IOPORT API (ioport)" + * + * \subsection usart_use_case_1_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.): + * \code + #define USART_SERIAL USART0 + #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT +\endcode + * + * A variable for the received byte must be added: + * \code + uint32_t received_byte; +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + board_init(); + + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; + + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif + + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \subsection usart_use_case_1_setup_flow Workflow + * -# Initialize system clock: + * \code + sysclk_init(); +\endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + board_init(); +\endcode + * \note Set the following define in conf_board.h file to enable COM port,it will be used in + * board_init() function to set up IOPorts for the USART pins. + * For SAM4L: + * \code + #define CONF_BOARD_COM_PORT +\endcode + * For other SAM devices: + * \code + #define CONF_BOARD_UART_CONSOLE +\endcode + * -# Create USART options struct: + * \code + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; +\endcode + * -# Enable the clock to the USART module: + * \code + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif +\endcode + * -# Initialize the USART module in RS232 mode: + * \code + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); +\endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \section usart_use_case_1_usage Usage steps + * + * \subsection usart_use_case_1_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + received_byte = usart_getchar(USART_SERIAL); + usart_putchar(USART_SERIAL, received_byte); +\endcode + * + * \subsection usart_use_case_1_usage_flow Workflow + * -# Wait for reception of a character: + * \code usart_getchar(USART_SERIAL, &received_byte); \endcode + * -# Echo the character back: + * \code usart_putchar(USART_SERIAL, received_byte); \endcode + */ + +/** + * \page usart_use_case_2 USART receive character and echo back via interrupts + * + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case waits for a received character on the configured USART and + * echoes the character back to the same USART. The character reception is + * performed via an interrupt handler, rather than the polling method used + * in \ref usart_use_case_1. + * + * \section usart_use_case_2_setup Setup steps + * + * \subsection usart_use_case_2_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref pio_group "Parallel Input/Output Controller (pio)" + * -# \ref pmc_group "Power Management Controller (pmc)" + * + * \subsection usart_use_case_2_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.): + * \code + #define USART_SERIAL USART0 + #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + #define USART_SERIAL_ISR_HANDLER USART0_Handler + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT +\endcode + * + * A variable for the received byte must be added: + * \code + uint32_t received_byte; +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + board_init(); + + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; + + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif + + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); + + usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY); + NVIC_EnableIRQ(USART_SERIAL_IRQ); +\endcode + * + * \subsection usart_use_case_2_setup_flow Workflow + * -# Initialize system clock: + * \code + sysclk_init(); +\endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + board_init(); +\endcode + * \note Set the following define in conf_board.h file to enable COM port,it will be used in + * board_init() function to set up IOPorts for the USART pins. + * For SAM4L: + * \code + #define CONF_BOARD_COM_PORT +\endcode + * For other SAM devices: + * \code + #define CONF_BOARD_UART_CONSOLE +\endcode + * -# Create USART options struct: + * \code + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; +\endcode + * -# Enable the clock to the USART module: + * \code + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif +\endcode + * -# Initialize the USART module in RS232 mode: + * \code + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); +\endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * -# Enable the USART character reception interrupt, and general interrupts + * for the USART module. + * \code + usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY); + NVIC_EnableIRQ(USART_SERIAL_IRQ); +\endcode + * \section usart_use_case_2_usage Usage steps + * + * \subsection usart_use_case_2_usage_code Example code + * Add to your main application C-file the USART interrupt handler: + * \code + void USART_SERIAL_ISR_HANDLER(void) + { + uint32_t dw_status = usart_get_status(USART_SERIAL); + + if (dw_status & US_CSR_RXRDY) { + uint32_t received_byte; + + usart_read(USART_SERIAL, &received_byte); + usart_write(USART_SERIAL, received_byte); + } + } +\endcode + * + * \subsection usart_use_case_2_usage_flow Workflow + * -# When the USART ISR fires, retrieve the USART module interrupt flags: + * \code uint32_t dw_status = usart_get_status(USART_SERIAL); \endcode + * -# Check if the USART Receive Character interrupt has fired: + * \code if (dw_status & US_CSR_RXRDY) \endcode + * -# If a character has been received, fetch it into a temporary variable: + * \code usart_read(USART_SERIAL, &received_byte); \endcode + * -# Echo the character back: + * \code usart_write(USART_SERIAL, received_byte); \endcode + */ + +#endif /* USART_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/acc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/acc.h new file mode 100644 index 00000000..741aacfe --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/acc.h @@ -0,0 +1,141 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ACC_COMPONENT_ +#define _SAME70_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t ACC_VER; /**< \brief (Acc Offset: 0xFC) Version Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */ +#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))) +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_ADVREFP (0x1u << 0) /**< \brief (ACC_MR) Select ADVREFP */ +#define ACC_MR_SELMINUS_VREFP (0x1u << 0) /**< \brief (ACC_MR) Select VREFP */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */ +#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))) +#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */ +#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))) +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */ +#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */ +/* -------- ACC_VER : (ACC Offset: 0xFC) Version Register -------- */ +#define ACC_VER_VERSION_Pos 0 +#define ACC_VER_VERSION_Msk (0xfffu << ACC_VER_VERSION_Pos) /**< \brief (ACC_VER) Version of the Hardware Module */ +#define ACC_VER_MFN_Pos 16 +#define ACC_VER_MFN_Msk (0x7u << ACC_VER_MFN_Pos) /**< \brief (ACC_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_ACC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/aes.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/aes.h new file mode 100644 index 00000000..5a53659e --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/aes.h @@ -0,0 +1,203 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_AES_COMPONENT_ +#define _SAME70_AES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAME70_AES Advanced Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aes hardware registers */ +typedef struct { + __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ + __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */ + __I uint32_t Reserved2[20]; + __I uint32_t AES_VERSION; /**< \brief (Aes Offset: 0xFC) Version Register */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ +#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ +#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ +#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ +#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ +#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */ +#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */ +#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */ +#define AES_MR_PROCDLY_Pos 4 +#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ +#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) +#define AES_MR_SMOD_Pos 8 +#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ +#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))) +#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_KEYSIZE_Pos 10 +#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ +#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))) +#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_OPMOD_Pos 12 +#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ +#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))) +#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ +#define AES_MR_CFBS_Pos 16 +#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ +#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))) +#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ +#define AES_MR_CKEY_Pos 20 +#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Key */ +#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))) +#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ +#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */ +#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled. */ +#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled. */ +#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */ +#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled. */ +#define AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled. */ +#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */ +#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled. */ +#define AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled. */ +#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */ +#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled. */ +#define AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled. */ +#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */ +#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled. */ +#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled. */ +#define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) Countermeasure Type 6 */ +#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled. */ +#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ +#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ +#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ +#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ +#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ +#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ +#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */ +/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ +#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_Pos 12 +#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ +#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */ +/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos 0 +#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ +#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) +/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos 0 +#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ +#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) +/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos 0 +#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ +/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos 0 +#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ +#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) +/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos 0 +#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */ +#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))) +/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos 0 +#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */ +#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))) +/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos 0 +#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */ +#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))) +/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos 0 +#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */ +/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos 0 +#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */ +/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */ +#define AES_GCMHR_H_Pos 0 +#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */ +#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))) +/* -------- AES_VERSION : (AES Offset: 0xFC) Version Register -------- */ +#define AES_VERSION_VERSION_Pos 0 +#define AES_VERSION_VERSION_Msk (0xfffu << AES_VERSION_VERSION_Pos) /**< \brief (AES_VERSION) Version of the Hardware Module */ +#define AES_VERSION_MFN_Pos 16 +#define AES_VERSION_MFN_Msk (0x7u << AES_VERSION_MFN_Pos) /**< \brief (AES_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_AES_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/afec.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/afec.h new file mode 100644 index 00000000..4159447d --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/afec.h @@ -0,0 +1,495 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_AFEC_COMPONENT_ +#define _SAME70_AFEC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_AFEC Analog Front-End Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Afec hardware registers */ +typedef struct { + __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */ + __I uint32_t Reserved1[6]; + __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */ + __I uint32_t Reserved5[11]; + __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */ + __I uint32_t Reserved7[4]; + __I uint32_t AFEC_VERSION; /**< \brief (Afec Offset: 0xFC) AFEC Version Register */ +} Afec; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */ +#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */ +#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */ +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */ +#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGSEL_Pos 1 +#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))) +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */ +#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */ +#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */ +#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */ +#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_PRESCAL_Pos 8 +#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */ +#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) +#define AFEC_MR_STARTUP_Pos 16 +#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */ +#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))) +#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */ +#define AFEC_MR_TRACKTIM_Pos 24 +#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */ +#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) +#define AFEC_MR_TRANSFER_Pos 28 +#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */ +#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) +#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */ +#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos 0 +#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */ +#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))) +#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPSEL_Pos 3 +#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */ +#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) +#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPFILTER_Pos 12 +#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */ +#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) +#define AFEC_EMR_RES_Pos 16 +#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */ +#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))) +#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */ +#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_SIGNMODE_Pos 28 +#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */ +#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */ +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos 0 +#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */ +#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) +#define AFEC_SEQ1R_USCH1_Pos 4 +#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */ +#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) +#define AFEC_SEQ1R_USCH2_Pos 8 +#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */ +#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) +#define AFEC_SEQ1R_USCH3_Pos 12 +#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */ +#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) +#define AFEC_SEQ1R_USCH4_Pos 16 +#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */ +#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) +#define AFEC_SEQ1R_USCH5_Pos 20 +#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */ +#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) +#define AFEC_SEQ1R_USCH6_Pos 24 +#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */ +#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) +#define AFEC_SEQ1R_USCH7_Pos 28 +#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */ +#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos 0 +#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */ +#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) +#define AFEC_SEQ2R_USCH9_Pos 4 +#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */ +#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) +#define AFEC_SEQ2R_USCH10_Pos 8 +#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */ +#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) +#define AFEC_SEQ2R_USCH11_Pos 12 +#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */ +#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) +#define AFEC_SEQ2R_USCH12_Pos 16 +#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */ +#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) +#define AFEC_SEQ2R_USCH13_Pos 20 +#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */ +#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) +#define AFEC_SEQ2R_USCH14_Pos 24 +#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */ +#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) +#define AFEC_SEQ2R_USCH15_Pos 28 +#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */ +#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) +/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */ +#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */ +#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */ +#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */ +#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */ +#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */ +#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */ +#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */ +#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */ +#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */ +#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */ +#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */ +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */ +#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */ +#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */ +#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */ +#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */ +#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */ +#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */ +#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */ +#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */ +#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */ +#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */ +#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */ +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */ +#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */ +#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */ +#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */ +#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */ +#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */ +#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */ +#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */ +#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */ +#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */ +#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */ +#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */ +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos 0 +#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */ +#define AFEC_LCDR_CHNB_Pos 24 +#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */ +/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */ +#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */ +#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */ +#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */ +#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */ +#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */ +#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */ +#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */ +#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */ +#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */ +#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */ +#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */ +#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */ +#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */ +#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */ +#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */ +/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */ +#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */ +#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */ +#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */ +#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */ +#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */ +#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */ +#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */ +#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */ +#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */ +#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */ +#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */ +#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */ +#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */ +#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */ +#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */ +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */ +#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */ +#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */ +#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */ +#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */ +#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */ +#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */ +#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */ +#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */ +#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */ +#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */ +#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */ +#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */ +#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */ +#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */ +#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */ +/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */ +#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */ +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */ +#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */ +#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */ +#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */ +#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */ +#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */ +#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */ +#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */ +#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */ +#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */ +#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */ +#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */ +/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos 0 +#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */ +#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) +#define AFEC_CWR_HIGHTHRES_Pos 16 +#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */ +#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) +/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos 0 +#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */ +#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) +#define AFEC_CGR_GAIN1_Pos 2 +#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */ +#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) +#define AFEC_CGR_GAIN2_Pos 4 +#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */ +#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) +#define AFEC_CGR_GAIN3_Pos 6 +#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */ +#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) +#define AFEC_CGR_GAIN4_Pos 8 +#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */ +#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) +#define AFEC_CGR_GAIN5_Pos 10 +#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */ +#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) +#define AFEC_CGR_GAIN6_Pos 12 +#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */ +#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) +#define AFEC_CGR_GAIN7_Pos 14 +#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */ +#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) +#define AFEC_CGR_GAIN8_Pos 16 +#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */ +#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) +#define AFEC_CGR_GAIN9_Pos 18 +#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */ +#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) +#define AFEC_CGR_GAIN10_Pos 20 +#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */ +#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) +#define AFEC_CGR_GAIN11_Pos 22 +#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */ +#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */ +#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */ +#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */ +#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */ +#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */ +#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */ +#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */ +#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */ +#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */ +#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */ +#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */ +#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */ +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos 0 +#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */ +#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) +/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos 0 +#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */ +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos 0 +#define AFEC_COCR_AOFF_Msk (0xfffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */ +#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 +#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */ +#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) +#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 +#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */ +#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) +/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */ +#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */ +#define AFEC_ACR_IBCTL_Pos 8 +#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */ +#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */ +#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */ +#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */ +#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */ +#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */ +#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */ +#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */ +#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */ +#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */ +#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */ +#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */ +#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */ +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */ +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos 0 +#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */ +#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))) +#define AFEC_CVR_GAINCORR_Pos 16 +#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */ +#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))) +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */ +#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */ +#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */ +#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */ +#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */ +#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */ +#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */ +#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */ +#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */ +#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */ +#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */ +#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */ +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */ +#define AFEC_WPMR_WPKEY_Pos 8 +#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */ +#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))) +#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */ +#define AFEC_WPSR_WPVSRC_Pos 8 +#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */ +/* -------- AFEC_VERSION : (AFEC Offset: 0xFC) AFEC Version Register -------- */ +#define AFEC_VERSION_VERSION_Pos 0 +#define AFEC_VERSION_VERSION_Msk (0xfffu << AFEC_VERSION_VERSION_Pos) /**< \brief (AFEC_VERSION) Version of the Hardware Module */ +#define AFEC_VERSION_MFN_Pos 16 +#define AFEC_VERSION_MFN_Msk (0x7u << AFEC_VERSION_MFN_Pos) /**< \brief (AFEC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_AFEC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/chipid.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/chipid.h new file mode 100644 index 00000000..3ba65d34 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/chipid.h @@ -0,0 +1,128 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_CHIPID_COMPONENT_ +#define _SAME70_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAME70_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAME70_CHIPID_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/dacc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/dacc.h new file mode 100644 index 00000000..899126fc --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/dacc.h @@ -0,0 +1,217 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_DACC_COMPONENT_ +#define _SAME70_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */ + __I uint32_t Reserved1[1]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t DACC_VERSION; /**< \brief (Dacc Offset: 0xFC) Version Register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */ +#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) Triggered by selected event */ +#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode enabled */ +#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */ +#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) Triggered by selected event */ +#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode enabled */ +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */ +#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC */ +#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces number of requests to DMA and the number of system bus accesses) */ +#define DACC_MR_ZERO (0x1u << 5) /**< \brief (DACC_MR) Must always be written to 0. */ +#define DACC_MR_REFRESH_Pos 8 +#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */ +#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos))) +#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */ +#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 outputs can be separately configured */ +#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN outputs are configured by the channel 0 value. */ +#define DACC_MR_PRESCALER_Pos 24 +#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */ +#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))) +/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */ +#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */ +#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */ +#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */ +#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGSEL0_Pos 4 +#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */ +#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))) +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) DATRG */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL7 (0x7u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL1_Pos 8 +#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */ +#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))) +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) DATRG */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL7 (0x7u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_OSR0_Pos 16 +#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */ +#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))) +#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_Pos 20 +#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */ +#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))) +#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC ready flag */ +#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC ready flag */ +/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */ +#define DACC_CDR_DATA0_Pos 0 +#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */ +#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))) +#define DACC_CDR_DATA1_Pos 16 +#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */ +#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */ +#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */ +#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */ +#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */ +#define DACC_IER_ENDTX0 (0x1u << 8) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 0 */ +#define DACC_IER_ENDTX1 (0x1u << 9) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 1 */ +#define DACC_IER_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 0 */ +#define DACC_IER_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 1 */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */ +#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */ +#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */ +#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */ +#define DACC_IDR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 0 */ +#define DACC_IDR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 1 */ +#define DACC_IDR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 0 */ +#define DACC_IDR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 1 */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */ +#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */ +#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */ +#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */ +#define DACC_IMR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 0 */ +#define DACC_IMR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 1 */ +#define DACC_IMR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 0 */ +#define DACC_IMR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 1 */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */ +#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */ +#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */ +#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */ +#define DACC_ISR_ENDTX0 (0x1u << 8) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 0 */ +#define DACC_ISR_ENDTX1 (0x1u << 9) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 1 */ +#define DACC_ISR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 0 */ +#define DACC_ISR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 1 */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status register -------- */ +#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ +#define DACC_WPSR_WPVSRC_Pos 8 +#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ +/* -------- DACC_VERSION : (DACC Offset: 0xFC) Version Register -------- */ +#define DACC_VERSION_VERSION_Pos 0 +#define DACC_VERSION_VERSION_Msk (0xfffu << DACC_VERSION_VERSION_Pos) /**< \brief (DACC_VERSION) Version */ +#define DACC_VERSION_MFN_Pos 16 +#define DACC_VERSION_MFN_Msk (0x7u << DACC_VERSION_MFN_Pos) /**< \brief (DACC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_DACC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/efc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/efc.h new file mode 100644 index 00000000..34b7c70d --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/efc.h @@ -0,0 +1,123 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_EFC_COMPONENT_ +#define _SAME70_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ + __I uint32_t Reserved1[1]; + __I uint32_t EEFC_VERSION; /**< \brief (Efc Offset: 0x14) EEFC Version Register */ + __I uint32_t Reserved2[51]; + __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */ +#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */ +#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ +/* -------- EEFC_VERSION : (EFC Offset: 0x14) EEFC Version Register -------- */ +#define EEFC_VERSION_VERSION_Pos 0 +#define EEFC_VERSION_VERSION_Msk (0xfffu << EEFC_VERSION_VERSION_Pos) /**< \brief (EEFC_VERSION) Version of the Hardware Module */ +#define EEFC_VERSION_MFN_Pos 16 +#define EEFC_VERSION_MFN_Msk (0x7u << EEFC_VERSION_MFN_Pos) /**< \brief (EEFC_VERSION) Metal Fix Number */ +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */ +#define EEFC_WPMR_WPKEY_Pos 8 +#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */ +#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))) +#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_EFC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/gmac.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/gmac.h new file mode 100644 index 00000000..7da341a0 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/gmac.h @@ -0,0 +1,1307 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_GMAC_COMPONENT_ +#define _SAME70_GMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ +/* ============================================================================= */ +/** \addtogroup SAME70_GMAC Gigabit Ethernet MAC */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GmacSa hardware registers */ +typedef struct { + __IO uint32_t GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top Register */ +} GmacSa; +/** \brief Gmac hardware registers */ +#define GMACSA_NUMBER 4 +typedef struct { + __IO uint32_t GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ + __IO uint32_t GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ + __I uint32_t GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ + __IO uint32_t GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ + __IO uint32_t GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ + __IO uint32_t GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ + __IO uint32_t GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address Register */ + __IO uint32_t GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register */ + __IO uint32_t GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ + __I uint32_t GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ + __O uint32_t GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ + __O uint32_t GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ + __IO uint32_t GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ + __IO uint32_t GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ + __I uint32_t GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ + __IO uint32_t GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ + __IO uint32_t GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */ + __IO uint32_t GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */ + __IO uint32_t GMAC_RJFML; /**< \brief (Gmac Offset: 0x048) RX Jumbo Frame Max Length Register */ + __I uint32_t Reserved1[13]; + __IO uint32_t GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom */ + __IO uint32_t GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top */ + GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ + __IO uint32_t GMAC_TIDM1; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ + __IO uint32_t GMAC_TIDM2; /**< \brief (Gmac Offset: 0x0AC) Type ID Match 2 Register */ + __IO uint32_t GMAC_TIDM3; /**< \brief (Gmac Offset: 0x0B0) Type ID Match 3 Register */ + __IO uint32_t GMAC_TIDM4; /**< \brief (Gmac Offset: 0x0B4) Type ID Match 4 Register */ + __IO uint32_t GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */ + __IO uint32_t GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ + __IO uint32_t GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ + __IO uint32_t GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ + __IO uint32_t GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register */ + __IO uint32_t GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t GMAC_NSC; /**< \brief (Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register */ + __IO uint32_t GMAC_SCL; /**< \brief (Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register */ + __IO uint32_t GMAC_SCH; /**< \brief (Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register */ + __I uint32_t GMAC_EFTSH; /**< \brief (Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_EFRSH; /**< \brief (Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register */ + __I uint32_t GMAC_PEFTSH; /**< \brief (Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_PEFRSH; /**< \brief (Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register */ + __I uint32_t Reserved3[1]; + __I uint32_t GMAC_MID; /**< \brief (Gmac Offset: 0x0FC) Module ID Register */ + __I uint32_t GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted Low Register */ + __I uint32_t GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted High Register */ + __I uint32_t GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ + __I uint32_t GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ + __I uint32_t GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ + __I uint32_t GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ + __I uint32_t GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Underruns Register */ + __I uint32_t GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ + __I uint32_t GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ + __I uint32_t GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ + __I uint32_t GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ + __I uint32_t GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ + __I uint32_t GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */ + __I uint32_t GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received Low Received Register */ + __I uint32_t GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received High Received Register */ + __I uint32_t GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ + __I uint32_t GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ + __I uint32_t GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ + __I uint32_t GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ + __I uint32_t GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ + __I uint32_t GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ + __I uint32_t GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ + __I uint32_t GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ + __I uint32_t GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ + __I uint32_t GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ + __I uint32_t GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ + __I uint32_t GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ + __I uint32_t GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ + __I uint32_t GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ + __I uint32_t GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ + __I uint32_t GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ + __I uint32_t GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ + __I uint32_t GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t GMAC_TISUBN; /**< \brief (Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */ + __IO uint32_t GMAC_TSH; /**< \brief (Gmac Offset: 0x1C0) 1588 Timer Seconds High Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t GMAC_TSL; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register */ + __IO uint32_t GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ + __O uint32_t GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ + __IO uint32_t GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ + __I uint32_t GMAC_EFTSL; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_EFRSL; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */ + __I uint32_t GMAC_PEFTSL; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_PEFRSL; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint32_t Reserved6[28]; + __I uint32_t GMAC_RXLPI; /**< \brief (Gmac Offset: 0x270) Received LPI Transitions */ + __I uint32_t GMAC_RXLPITIME; /**< \brief (Gmac Offset: 0x274) Received LPI Time */ + __I uint32_t GMAC_TXLPI; /**< \brief (Gmac Offset: 0x278) Transmit LPI Transitions */ + __I uint32_t GMAC_TXLPITIME; /**< \brief (Gmac Offset: 0x27C) Transmit LPI Time */ + __I uint32_t Reserved7[96]; + __I uint32_t GMAC_ISRPQ[5]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) */ + __I uint32_t Reserved8[11]; + __IO uint32_t GMAC_TBQBAPQ[5]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved9[11]; + __IO uint32_t GMAC_RBQBAPQ[5]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved10[3]; + __IO uint32_t GMAC_RBSRPQ[5]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) */ + __I uint32_t Reserved11[2]; + __IO uint32_t GMAC_CBSCR; /**< \brief (Gmac Offset: 0x4BC) Credit-Based Shaping Control Register */ + __IO uint32_t GMAC_CBSISQA; /**< \brief (Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO uint32_t GMAC_CBSISQB; /**< \brief (Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint32_t Reserved12[14]; + __IO uint32_t GMAC_ST1RPQ[4]; /**< \brief (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) */ + __I uint32_t Reserved13[12]; + __IO uint32_t GMAC_ST2RPQ[8]; /**< \brief (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) */ + __I uint32_t Reserved14[39]; + __O uint32_t GMAC_IERPQ[5]; /**< \brief (Gmac Offset: 0x5FC) Interrupt Enable Register Priority Queue (index = 1) */ + __I uint32_t Reserved15[3]; + __O uint32_t GMAC_IDRPQ[5]; /**< \brief (Gmac Offset: 0x61C) Interrupt Disable Register Priority Queue (index = 1) */ + __I uint32_t Reserved16[3]; + __IO uint32_t GMAC_IMRPQ[5]; /**< \brief (Gmac Offset: 0x63C) Interrupt Mask Register Priority Queue (index = 1) */ + __I uint32_t Reserved17[36]; + __IO uint32_t GMAC_ST2ER[4]; /**< \brief (Gmac Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) */ + __I uint32_t Reserved18[4]; + __IO uint32_t GMAC_ST2CW00; /**< \brief (Gmac Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) */ + __IO uint32_t GMAC_ST2CW10; /**< \brief (Gmac Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) */ + __IO uint32_t GMAC_ST2CW01; /**< \brief (Gmac Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) */ + __IO uint32_t GMAC_ST2CW11; /**< \brief (Gmac Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) */ + __IO uint32_t GMAC_ST2CW02; /**< \brief (Gmac Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) */ + __IO uint32_t GMAC_ST2CW12; /**< \brief (Gmac Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) */ + __IO uint32_t GMAC_ST2CW03; /**< \brief (Gmac Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) */ + __IO uint32_t GMAC_ST2CW13; /**< \brief (Gmac Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) */ + __IO uint32_t GMAC_ST2CW04; /**< \brief (Gmac Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) */ + __IO uint32_t GMAC_ST2CW14; /**< \brief (Gmac Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) */ + __IO uint32_t GMAC_ST2CW05; /**< \brief (Gmac Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) */ + __IO uint32_t GMAC_ST2CW15; /**< \brief (Gmac Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) */ + __IO uint32_t GMAC_ST2CW06; /**< \brief (Gmac Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) */ + __IO uint32_t GMAC_ST2CW16; /**< \brief (Gmac Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) */ + __IO uint32_t GMAC_ST2CW07; /**< \brief (Gmac Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) */ + __IO uint32_t GMAC_ST2CW17; /**< \brief (Gmac Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) */ + __IO uint32_t GMAC_ST2CW08; /**< \brief (Gmac Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) */ + __IO uint32_t GMAC_ST2CW18; /**< \brief (Gmac Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) */ + __IO uint32_t GMAC_ST2CW09; /**< \brief (Gmac Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) */ + __IO uint32_t GMAC_ST2CW19; /**< \brief (Gmac Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) */ + __IO uint32_t GMAC_ST2CW010; /**< \brief (Gmac Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) */ + __IO uint32_t GMAC_ST2CW110; /**< \brief (Gmac Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) */ + __IO uint32_t GMAC_ST2CW011; /**< \brief (Gmac Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) */ + __IO uint32_t GMAC_ST2CW111; /**< \brief (Gmac Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) */ + __IO uint32_t GMAC_ST2CW012; /**< \brief (Gmac Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) */ + __IO uint32_t GMAC_ST2CW112; /**< \brief (Gmac Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) */ + __IO uint32_t GMAC_ST2CW013; /**< \brief (Gmac Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) */ + __IO uint32_t GMAC_ST2CW113; /**< \brief (Gmac Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) */ + __IO uint32_t GMAC_ST2CW014; /**< \brief (Gmac Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) */ + __IO uint32_t GMAC_ST2CW114; /**< \brief (Gmac Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) */ + __IO uint32_t GMAC_ST2CW015; /**< \brief (Gmac Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) */ + __IO uint32_t GMAC_ST2CW115; /**< \brief (Gmac Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) */ + __IO uint32_t GMAC_ST2CW016; /**< \brief (Gmac Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) */ + __IO uint32_t GMAC_ST2CW116; /**< \brief (Gmac Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) */ + __IO uint32_t GMAC_ST2CW017; /**< \brief (Gmac Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) */ + __IO uint32_t GMAC_ST2CW117; /**< \brief (Gmac Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) */ + __IO uint32_t GMAC_ST2CW018; /**< \brief (Gmac Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) */ + __IO uint32_t GMAC_ST2CW118; /**< \brief (Gmac Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) */ + __IO uint32_t GMAC_ST2CW019; /**< \brief (Gmac Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) */ + __IO uint32_t GMAC_ST2CW119; /**< \brief (Gmac Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) */ + __IO uint32_t GMAC_ST2CW020; /**< \brief (Gmac Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) */ + __IO uint32_t GMAC_ST2CW120; /**< \brief (Gmac Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) */ + __IO uint32_t GMAC_ST2CW021; /**< \brief (Gmac Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) */ + __IO uint32_t GMAC_ST2CW121; /**< \brief (Gmac Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) */ + __IO uint32_t GMAC_ST2CW022; /**< \brief (Gmac Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) */ + __IO uint32_t GMAC_ST2CW122; /**< \brief (Gmac Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) */ + __IO uint32_t GMAC_ST2CW023; /**< \brief (Gmac Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) */ + __IO uint32_t GMAC_ST2CW123; /**< \brief (Gmac Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) */ +} Gmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ +#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */ +#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */ +#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */ +#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */ +#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */ +#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */ +#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ +#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */ +#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */ +#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */ +#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */ +#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ +#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ +#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ +#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ +#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */ +/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */ +#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */ +#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ +#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ +#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */ +#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */ +#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ +#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ +#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ +#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */ +#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */ +#define GMAC_NCFGR_RXBUFO_Pos 14 +#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ +#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) +#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ +#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */ +#define GMAC_NCFGR_CLK_Pos 18 +#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */ +#define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))) +#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ +#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_DBW_Pos 21 +#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */ +#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))) +#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ +#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ +#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ +#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ +#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ +#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ +#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */ +/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ +#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */ +#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ +/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ +#define GMAC_UR_RMII (0x1u << 0) /**< \brief (GMAC_UR) Reduced MII Mode */ +/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos 0 +#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ +#define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))) +#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ +#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ +#define GMAC_DCFGR_RXBMS_Pos 8 +#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))) +#define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 4/8 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 4/4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4/2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ +#define GMAC_DCFGR_DRBS_Pos 16 +#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ +#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) +#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */ +/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ +#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */ +#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */ +#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ +#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */ +#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */ +#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */ +/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */ +#define GMAC_RBQB_ADDR_Pos 2 +#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */ +#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) +/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */ +#define GMAC_TBQB_ADDR_Pos 2 +#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ +#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) +/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ +#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */ +#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */ +#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */ +#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */ +/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */ +#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */ +#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */ +#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */ +#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Underrun */ +#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */ +#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */ +#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */ +#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */ +#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */ +#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ +#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ +#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ +#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ +#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ +#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ +#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ +#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ +#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ +#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ +#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */ +/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */ +#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */ +#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */ +#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */ +#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Underrun */ +#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ +#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */ +#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */ +#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */ +#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */ +#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */ +#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */ +#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ +#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */ +#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ +#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ +#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */ +#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */ +#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ +#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ +#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ +#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */ +#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */ +#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */ +#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */ +#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Underrun */ +#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */ +#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */ +#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */ +#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */ +#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ +#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */ +#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ +#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ +#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ +#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ +#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ +#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ +#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ +#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ +#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */ +/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */ +#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */ +#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */ +#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */ +#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Underrun */ +#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */ +#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */ +#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */ +#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */ +#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */ +#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ +#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */ +#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ +#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ +#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ +#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ +#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ +#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ +#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ +#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ +#define GMAC_IMR_SRI (0x1u << 26) /**< \brief (GMAC_IMR) TSU Seconds Register Increment */ +#define GMAC_IMR_WOL (0x1u << 28) /**< \brief (GMAC_IMR) Wake On LAN */ +/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos 0 +#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */ +#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) +#define GMAC_MAN_WTN_Pos 16 +#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */ +#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) +#define GMAC_MAN_REGA_Pos 18 +#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */ +#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) +#define GMAC_MAN_PHYA_Pos 23 +#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */ +#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) +#define GMAC_MAN_OP_Pos 28 +#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */ +#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) +#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */ +#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */ +/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos 0 +#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */ +/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos 0 +#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ +#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) +/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos 0 +#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) Transmit Partial Store and Forward Address */ +#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) +#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */ +/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos 0 +#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) Receive Partial Store and Forward Address */ +#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) +#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */ +/* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */ +#define GMAC_RJFML_FML_Pos 0 +#define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) /**< \brief (GMAC_RJFML) Frame Max Length */ +#define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))) +/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */ +#define GMAC_HRB_ADDR_Pos 0 +#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */ +#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) +/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */ +#define GMAC_HRT_ADDR_Pos 0 +#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */ +#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) +/* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */ +#define GMAC_SAB_ADDR_Pos 0 +#define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) /**< \brief (GMAC_SAB) Specific Address 1 */ +#define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))) +/* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */ +#define GMAC_SAT_ADDR_Pos 0 +#define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) /**< \brief (GMAC_SAT) Specific Address 1 */ +#define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))) +/* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ +#define GMAC_TIDM1_TID_Pos 0 +#define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) /**< \brief (GMAC_TIDM1) Type ID Match 1 */ +#define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos))) +#define GMAC_TIDM1_ENID1 (0x1u << 31) /**< \brief (GMAC_TIDM1) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */ +#define GMAC_TIDM2_TID_Pos 0 +#define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) /**< \brief (GMAC_TIDM2) Type ID Match 2 */ +#define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos))) +#define GMAC_TIDM2_ENID2 (0x1u << 31) /**< \brief (GMAC_TIDM2) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */ +#define GMAC_TIDM3_TID_Pos 0 +#define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) /**< \brief (GMAC_TIDM3) Type ID Match 3 */ +#define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos))) +#define GMAC_TIDM3_ENID3 (0x1u << 31) /**< \brief (GMAC_TIDM3) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */ +#define GMAC_TIDM4_TID_Pos 0 +#define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) /**< \brief (GMAC_TIDM4) Type ID Match 4 */ +#define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos))) +#define GMAC_TIDM4_ENID4 (0x1u << 31) /**< \brief (GMAC_TIDM4) Enable Copying of TID Matched Frames */ +/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos 0 +#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) +#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */ +#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */ +#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */ +/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos 0 +#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */ +#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) +/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos 0 +#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ +#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) +#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ +/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos 0 +#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ +#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) +#define GMAC_TPFCP_PQ_Pos 8 +#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */ +#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) +/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */ +#define GMAC_SAMB1_ADDR_Pos 0 +#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ +#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) +/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */ +#define GMAC_SAMT1_ADDR_Pos 0 +#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ +#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) +/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */ +#define GMAC_NSC_NANOSEC_Pos 0 +#define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) /**< \brief (GMAC_NSC) 1588 Timer Nanosecond Comparison Value */ +#define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))) +/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */ +#define GMAC_SCL_SEC_Pos 0 +#define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) /**< \brief (GMAC_SCL) 1588 Timer Second Comparison Value */ +#define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))) +/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */ +#define GMAC_SCH_SEC_Pos 0 +#define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) /**< \brief (GMAC_SCH) 1588 Timer Second Comparison Value */ +#define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))) +/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_EFTSH_RUD_Pos 0 +#define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) /**< \brief (GMAC_EFTSH) Register Update */ +/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */ +#define GMAC_EFRSH_RUD_Pos 0 +#define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) /**< \brief (GMAC_EFRSH) Register Update */ +/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_PEFTSH_RUD_Pos 0 +#define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) /**< \brief (GMAC_PEFTSH) Register Update */ +/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */ +#define GMAC_PEFRSH_RUD_Pos 0 +#define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) /**< \brief (GMAC_PEFRSH) Register Update */ +/* -------- GMAC_MID : (GMAC Offset: 0x0FC) Module ID Register -------- */ +#define GMAC_MID_MREV_Pos 0 +#define GMAC_MID_MREV_Msk (0xffffu << GMAC_MID_MREV_Pos) /**< \brief (GMAC_MID) Module Revision */ +#define GMAC_MID_MID_Pos 16 +#define GMAC_MID_MID_Msk (0xffffu << GMAC_MID_MID_Pos) /**< \brief (GMAC_MID) Module Identification Number */ +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */ +#define GMAC_OTLO_TXO_Pos 0 +#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */ +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */ +#define GMAC_OTHI_TXO_Pos 0 +#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */ +/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos 0 +#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */ +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos 0 +#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ +/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos 0 +#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ +/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos 0 +#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos 0 +#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos 0 +#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos 0 +#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos 0 +#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos 0 +#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos 0 +#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos 0 +#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */ +#define GMAC_TUR_TXUNR_Pos 0 +#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Underruns */ +/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos 0 +#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */ +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos 0 +#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */ +/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos 0 +#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */ +/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos 0 +#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */ +/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos 0 +#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */ +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */ +#define GMAC_CSE_CSR_Pos 0 +#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */ +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */ +#define GMAC_ORLO_RXO_Pos 0 +#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */ +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */ +#define GMAC_ORHI_RXO_Pos 0 +#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */ +/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos 0 +#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */ +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos 0 +#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ +/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos 0 +#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ +/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos 0 +#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */ +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos 0 +#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos 0 +#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos 0 +#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos 0 +#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos 0 +#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos 0 +#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos 0 +#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ +/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos 0 +#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */ +/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos 0 +#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */ +/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos 0 +#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */ +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos 0 +#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos 0 +#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ +/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos 0 +#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */ +/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos 0 +#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */ +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos 0 +#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */ +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos 0 +#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */ +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos 0 +#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos 0 +#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */ +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos 0 +#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */ +/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */ +#define GMAC_TISUBN_LSBTIR_Pos 0 +#define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register */ +#define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))) +/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */ +#define GMAC_TSH_TCS_Pos 0 +#define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) /**< \brief (GMAC_TSH) Timer Count in Seconds */ +#define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))) +/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */ +#define GMAC_TSL_TCS_Pos 0 +#define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) /**< \brief (GMAC_TSL) Timer Count in Seconds */ +#define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))) +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos 0 +#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ +#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos 0 +#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */ +#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) +#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */ +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos 0 +#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */ +#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) +#define GMAC_TI_ACNS_Pos 8 +#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ +#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) +#define GMAC_TI_NIT_Pos 16 +#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */ +#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) +/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_EFTSL_RUD_Pos 0 +#define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) /**< \brief (GMAC_EFTSL) Register Update */ +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_EFTN_RUD_Pos 0 +#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */ +/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */ +#define GMAC_EFRSL_RUD_Pos 0 +#define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) /**< \brief (GMAC_EFRSL) Register Update */ +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */ +#define GMAC_EFRN_RUD_Pos 0 +#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */ +/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_PEFTSL_RUD_Pos 0 +#define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) /**< \brief (GMAC_PEFTSL) Register Update */ +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_PEFTN_RUD_Pos 0 +#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */ +/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */ +#define GMAC_PEFRSL_RUD_Pos 0 +#define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) /**< \brief (GMAC_PEFRSL) Register Update */ +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */ +#define GMAC_PEFRN_RUD_Pos 0 +#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */ +/* -------- GMAC_RXLPI : (GMAC Offset: 0x270) Received LPI Transitions -------- */ +#define GMAC_RXLPI_COUNT_Pos 0 +#define GMAC_RXLPI_COUNT_Msk (0xffffu << GMAC_RXLPI_COUNT_Pos) /**< \brief (GMAC_RXLPI) Count of RX LPI transitions (cleared on read) */ +/* -------- GMAC_RXLPITIME : (GMAC Offset: 0x274) Received LPI Time -------- */ +#define GMAC_RXLPITIME_LPITIME_Pos 0 +#define GMAC_RXLPITIME_LPITIME_Msk (0xffffffu << GMAC_RXLPITIME_LPITIME_Pos) /**< \brief (GMAC_RXLPITIME) Time in LPI (cleared on read) */ +/* -------- GMAC_TXLPI : (GMAC Offset: 0x278) Transmit LPI Transitions -------- */ +#define GMAC_TXLPI_COUNT_Pos 0 +#define GMAC_TXLPI_COUNT_Msk (0xffffu << GMAC_TXLPI_COUNT_Pos) /**< \brief (GMAC_TXLPI) Count of LPI transitions (cleared on read) */ +/* -------- GMAC_TXLPITIME : (GMAC Offset: 0x27C) Transmit LPI Time -------- */ +#define GMAC_TXLPITIME_LPITIME_Pos 0 +#define GMAC_TXLPITIME_LPITIME_Msk (0xffffffu << GMAC_TXLPITIME_LPITIME_Pos) /**< \brief (GMAC_TXLPITIME) Time in LPI (cleared on read) */ +/* -------- GMAC_ISRPQ[5] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) -------- */ +#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[5]) Receive Complete */ +#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[5]) RX Used Bit Read */ +#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[5]) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[5]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[5]) Transmit Complete */ +#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[5]) Receive Overrun */ +#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[5]) HRESP Not OK */ +/* -------- GMAC_TBQBAPQ[5] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos 2 +#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[5]) Transmit Buffer Queue Base Address */ +#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) +/* -------- GMAC_RBQBAPQ[5] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos 2 +#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[5]) Receive Buffer Queue Base Address */ +#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) +/* -------- GMAC_RBSRPQ[5] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) -------- */ +#define GMAC_RBSRPQ_RBS_Pos 0 +#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[5]) Receive Buffer Size */ +#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) +/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */ +#define GMAC_CBSCR_QBE (0x1u << 0) /**< \brief (GMAC_CBSCR) Queue B CBS Enable */ +#define GMAC_CBSCR_QAE (0x1u << 1) /**< \brief (GMAC_CBSCR) Queue A CBS Enable */ +/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */ +#define GMAC_CBSISQA_IS_Pos 0 +#define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) /**< \brief (GMAC_CBSISQA) IdleSlope */ +#define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos))) +/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */ +#define GMAC_CBSISQB_IS_Pos 0 +#define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) /**< \brief (GMAC_CBSISQB) IdleSlope */ +#define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos))) +/* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST1RPQ_QNB_Pos 0 +#define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[4]) Queue Number (0-5) */ +#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) +#define GMAC_ST1RPQ_DSTCM_Pos 4 +#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match */ +#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) +#define GMAC_ST1RPQ_UDPM_Pos 12 +#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match */ +#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) +#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable */ +#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match Enable */ +/* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST2RPQ_QNB_Pos 0 +#define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Queue Number (0-5) */ +#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) +#define GMAC_ST2RPQ_VLANP_Pos 4 +#define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[8]) VLAN Priority */ +#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) +#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[8]) VLAN Enable */ +#define GMAC_ST2RPQ_I2ETH_Pos 9 +#define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x */ +#define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos))) +#define GMAC_ST2RPQ_ETHE (0x1u << 12) /**< \brief (GMAC_ST2RPQ[8]) EtherType Enable */ +#define GMAC_ST2RPQ_COMPA_Pos 13 +#define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos))) +#define GMAC_ST2RPQ_COMPAE (0x1u << 18) /**< \brief (GMAC_ST2RPQ[8]) Compare A Enable */ +#define GMAC_ST2RPQ_COMPB_Pos 19 +#define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos))) +#define GMAC_ST2RPQ_COMPBE (0x1u << 24) /**< \brief (GMAC_ST2RPQ[8]) Compare B Enable */ +#define GMAC_ST2RPQ_COMPC_Pos 25 +#define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos))) +#define GMAC_ST2RPQ_COMPCE (0x1u << 30) /**< \brief (GMAC_ST2RPQ[8]) Compare C Enable */ +/* -------- GMAC_IERPQ[5] : (GMAC Offset: 0x5FC) Interrupt Enable Register Priority Queue (index = 1) -------- */ +#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[5]) Receive Complete */ +#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[5]) RX Used Bit Read */ +#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[5]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[5]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[5]) Transmit Complete */ +#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[5]) Receive Overrun */ +#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[5]) HRESP Not OK */ +/* -------- GMAC_IDRPQ[5] : (GMAC Offset: 0x61C) Interrupt Disable Register Priority Queue (index = 1) -------- */ +#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[5]) Receive Complete */ +#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[5]) RX Used Bit Read */ +#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[5]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[5]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[5]) Transmit Complete */ +#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[5]) Receive Overrun */ +#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[5]) HRESP Not OK */ +/* -------- GMAC_IMRPQ[5] : (GMAC Offset: 0x63C) Interrupt Mask Register Priority Queue (index = 1) -------- */ +#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[5]) Receive Complete */ +#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[5]) RX Used Bit Read */ +#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[5]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[5]) AHB Error */ +#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[5]) Transmit Complete */ +#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[5]) Receive Overrun */ +#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[5]) HRESP Not OK */ +/* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) -------- */ +#define GMAC_ST2ER_COMPVAL_Pos 0 +#define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) /**< \brief (GMAC_ST2ER[4]) Ethertype Compare Value */ +#define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos))) +/* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) -------- */ +#define GMAC_ST2CW00_MASKVAL_Pos 0 +#define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos) /**< \brief (GMAC_ST2CW00) Mask Value */ +#define GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos))) +#define GMAC_ST2CW00_COMPVAL_Pos 16 +#define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos) /**< \brief (GMAC_ST2CW00) Compare Value */ +#define GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos))) +/* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) -------- */ +#define GMAC_ST2CW10_OFFSVAL_Pos 0 +#define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW10) Offset Value in Bytes */ +#define GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_Pos 7 +#define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW10) Ethernet Frame Offset Start */ +#define GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW10) Offset from the start of the frame */ +#define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the IP header field */ +#define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) -------- */ +#define GMAC_ST2CW01_MASKVAL_Pos 0 +#define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos) /**< \brief (GMAC_ST2CW01) Mask Value */ +#define GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos))) +#define GMAC_ST2CW01_COMPVAL_Pos 16 +#define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos) /**< \brief (GMAC_ST2CW01) Compare Value */ +#define GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos))) +/* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) -------- */ +#define GMAC_ST2CW11_OFFSVAL_Pos 0 +#define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW11) Offset Value in Bytes */ +#define GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_Pos 7 +#define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW11) Ethernet Frame Offset Start */ +#define GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW11) Offset from the start of the frame */ +#define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the IP header field */ +#define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) -------- */ +#define GMAC_ST2CW02_MASKVAL_Pos 0 +#define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos) /**< \brief (GMAC_ST2CW02) Mask Value */ +#define GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos))) +#define GMAC_ST2CW02_COMPVAL_Pos 16 +#define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos) /**< \brief (GMAC_ST2CW02) Compare Value */ +#define GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos))) +/* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) -------- */ +#define GMAC_ST2CW12_OFFSVAL_Pos 0 +#define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW12) Offset Value in Bytes */ +#define GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_Pos 7 +#define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW12) Ethernet Frame Offset Start */ +#define GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW12) Offset from the start of the frame */ +#define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the IP header field */ +#define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) -------- */ +#define GMAC_ST2CW03_MASKVAL_Pos 0 +#define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos) /**< \brief (GMAC_ST2CW03) Mask Value */ +#define GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos))) +#define GMAC_ST2CW03_COMPVAL_Pos 16 +#define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos) /**< \brief (GMAC_ST2CW03) Compare Value */ +#define GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos))) +/* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) -------- */ +#define GMAC_ST2CW13_OFFSVAL_Pos 0 +#define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW13) Offset Value in Bytes */ +#define GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_Pos 7 +#define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW13) Ethernet Frame Offset Start */ +#define GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW13) Offset from the start of the frame */ +#define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the IP header field */ +#define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) -------- */ +#define GMAC_ST2CW04_MASKVAL_Pos 0 +#define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos) /**< \brief (GMAC_ST2CW04) Mask Value */ +#define GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos))) +#define GMAC_ST2CW04_COMPVAL_Pos 16 +#define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos) /**< \brief (GMAC_ST2CW04) Compare Value */ +#define GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos))) +/* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) -------- */ +#define GMAC_ST2CW14_OFFSVAL_Pos 0 +#define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW14) Offset Value in Bytes */ +#define GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_Pos 7 +#define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW14) Ethernet Frame Offset Start */ +#define GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW14) Offset from the start of the frame */ +#define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the IP header field */ +#define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) -------- */ +#define GMAC_ST2CW05_MASKVAL_Pos 0 +#define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos) /**< \brief (GMAC_ST2CW05) Mask Value */ +#define GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos))) +#define GMAC_ST2CW05_COMPVAL_Pos 16 +#define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos) /**< \brief (GMAC_ST2CW05) Compare Value */ +#define GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos))) +/* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) -------- */ +#define GMAC_ST2CW15_OFFSVAL_Pos 0 +#define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW15) Offset Value in Bytes */ +#define GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_Pos 7 +#define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW15) Ethernet Frame Offset Start */ +#define GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW15) Offset from the start of the frame */ +#define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the IP header field */ +#define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) -------- */ +#define GMAC_ST2CW06_MASKVAL_Pos 0 +#define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos) /**< \brief (GMAC_ST2CW06) Mask Value */ +#define GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos))) +#define GMAC_ST2CW06_COMPVAL_Pos 16 +#define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos) /**< \brief (GMAC_ST2CW06) Compare Value */ +#define GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos))) +/* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) -------- */ +#define GMAC_ST2CW16_OFFSVAL_Pos 0 +#define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW16) Offset Value in Bytes */ +#define GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_Pos 7 +#define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW16) Ethernet Frame Offset Start */ +#define GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW16) Offset from the start of the frame */ +#define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the IP header field */ +#define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) -------- */ +#define GMAC_ST2CW07_MASKVAL_Pos 0 +#define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos) /**< \brief (GMAC_ST2CW07) Mask Value */ +#define GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos))) +#define GMAC_ST2CW07_COMPVAL_Pos 16 +#define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos) /**< \brief (GMAC_ST2CW07) Compare Value */ +#define GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos))) +/* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) -------- */ +#define GMAC_ST2CW17_OFFSVAL_Pos 0 +#define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW17) Offset Value in Bytes */ +#define GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_Pos 7 +#define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW17) Ethernet Frame Offset Start */ +#define GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW17) Offset from the start of the frame */ +#define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the IP header field */ +#define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) -------- */ +#define GMAC_ST2CW08_MASKVAL_Pos 0 +#define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos) /**< \brief (GMAC_ST2CW08) Mask Value */ +#define GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos))) +#define GMAC_ST2CW08_COMPVAL_Pos 16 +#define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos) /**< \brief (GMAC_ST2CW08) Compare Value */ +#define GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos))) +/* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) -------- */ +#define GMAC_ST2CW18_OFFSVAL_Pos 0 +#define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW18) Offset Value in Bytes */ +#define GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_Pos 7 +#define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW18) Ethernet Frame Offset Start */ +#define GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW18) Offset from the start of the frame */ +#define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the IP header field */ +#define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) -------- */ +#define GMAC_ST2CW09_MASKVAL_Pos 0 +#define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos) /**< \brief (GMAC_ST2CW09) Mask Value */ +#define GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos))) +#define GMAC_ST2CW09_COMPVAL_Pos 16 +#define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos) /**< \brief (GMAC_ST2CW09) Compare Value */ +#define GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos))) +/* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) -------- */ +#define GMAC_ST2CW19_OFFSVAL_Pos 0 +#define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW19) Offset Value in Bytes */ +#define GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_Pos 7 +#define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW19) Ethernet Frame Offset Start */ +#define GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW19) Offset from the start of the frame */ +#define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the IP header field */ +#define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) -------- */ +#define GMAC_ST2CW010_MASKVAL_Pos 0 +#define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos) /**< \brief (GMAC_ST2CW010) Mask Value */ +#define GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos))) +#define GMAC_ST2CW010_COMPVAL_Pos 16 +#define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos) /**< \brief (GMAC_ST2CW010) Compare Value */ +#define GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos))) +/* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) -------- */ +#define GMAC_ST2CW110_OFFSVAL_Pos 0 +#define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW110) Offset Value in Bytes */ +#define GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_Pos 7 +#define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW110) Ethernet Frame Offset Start */ +#define GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW110) Offset from the start of the frame */ +#define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the IP header field */ +#define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) -------- */ +#define GMAC_ST2CW011_MASKVAL_Pos 0 +#define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos) /**< \brief (GMAC_ST2CW011) Mask Value */ +#define GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos))) +#define GMAC_ST2CW011_COMPVAL_Pos 16 +#define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos) /**< \brief (GMAC_ST2CW011) Compare Value */ +#define GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos))) +/* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) -------- */ +#define GMAC_ST2CW111_OFFSVAL_Pos 0 +#define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW111) Offset Value in Bytes */ +#define GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_Pos 7 +#define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW111) Ethernet Frame Offset Start */ +#define GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW111) Offset from the start of the frame */ +#define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the IP header field */ +#define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) -------- */ +#define GMAC_ST2CW012_MASKVAL_Pos 0 +#define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos) /**< \brief (GMAC_ST2CW012) Mask Value */ +#define GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos))) +#define GMAC_ST2CW012_COMPVAL_Pos 16 +#define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos) /**< \brief (GMAC_ST2CW012) Compare Value */ +#define GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos))) +/* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) -------- */ +#define GMAC_ST2CW112_OFFSVAL_Pos 0 +#define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW112) Offset Value in Bytes */ +#define GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_Pos 7 +#define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW112) Ethernet Frame Offset Start */ +#define GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW112) Offset from the start of the frame */ +#define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the IP header field */ +#define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) -------- */ +#define GMAC_ST2CW013_MASKVAL_Pos 0 +#define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos) /**< \brief (GMAC_ST2CW013) Mask Value */ +#define GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos))) +#define GMAC_ST2CW013_COMPVAL_Pos 16 +#define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos) /**< \brief (GMAC_ST2CW013) Compare Value */ +#define GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos))) +/* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) -------- */ +#define GMAC_ST2CW113_OFFSVAL_Pos 0 +#define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW113) Offset Value in Bytes */ +#define GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_Pos 7 +#define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW113) Ethernet Frame Offset Start */ +#define GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW113) Offset from the start of the frame */ +#define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the IP header field */ +#define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) -------- */ +#define GMAC_ST2CW014_MASKVAL_Pos 0 +#define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos) /**< \brief (GMAC_ST2CW014) Mask Value */ +#define GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos))) +#define GMAC_ST2CW014_COMPVAL_Pos 16 +#define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos) /**< \brief (GMAC_ST2CW014) Compare Value */ +#define GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos))) +/* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) -------- */ +#define GMAC_ST2CW114_OFFSVAL_Pos 0 +#define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW114) Offset Value in Bytes */ +#define GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_Pos 7 +#define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW114) Ethernet Frame Offset Start */ +#define GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW114) Offset from the start of the frame */ +#define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the IP header field */ +#define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) -------- */ +#define GMAC_ST2CW015_MASKVAL_Pos 0 +#define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos) /**< \brief (GMAC_ST2CW015) Mask Value */ +#define GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos))) +#define GMAC_ST2CW015_COMPVAL_Pos 16 +#define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos) /**< \brief (GMAC_ST2CW015) Compare Value */ +#define GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos))) +/* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) -------- */ +#define GMAC_ST2CW115_OFFSVAL_Pos 0 +#define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW115) Offset Value in Bytes */ +#define GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_Pos 7 +#define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW115) Ethernet Frame Offset Start */ +#define GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW115) Offset from the start of the frame */ +#define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the IP header field */ +#define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) -------- */ +#define GMAC_ST2CW016_MASKVAL_Pos 0 +#define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos) /**< \brief (GMAC_ST2CW016) Mask Value */ +#define GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos))) +#define GMAC_ST2CW016_COMPVAL_Pos 16 +#define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos) /**< \brief (GMAC_ST2CW016) Compare Value */ +#define GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos))) +/* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) -------- */ +#define GMAC_ST2CW116_OFFSVAL_Pos 0 +#define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW116) Offset Value in Bytes */ +#define GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_Pos 7 +#define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW116) Ethernet Frame Offset Start */ +#define GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW116) Offset from the start of the frame */ +#define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the IP header field */ +#define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) -------- */ +#define GMAC_ST2CW017_MASKVAL_Pos 0 +#define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos) /**< \brief (GMAC_ST2CW017) Mask Value */ +#define GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos))) +#define GMAC_ST2CW017_COMPVAL_Pos 16 +#define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos) /**< \brief (GMAC_ST2CW017) Compare Value */ +#define GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos))) +/* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) -------- */ +#define GMAC_ST2CW117_OFFSVAL_Pos 0 +#define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW117) Offset Value in Bytes */ +#define GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_Pos 7 +#define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW117) Ethernet Frame Offset Start */ +#define GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW117) Offset from the start of the frame */ +#define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the IP header field */ +#define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) -------- */ +#define GMAC_ST2CW018_MASKVAL_Pos 0 +#define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos) /**< \brief (GMAC_ST2CW018) Mask Value */ +#define GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos))) +#define GMAC_ST2CW018_COMPVAL_Pos 16 +#define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos) /**< \brief (GMAC_ST2CW018) Compare Value */ +#define GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos))) +/* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) -------- */ +#define GMAC_ST2CW118_OFFSVAL_Pos 0 +#define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW118) Offset Value in Bytes */ +#define GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_Pos 7 +#define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW118) Ethernet Frame Offset Start */ +#define GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW118) Offset from the start of the frame */ +#define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the IP header field */ +#define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) -------- */ +#define GMAC_ST2CW019_MASKVAL_Pos 0 +#define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos) /**< \brief (GMAC_ST2CW019) Mask Value */ +#define GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos))) +#define GMAC_ST2CW019_COMPVAL_Pos 16 +#define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos) /**< \brief (GMAC_ST2CW019) Compare Value */ +#define GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos))) +/* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) -------- */ +#define GMAC_ST2CW119_OFFSVAL_Pos 0 +#define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW119) Offset Value in Bytes */ +#define GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_Pos 7 +#define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW119) Ethernet Frame Offset Start */ +#define GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW119) Offset from the start of the frame */ +#define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the IP header field */ +#define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) -------- */ +#define GMAC_ST2CW020_MASKVAL_Pos 0 +#define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos) /**< \brief (GMAC_ST2CW020) Mask Value */ +#define GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos))) +#define GMAC_ST2CW020_COMPVAL_Pos 16 +#define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos) /**< \brief (GMAC_ST2CW020) Compare Value */ +#define GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos))) +/* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) -------- */ +#define GMAC_ST2CW120_OFFSVAL_Pos 0 +#define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW120) Offset Value in Bytes */ +#define GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_Pos 7 +#define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW120) Ethernet Frame Offset Start */ +#define GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW120) Offset from the start of the frame */ +#define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the IP header field */ +#define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) -------- */ +#define GMAC_ST2CW021_MASKVAL_Pos 0 +#define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos) /**< \brief (GMAC_ST2CW021) Mask Value */ +#define GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos))) +#define GMAC_ST2CW021_COMPVAL_Pos 16 +#define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos) /**< \brief (GMAC_ST2CW021) Compare Value */ +#define GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos))) +/* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) -------- */ +#define GMAC_ST2CW121_OFFSVAL_Pos 0 +#define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW121) Offset Value in Bytes */ +#define GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_Pos 7 +#define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW121) Ethernet Frame Offset Start */ +#define GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW121) Offset from the start of the frame */ +#define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the IP header field */ +#define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) -------- */ +#define GMAC_ST2CW022_MASKVAL_Pos 0 +#define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos) /**< \brief (GMAC_ST2CW022) Mask Value */ +#define GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos))) +#define GMAC_ST2CW022_COMPVAL_Pos 16 +#define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos) /**< \brief (GMAC_ST2CW022) Compare Value */ +#define GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos))) +/* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) -------- */ +#define GMAC_ST2CW122_OFFSVAL_Pos 0 +#define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW122) Offset Value in Bytes */ +#define GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_Pos 7 +#define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW122) Ethernet Frame Offset Start */ +#define GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW122) Offset from the start of the frame */ +#define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the IP header field */ +#define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) -------- */ +#define GMAC_ST2CW023_MASKVAL_Pos 0 +#define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos) /**< \brief (GMAC_ST2CW023) Mask Value */ +#define GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos))) +#define GMAC_ST2CW023_COMPVAL_Pos 16 +#define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos) /**< \brief (GMAC_ST2CW023) Compare Value */ +#define GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos))) +/* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) -------- */ +#define GMAC_ST2CW123_OFFSVAL_Pos 0 +#define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW123) Offset Value in Bytes */ +#define GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_Pos 7 +#define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW123) Ethernet Frame Offset Start */ +#define GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW123) Offset from the start of the frame */ +#define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the IP header field */ +#define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field */ + +/*@}*/ + + +#endif /* _SAME70_GMAC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/gpbr.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/gpbr.h new file mode 100644 index 00000000..d6d19b0d --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/gpbr.h @@ -0,0 +1,58 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_GPBR_COMPONENT_ +#define _SAME70_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ +/* ============================================================================= */ +/** \addtogroup SAME70_GPBR General Purpose Backup Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAME70_GPBR_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/hsmci.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/hsmci.h new file mode 100644 index 00000000..d2f35e30 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/hsmci.h @@ -0,0 +1,347 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_HSMCI_COMPONENT_ +#define _SAME70_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved2[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t HSMCI_VERSION; /**< \brief (Hsmci Offset: 0xFC) Version Register */ + __I uint32_t Reserved4[64]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos 4 +#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos))) +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */ +#define HSMCI_WPMR_WPKEY_Pos 8 +#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */ +#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos))) +#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WPVSRC_Pos 8 +#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */ +/* -------- HSMCI_VERSION : (HSMCI Offset: 0xFC) Version Register -------- */ +#define HSMCI_VERSION_VERSION_Pos 0 +#define HSMCI_VERSION_VERSION_Msk (0xfffu << HSMCI_VERSION_VERSION_Pos) /**< \brief (HSMCI_VERSION) Hardware Module Version */ +#define HSMCI_VERSION_MFN_Pos 16 +#define HSMCI_VERSION_MFN_Msk (0x7u << HSMCI_VERSION_MFN_Pos) /**< \brief (HSMCI_VERSION) Metal Fix Number */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAME70_HSMCI_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/i2sc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/i2sc.h new file mode 100644 index 00000000..ea0afdbe --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/i2sc.h @@ -0,0 +1,174 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_I2SC_COMPONENT_ +#define _SAME70_I2SC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Inter-IC Sound Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_I2SC Inter-IC Sound Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief I2sc hardware registers */ +typedef struct { + __O uint32_t I2SC_CR; /**< \brief (I2sc Offset: 0x00) Control Register */ + __IO uint32_t I2SC_MR; /**< \brief (I2sc Offset: 0x04) Mode Register */ + __I uint32_t I2SC_SR; /**< \brief (I2sc Offset: 0x08) Status Register */ + __O uint32_t I2SC_SCR; /**< \brief (I2sc Offset: 0x0C) Status Clear Register */ + __O uint32_t I2SC_SSR; /**< \brief (I2sc Offset: 0x10) Status Set Register */ + __O uint32_t I2SC_IER; /**< \brief (I2sc Offset: 0x14) Interrupt Enable Register */ + __O uint32_t I2SC_IDR; /**< \brief (I2sc Offset: 0x18) Interrupt Disable Register */ + __I uint32_t I2SC_IMR; /**< \brief (I2sc Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t I2SC_RHR; /**< \brief (I2sc Offset: 0x20) Receiver Holding Register */ + __O uint32_t I2SC_THR; /**< \brief (I2sc Offset: 0x24) Transmitter Holding Register */ + __I uint32_t I2SC_VERSION; /**< \brief (I2sc Offset: 0x28) Version Register */ +} I2sc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- I2SC_CR : (I2SC Offset: 0x00) Control Register -------- */ +#define I2SC_CR_RXEN (0x1u << 0) /**< \brief (I2SC_CR) Receiver Enable */ +#define I2SC_CR_RXDIS (0x1u << 1) /**< \brief (I2SC_CR) Receiver Disable */ +#define I2SC_CR_CKEN (0x1u << 2) /**< \brief (I2SC_CR) Clocks Enable */ +#define I2SC_CR_CKDIS (0x1u << 3) /**< \brief (I2SC_CR) Clocks Disable */ +#define I2SC_CR_TXEN (0x1u << 4) /**< \brief (I2SC_CR) Transmitter Enable */ +#define I2SC_CR_TXDIS (0x1u << 5) /**< \brief (I2SC_CR) Transmitter Disable */ +#define I2SC_CR_SWRST (0x1u << 7) /**< \brief (I2SC_CR) Software Reset */ +/* -------- I2SC_MR : (I2SC Offset: 0x04) Mode Register -------- */ +#define I2SC_MR_MODE (0x1u << 0) /**< \brief (I2SC_MR) Inter-IC Sound Controller Mode */ +#define I2SC_MR_MODE_SLAVE (0x0u << 0) /**< \brief (I2SC_MR) I2SCK and i2SWS pin inputs used as bit clock and word select/frame synchronization. */ +#define I2SC_MR_MODE_MASTER (0x1u << 0) /**< \brief (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SCK and I2SWS pins. MCK is output as master clock on I2SMCK if I2SC_MR.IMCKMODE is set. */ +#define I2SC_MR_DATALENGTH_Pos 2 +#define I2SC_MR_DATALENGTH_Msk (0x7u << I2SC_MR_DATALENGTH_Pos) /**< \brief (I2SC_MR) Data Word Length */ +#define I2SC_MR_DATALENGTH(value) ((I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos))) +#define I2SC_MR_DATALENGTH_32_BITS (0x0u << 2) /**< \brief (I2SC_MR) Data length is set to 32 bits */ +#define I2SC_MR_DATALENGTH_24_BITS (0x1u << 2) /**< \brief (I2SC_MR) Data length is set to 24 bits */ +#define I2SC_MR_DATALENGTH_20_BITS (0x2u << 2) /**< \brief (I2SC_MR) Data length is set to 20 bits */ +#define I2SC_MR_DATALENGTH_18_BITS (0x3u << 2) /**< \brief (I2SC_MR) Data length is set to 18 bits */ +#define I2SC_MR_DATALENGTH_16_BITS (0x4u << 2) /**< \brief (I2SC_MR) Data length is set to 16 bits */ +#define I2SC_MR_DATALENGTH_16_BITS_COMPACT (0x5u << 2) /**< \brief (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. */ +#define I2SC_MR_DATALENGTH_8_BITS (0x6u << 2) /**< \brief (I2SC_MR) Data length is set to 8 bits */ +#define I2SC_MR_DATALENGTH_8_BITS_COMPACT (0x7u << 2) /**< \brief (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. */ +#define I2SC_MR_FORMAT_Pos 6 +#define I2SC_MR_FORMAT_Msk (0x3u << I2SC_MR_FORMAT_Pos) /**< \brief (I2SC_MR) Data Format */ +#define I2SC_MR_FORMAT(value) ((I2SC_MR_FORMAT_Msk & ((value) << I2SC_MR_FORMAT_Pos))) +#define I2SC_MR_FORMAT_I2S (0x0u << 6) /**< \brief (I2SC_MR) I2S format, stereo with I2SWS low for left channel, and MSB of sample starting one I2SCK period after I2SWS edge */ +#define I2SC_MR_FORMAT_LJ (0x1u << 6) /**< \brief (I2SC_MR) Left-justified format, stereo with I2SWS high for left channel, and MSB of sample starting on I2SWS edge */ +#define I2SC_MR_RXMONO (0x1u << 8) /**< \brief (I2SC_MR) Receive Mono */ +#define I2SC_MR_RXDMA (0x1u << 9) /**< \brief (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver */ +#define I2SC_MR_RXLOOP (0x1u << 10) /**< \brief (I2SC_MR) Loop-back Test Mode */ +#define I2SC_MR_TXMONO (0x1u << 12) /**< \brief (I2SC_MR) Transmit Mono */ +#define I2SC_MR_TXDMA (0x1u << 13) /**< \brief (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter */ +#define I2SC_MR_TXSAME (0x1u << 14) /**< \brief (I2SC_MR) Transmit Data when Underrun */ +#define I2SC_MR_IMCKDIV_Pos 16 +#define I2SC_MR_IMCKDIV_Msk (0x3fu << I2SC_MR_IMCKDIV_Pos) /**< \brief (I2SC_MR) Selected Clock to I2SC Master Clock Ratio */ +#define I2SC_MR_IMCKDIV(value) ((I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos))) +#define I2SC_MR_IMCKFS_Pos 24 +#define I2SC_MR_IMCKFS_Msk (0x3fu << I2SC_MR_IMCKFS_Pos) /**< \brief (I2SC_MR) Master Clock to fs Ratio */ +#define I2SC_MR_IMCKFS(value) ((I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos))) +#define I2SC_MR_IMCKFS_M2SF32 (0x0u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 32 */ +#define I2SC_MR_IMCKFS_M2SF64 (0x1u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 64 */ +#define I2SC_MR_IMCKFS_M2SF96 (0x2u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 96 */ +#define I2SC_MR_IMCKFS_M2SF128 (0x3u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 128 */ +#define I2SC_MR_IMCKFS_M2SF192 (0x5u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 192 */ +#define I2SC_MR_IMCKFS_M2SF256 (0x7u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 256 */ +#define I2SC_MR_IMCKFS_M2SF384 (0xBu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 384 */ +#define I2SC_MR_IMCKFS_M2SF512 (0xFu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 512 */ +#define I2SC_MR_IMCKFS_M2SF768 (0x17u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 768 */ +#define I2SC_MR_IMCKFS_M2SF1024 (0x1Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 1024 */ +#define I2SC_MR_IMCKFS_M2SF1536 (0x2Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 1536 */ +#define I2SC_MR_IMCKFS_M2SF2048 (0x3Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 2048 */ +#define I2SC_MR_IMCKMODE (0x1u << 30) /**< \brief (I2SC_MR) Master Clock Mode */ +#define I2SC_MR_IWS (0x1u << 31) /**< \brief (I2SC_MR) I2SWS Slot Width */ +/* -------- I2SC_SR : (I2SC Offset: 0x08) Status Register -------- */ +#define I2SC_SR_RXEN (0x1u << 0) /**< \brief (I2SC_SR) Receiver Enabled */ +#define I2SC_SR_RXRDY (0x1u << 1) /**< \brief (I2SC_SR) Receive Ready */ +#define I2SC_SR_RXOR (0x1u << 2) /**< \brief (I2SC_SR) Receive Overrun */ +#define I2SC_SR_TXEN (0x1u << 4) /**< \brief (I2SC_SR) Transmitter Enabled */ +#define I2SC_SR_TXRDY (0x1u << 5) /**< \brief (I2SC_SR) Transmit Ready */ +#define I2SC_SR_TXUR (0x1u << 6) /**< \brief (I2SC_SR) Transmit Underrun */ +#define I2SC_SR_RXORCH_Pos 8 +#define I2SC_SR_RXORCH_Msk (0x3u << I2SC_SR_RXORCH_Pos) /**< \brief (I2SC_SR) Receive Overrun Channel */ +#define I2SC_SR_TXURCH_Pos 20 +#define I2SC_SR_TXURCH_Msk (0x3u << I2SC_SR_TXURCH_Pos) /**< \brief (I2SC_SR) Transmit Underrun Channel */ +/* -------- I2SC_SCR : (I2SC Offset: 0x0C) Status Clear Register -------- */ +#define I2SC_SCR_RXOR (0x1u << 2) /**< \brief (I2SC_SCR) Receive Overrun Status Clear */ +#define I2SC_SCR_TXUR (0x1u << 6) /**< \brief (I2SC_SCR) Transmit Underrun Status Clear */ +#define I2SC_SCR_RXORCH_Pos 8 +#define I2SC_SCR_RXORCH_Msk (0x3u << I2SC_SCR_RXORCH_Pos) /**< \brief (I2SC_SCR) Receive Overrun Per Channel Status Clear */ +#define I2SC_SCR_RXORCH(value) ((I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos))) +#define I2SC_SCR_TXURCH_Pos 20 +#define I2SC_SCR_TXURCH_Msk (0x3u << I2SC_SCR_TXURCH_Pos) /**< \brief (I2SC_SCR) Transmit Underrun Per Channel Status Clear */ +#define I2SC_SCR_TXURCH(value) ((I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos))) +/* -------- I2SC_SSR : (I2SC Offset: 0x10) Status Set Register -------- */ +#define I2SC_SSR_RXOR (0x1u << 2) /**< \brief (I2SC_SSR) Receive Overrun Status Set */ +#define I2SC_SSR_TXUR (0x1u << 6) /**< \brief (I2SC_SSR) Transmit Underrun Status Set */ +#define I2SC_SSR_RXORCH_Pos 8 +#define I2SC_SSR_RXORCH_Msk (0x3u << I2SC_SSR_RXORCH_Pos) /**< \brief (I2SC_SSR) Receive Overrun Per Channel Status Set */ +#define I2SC_SSR_RXORCH(value) ((I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos))) +#define I2SC_SSR_TXURCH_Pos 20 +#define I2SC_SSR_TXURCH_Msk (0x3u << I2SC_SSR_TXURCH_Pos) /**< \brief (I2SC_SSR) Transmit Underrun Per Channel Status Set */ +#define I2SC_SSR_TXURCH(value) ((I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos))) +/* -------- I2SC_IER : (I2SC Offset: 0x14) Interrupt Enable Register -------- */ +#define I2SC_IER_RXRDY (0x1u << 1) /**< \brief (I2SC_IER) Receiver Ready Interrupt Enable */ +#define I2SC_IER_RXOR (0x1u << 2) /**< \brief (I2SC_IER) Receiver Overrun Interrupt Enable */ +#define I2SC_IER_TXRDY (0x1u << 5) /**< \brief (I2SC_IER) Transmit Ready Interrupt Enable */ +#define I2SC_IER_TXUR (0x1u << 6) /**< \brief (I2SC_IER) Transmit Underflow Interrupt Enable */ +/* -------- I2SC_IDR : (I2SC Offset: 0x18) Interrupt Disable Register -------- */ +#define I2SC_IDR_RXRDY (0x1u << 1) /**< \brief (I2SC_IDR) Receiver Ready Interrupt Disable */ +#define I2SC_IDR_RXOR (0x1u << 2) /**< \brief (I2SC_IDR) Receiver Overrun Interrupt Disable */ +#define I2SC_IDR_TXRDY (0x1u << 5) /**< \brief (I2SC_IDR) Transmit Ready Interrupt Disable */ +#define I2SC_IDR_TXUR (0x1u << 6) /**< \brief (I2SC_IDR) Transmit Underflow Interrupt Disable */ +/* -------- I2SC_IMR : (I2SC Offset: 0x1C) Interrupt Mask Register -------- */ +#define I2SC_IMR_RXRDY (0x1u << 1) /**< \brief (I2SC_IMR) Receiver Ready Interrupt Disable */ +#define I2SC_IMR_RXOR (0x1u << 2) /**< \brief (I2SC_IMR) Receiver Overrun Interrupt Disable */ +#define I2SC_IMR_TXRDY (0x1u << 5) /**< \brief (I2SC_IMR) Transmit Ready Interrupt Disable */ +#define I2SC_IMR_TXUR (0x1u << 6) /**< \brief (I2SC_IMR) Transmit Underflow Interrupt Disable */ +/* -------- I2SC_RHR : (I2SC Offset: 0x20) Receiver Holding Register -------- */ +#define I2SC_RHR_RHR_Pos 0 +#define I2SC_RHR_RHR_Msk (0xffffffffu << I2SC_RHR_RHR_Pos) /**< \brief (I2SC_RHR) Receiver Holding Register */ +/* -------- I2SC_THR : (I2SC Offset: 0x24) Transmitter Holding Register -------- */ +#define I2SC_THR_THR_Pos 0 +#define I2SC_THR_THR_Msk (0xffffffffu << I2SC_THR_THR_Pos) /**< \brief (I2SC_THR) Transmitter Holding Register */ +#define I2SC_THR_THR(value) ((I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos))) +/* -------- I2SC_VERSION : (I2SC Offset: 0x28) Version Register -------- */ +#define I2SC_VERSION_VERSION_Pos 0 +#define I2SC_VERSION_VERSION_Msk (0xfffu << I2SC_VERSION_VERSION_Pos) /**< \brief (I2SC_VERSION) Version of the Hardware Module */ +#define I2SC_VERSION_MFN_Pos 16 +#define I2SC_VERSION_MFN_Msk (0x7u << I2SC_VERSION_MFN_Pos) /**< \brief (I2SC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_I2SC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/icm.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/icm.h new file mode 100644 index 00000000..98a4e3fa --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/icm.h @@ -0,0 +1,229 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ICM_COMPONENT_ +#define _SAME70_ICM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */ +/* ============================================================================= */ +/** \addtogroup SAME70_ICM Integrity Check Monitor */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Icm hardware registers */ +typedef struct { + __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */ + __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */ + __I uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */ + __I uint32_t Reserved3[37]; + __I uint32_t ICM_ADDRSIZE; /**< \brief (Icm Offset: 0xEC) Address Size Register */ + __I uint32_t ICM_IPNAME[2]; /**< \brief (Icm Offset: 0xF0) IP Name 1 Register */ + __I uint32_t ICM_FEATURES; /**< \brief (Icm Offset: 0xF8) Feature Register */ + __I uint32_t ICM_VERSION; /**< \brief (Icm Offset: 0xFC) Version Register */ +} Icm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */ +#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */ +#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */ +#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */ +#define ICM_CFG_BBC_Pos 4 +#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */ +#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))) +#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */ +#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */ +#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */ +#define ICM_CFG_UALGO_Pos 13 +#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */ +#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))) +#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_HAPROT_Pos 16 +#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */ +#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))) +#define ICM_CFG_DAPROT_Pos 24 +#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */ +#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))) +/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */ +#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */ +#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */ +#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */ +#define ICM_CTRL_REHASH_Pos 4 +#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */ +#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))) +#define ICM_CTRL_RMDIS_Pos 8 +#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */ +#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))) +#define ICM_CTRL_RMEN_Pos 12 +#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */ +#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))) +/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */ +#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */ +#define ICM_SR_RAWRMDIS_Pos 8 +#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */ +#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))) +#define ICM_SR_RMDIS_Pos 12 +#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */ +#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))) +/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos 0 +#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */ +#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))) +#define ICM_IER_RDM_Pos 4 +#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */ +#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))) +#define ICM_IER_RBE_Pos 8 +#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */ +#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))) +#define ICM_IER_RWC_Pos 12 +#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */ +#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))) +#define ICM_IER_REC_Pos 16 +#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */ +#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))) +#define ICM_IER_RSU_Pos 20 +#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */ +#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))) +#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */ +/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos 0 +#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */ +#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))) +#define ICM_IDR_RDM_Pos 4 +#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */ +#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))) +#define ICM_IDR_RBE_Pos 8 +#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */ +#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))) +#define ICM_IDR_RWC_Pos 12 +#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */ +#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))) +#define ICM_IDR_REC_Pos 16 +#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */ +#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))) +#define ICM_IDR_RSU_Pos 20 +#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */ +#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))) +#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */ +/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos 0 +#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */ +#define ICM_IMR_RDM_Pos 4 +#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */ +#define ICM_IMR_RBE_Pos 8 +#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */ +#define ICM_IMR_RWC_Pos 12 +#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */ +#define ICM_IMR_REC_Pos 16 +#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */ +#define ICM_IMR_RSU_Pos 20 +#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */ +#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */ +/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos 0 +#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */ +#define ICM_ISR_RDM_Pos 4 +#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */ +#define ICM_ISR_RBE_Pos 8 +#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */ +#define ICM_ISR_RWC_Pos 12 +#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */ +#define ICM_ISR_REC_Pos 16 +#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */ +#define ICM_ISR_RSU_Pos 20 +#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */ +#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */ +/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos 0 +#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */ +/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos 6 +#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */ +#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))) +/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos 7 +#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */ +#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))) +/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */ +#define ICM_UIHVAL_VAL_Pos 0 +#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */ +#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))) +/* -------- ICM_ADDRSIZE : (ICM Offset: 0xEC) Address Size Register -------- */ +#define ICM_ADDRSIZE_ADDRSIZE_Pos 0 +#define ICM_ADDRSIZE_ADDRSIZE_Msk (0xffffu << ICM_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (ICM_ADDRSIZE) Peripheral Bus Address Area Size */ +/* -------- ICM_IPNAME[2] : (ICM Offset: 0xF0) IP Name 1 Register -------- */ +#define ICM_IPNAME_IPNAME_Pos 0 +#define ICM_IPNAME_IPNAME_Msk (0xffffffffu << ICM_IPNAME_IPNAME_Pos) /**< \brief (ICM_IPNAME[2]) IP Name in ASCII Format */ +/* -------- ICM_FEATURES : (ICM Offset: 0xF8) Feature Register -------- */ +#define ICM_FEATURES_CFGALGO (0x1u << 0) /**< \brief (ICM_FEATURES) Configurable Algorithms */ +#define ICM_FEATURES_RFU (0x1u << 1) /**< \brief (ICM_FEATURES) Reserved for Future Use */ +#define ICM_FEATURES_CFGPP (0x1u << 2) /**< \brief (ICM_FEATURES) Configurable Processing Period */ +#define ICM_FEATURES_HDPP (0x1u << 3) /**< \brief (ICM_FEATURES) Hardcoded Processing Period */ +#define ICM_FEATURES_PDC (0x1u << 4) /**< \brief (ICM_FEATURES) Peripheral DMA Logic */ +#define ICM_FEATURES_NAIS (0x1u << 5) /**< \brief (ICM_FEATURES) No Access to Intermediate State */ +#define ICM_FEATURES_EF (0x1u << 6) /**< \brief (ICM_FEATURES) Embedded LFSR */ +#define ICM_FEATURES_SI (0x1u << 7) /**< \brief (ICM_FEATURES) Scan Intrusion */ +#define ICM_FEATURES_BTYP (0x1u << 8) /**< \brief (ICM_FEATURES) Bridge Type */ +#define ICM_FEATURES_PDCOFF0C (0x1u << 9) /**< \brief (ICM_FEATURES) PDC Offset is 0x0C */ +#define ICM_FEATURES_HSHA1 (0x1u << 16) /**< \brief (ICM_FEATURES) SHA1 Hardcoded Mode */ +#define ICM_FEATURES_HSHA224 (0x1u << 17) /**< \brief (ICM_FEATURES) SHA224 Hardcoded Mode */ +#define ICM_FEATURES_HSHA256 (0x1u << 18) /**< \brief (ICM_FEATURES) SHA256 Hardcoded Mode */ +#define ICM_FEATURES_HSHA384 (0x1u << 19) /**< \brief (ICM_FEATURES) SHA384 Hardcoded Mode */ +#define ICM_FEATURES_HSHA512 (0x1u << 20) /**< \brief (ICM_FEATURES) SHA512 Hardcoded Mode */ +/* -------- ICM_VERSION : (ICM Offset: 0xFC) Version Register -------- */ +#define ICM_VERSION_VERSION_Pos 0 +#define ICM_VERSION_VERSION_Msk (0xfffu << ICM_VERSION_VERSION_Pos) /**< \brief (ICM_VERSION) Version of the Hardware Module */ +#define ICM_VERSION_MFN_Pos 16 +#define ICM_VERSION_MFN_Msk (0x7u << ICM_VERSION_MFN_Pos) /**< \brief (ICM_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_ICM_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/isi.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/isi.h new file mode 100644 index 00000000..c4467413 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/isi.h @@ -0,0 +1,293 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ISI_COMPONENT_ +#define _SAME70_ISI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Image Sensor Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_ISI Image Sensor Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Isi hardware registers */ +typedef struct { + __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ + __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ + __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ + __I uint32_t Reserved1[34]; + __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved2[4]; + __I uint32_t ISI_VERSION; /**< \brief (Isi Offset: 0xFC) Version Register */ +} Isi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ +#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ +#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ +#define ISI_CFG1_GRAYLE (0x1u << 5) /**< \brief (ISI_CFG1) Grayscale Little Endian */ +#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ +#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ +#define ISI_CFG1_FRATE_Pos 8 +#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ +#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) +#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ +#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ +#define ISI_CFG1_THMASK_Pos 13 +#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ +#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))) +#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_SLD_Pos 16 +#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ +#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) +#define ISI_CFG1_SFD_Pos 24 +#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ +#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) +/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos 0 +#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) +#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */ +#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */ +#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */ +#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */ +#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ +#define ISI_CFG2_IM_HSIZE_Pos 16 +#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) +#define ISI_CFG2_YCC_SWAP_Pos 28 +#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */ +#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) +#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_RGB_CFG_Pos 30 +#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */ +#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) +#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos 0 +#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ +#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 +#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ +#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) +/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos 0 +#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ +#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos 0 +#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) +#define ISI_Y2R_SET0_C1_Pos 8 +#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) +#define ISI_Y2R_SET0_C2_Pos 16 +#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) +#define ISI_Y2R_SET0_C3_Pos 24 +#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos 0 +#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) +#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ +#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ +#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos 0 +#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) +#define ISI_R2Y_SET0_C1_Pos 8 +#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) +#define ISI_R2Y_SET0_C2_Pos 16 +#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) +#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos 0 +#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) +#define ISI_R2Y_SET1_C4_Pos 8 +#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) +#define ISI_R2Y_SET1_C5_Pos 16 +#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ +#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) +#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos 0 +#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ +#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) +#define ISI_R2Y_SET2_C7_Pos 8 +#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ +#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) +#define ISI_R2Y_SET2_C8_Pos 16 +#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ +#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) +#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ +/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ +#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ +#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ +#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ +#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ +/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ +#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */ +#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */ +#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */ +#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */ +#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */ +#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */ +#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */ +#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */ +#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */ +#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */ +/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ +#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ +#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ +#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ +#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ +#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ +#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ +#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ +#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ +/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ +#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ +#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ +#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ +#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ +#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ +#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ +/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ +#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ +#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ +#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */ +#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */ +#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */ +#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */ +#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ +#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ +#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */ +#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */ +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */ +#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */ +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 +#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */ +#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */ +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 +#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */ +#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 +#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */ +#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */ +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 +#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */ +#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) +/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */ +#define ISI_WPMR_WPKEY_Pos 8 +#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */ +#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))) +#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */ +#define ISI_WPSR_WPVSRC_Pos 8 +#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ +/* -------- ISI_VERSION : (ISI Offset: 0xFC) Version Register -------- */ +#define ISI_VERSION_VERSION_Pos 0 +#define ISI_VERSION_VERSION_Msk (0xfffu << ISI_VERSION_VERSION_Pos) /**< \brief (ISI_VERSION) Version of the Hardware Module */ +#define ISI_VERSION_MFN_Pos 16 +#define ISI_VERSION_MFN_Msk (0x7u << ISI_VERSION_MFN_Pos) /**< \brief (ISI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_ISI_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/matrix.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/matrix.h new file mode 100644 index 00000000..40d858f6 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/matrix.h @@ -0,0 +1,328 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_MATRIX_COMPONENT_ +#define _SAME70_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAME70_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MatrixPr hardware registers */ +typedef struct { + __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */ +} MatrixPr; +/** \brief Matrix hardware registers */ +#define MATRIXPR_NUMBER 9 +typedef struct { + __IO uint32_t MATRIX_MCFG0; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register 0 */ + __IO uint32_t MATRIX_MCFG1; /**< \brief (Matrix Offset: 0x0004) Master Configuration Register 1 */ + __IO uint32_t MATRIX_MCFG2; /**< \brief (Matrix Offset: 0x0008) Master Configuration Register 2 */ + __IO uint32_t MATRIX_MCFG3; /**< \brief (Matrix Offset: 0x000C) Master Configuration Register 3 */ + __IO uint32_t MATRIX_MCFG4; /**< \brief (Matrix Offset: 0x0010) Master Configuration Register 4 */ + __IO uint32_t MATRIX_MCFG5; /**< \brief (Matrix Offset: 0x0014) Master Configuration Register 5 */ + __IO uint32_t MATRIX_MCFG6; /**< \brief (Matrix Offset: 0x0018) Master Configuration Register 6 */ + __I uint32_t Reserved1[1]; + __IO uint32_t MATRIX_MCFG8; /**< \brief (Matrix Offset: 0x0020) Master Configuration Register 8 */ + __IO uint32_t MATRIX_MCFG9; /**< \brief (Matrix Offset: 0x0024) Master Configuration Register 9 */ + __IO uint32_t MATRIX_MCFG10; /**< \brief (Matrix Offset: 0x0028) Master Configuration Register 10 */ + __IO uint32_t MATRIX_MCFG11; /**< \brief (Matrix Offset: 0x002C) Master Configuration Register 11 */ + __IO uint32_t MATRIX_MCFG12; /**< \brief (Matrix Offset: 0x0030) Master Configuration Register 12 */ + __I uint32_t Reserved2[3]; + __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved3[7]; + MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 8 */ + __I uint32_t Reserved4[14]; + __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t CCFG_CAN0; /**< \brief (Matrix Offset: 0x0110) CAN0 Configuration Register */ + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register */ + __IO uint32_t CCFG_PCCR; /**< \brief (Matrix Offset: 0x0118) Peripheral Clock Configuration Register */ + __IO uint32_t CCFG_DYNCFG; /**< \brief (Matrix Offset: 0x011C) Dynamic Clock Gating Register */ + __I uint32_t Reserved6[1]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */ + __I uint32_t Reserved7[47]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */ + __I uint32_t Reserved8[4]; + __I uint32_t MATRIX_VERSION; /**< \brief (Matrix Offset: 0x01FC) Version Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */ +#define MATRIX_MCFG0_ULBT_Pos 0 +#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) /**< \brief (MATRIX_MCFG0) Undefined Length Burst Type */ +#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos))) +#define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG0) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG0) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG0) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG0) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG0) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG0) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG0) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG0) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */ +#define MATRIX_MCFG1_ULBT_Pos 0 +#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) /**< \brief (MATRIX_MCFG1) Undefined Length Burst Type */ +#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos))) +#define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG1) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG1) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG1) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG1) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG1) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG1) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG1) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG1) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */ +#define MATRIX_MCFG2_ULBT_Pos 0 +#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) /**< \brief (MATRIX_MCFG2) Undefined Length Burst Type */ +#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos))) +#define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG2) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG2) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG2) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG2) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG2) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG2) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG2) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG2) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */ +#define MATRIX_MCFG3_ULBT_Pos 0 +#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) /**< \brief (MATRIX_MCFG3) Undefined Length Burst Type */ +#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos))) +#define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG3) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG3) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG3) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG3) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG3) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG3) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG3) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG3) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */ +#define MATRIX_MCFG4_ULBT_Pos 0 +#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) /**< \brief (MATRIX_MCFG4) Undefined Length Burst Type */ +#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos))) +#define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG4) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG4) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG4) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG4) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG4) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG4) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG4) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG4) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */ +#define MATRIX_MCFG5_ULBT_Pos 0 +#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) /**< \brief (MATRIX_MCFG5) Undefined Length Burst Type */ +#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos))) +#define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG5) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG5) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG5) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG5) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG5) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG5) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG5) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG5) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */ +#define MATRIX_MCFG6_ULBT_Pos 0 +#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) /**< \brief (MATRIX_MCFG6) Undefined Length Burst Type */ +#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos))) +#define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG6) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG6) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG6) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG6) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG6) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG6) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG6) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG6) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */ +#define MATRIX_MCFG8_ULBT_Pos 0 +#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) /**< \brief (MATRIX_MCFG8) Undefined Length Burst Type */ +#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos))) +#define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG8) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG8) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG8) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG8) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG8) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG8) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG8) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG8) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG9 : (MATRIX Offset: 0x0024) Master Configuration Register 9 -------- */ +#define MATRIX_MCFG9_ULBT_Pos 0 +#define MATRIX_MCFG9_ULBT_Msk (0x7u << MATRIX_MCFG9_ULBT_Pos) /**< \brief (MATRIX_MCFG9) Undefined Length Burst Type */ +#define MATRIX_MCFG9_ULBT(value) ((MATRIX_MCFG9_ULBT_Msk & ((value) << MATRIX_MCFG9_ULBT_Pos))) +#define MATRIX_MCFG9_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG9) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG9_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG9) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG9_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG9) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG9_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG9) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG9_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG9) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG9_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG9) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG9_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG9) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG9_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG9) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG10 : (MATRIX Offset: 0x0028) Master Configuration Register 10 -------- */ +#define MATRIX_MCFG10_ULBT_Pos 0 +#define MATRIX_MCFG10_ULBT_Msk (0x7u << MATRIX_MCFG10_ULBT_Pos) /**< \brief (MATRIX_MCFG10) Undefined Length Burst Type */ +#define MATRIX_MCFG10_ULBT(value) ((MATRIX_MCFG10_ULBT_Msk & ((value) << MATRIX_MCFG10_ULBT_Pos))) +#define MATRIX_MCFG10_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG10) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG10_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG10) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG10_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG10) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG10_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG10) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG10_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG10) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG10_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG10) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG10_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG10) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG10_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG10) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG11 : (MATRIX Offset: 0x002C) Master Configuration Register 11 -------- */ +#define MATRIX_MCFG11_ULBT_Pos 0 +#define MATRIX_MCFG11_ULBT_Msk (0x7u << MATRIX_MCFG11_ULBT_Pos) /**< \brief (MATRIX_MCFG11) Undefined Length Burst Type */ +#define MATRIX_MCFG11_ULBT(value) ((MATRIX_MCFG11_ULBT_Msk & ((value) << MATRIX_MCFG11_ULBT_Pos))) +#define MATRIX_MCFG11_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG11) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG11_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG11) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG11_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG11) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG11_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG11) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG11_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG11) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG11_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG11) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG11_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG11) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG11_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG11) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS_M0PR_Pos 0 +#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */ +#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos))) +#define MATRIX_PRAS_M1PR_Pos 4 +#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */ +#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos))) +#define MATRIX_PRAS_M2PR_Pos 8 +#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */ +#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos))) +#define MATRIX_PRAS_M3PR_Pos 12 +#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */ +#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos))) +#define MATRIX_PRAS_M4PR_Pos 16 +#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */ +#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos))) +#define MATRIX_PRAS_M5PR_Pos 20 +#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */ +#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos))) +#define MATRIX_PRAS_M6PR_Pos 24 +#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */ +#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos))) +/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS_M8PR_Pos 0 +#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */ +#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos))) +#define MATRIX_PRBS_M9PR_Pos 4 +#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */ +#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos))) +#define MATRIX_PRBS_M10PR_Pos 8 +#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */ +#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos))) +#define MATRIX_PRBS_M11PR_Pos 12 +#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */ +#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos))) +#define MATRIX_PRBS_M12PR_Pos 16 +#define MATRIX_PRBS_M12PR_Msk (0x3u << MATRIX_PRBS_M12PR_Pos) /**< \brief (MATRIX_PRBS) Master 12 Priority */ +#define MATRIX_PRBS_M12PR(value) ((MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */ +#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */ +#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */ +#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */ +#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */ +#define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 9 */ +#define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 10 */ +#define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 11 */ +#define MATRIX_MRCR_RCB12 (0x1u << 12) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 12 */ +/* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */ +#define CCFG_CAN0_CAN0DMABA_Pos 16 +#define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos) /**< \brief (CCFG_CAN0) CAN0 DMA Base Address */ +#define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos))) +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +#define CCFG_SYSIO_CAN1DMABA_Pos 16 +#define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos) /**< \brief (CCFG_SYSIO) CAN1 DMA Base Address */ +#define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos))) +/* -------- CCFG_PCCR : (MATRIX Offset: 0x0118) Peripheral Clock Configuration Register -------- */ +#define CCFG_PCCR_TC0CC (0x1u << 20) /**< \brief (CCFG_PCCR) TC0 Clock Configuration */ +#define CCFG_PCCR_I2SC0CC (0x1u << 21) /**< \brief (CCFG_PCCR) I2SC0 Clock Configuration */ +#define CCFG_PCCR_I2SC1CC (0x1u << 22) /**< \brief (CCFG_PCCR) I2SC1 Clock Configuration */ +/* -------- CCFG_DYNCKG : (MATRIX Offset: 0x11c) (R/W 32) Dynamic Clock Gating Register -------- */ +#define CCFG_DYNCKG_MATCKG (0x1u << 0) /**< \brief (CCFG_DYNCKG) MATRIX Dynamic Clock Gating */ +#define CCFG_DYNCKG_BRIDCKG (0x1u << 1) /**< \brief (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable */ +#define CCFG_DYNCKG_EFCCKG (0x1u << 2) /**< \brief (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable */ +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */ +/* -------- MATRIX_VERSION : (MATRIX Offset: 0x01FC) Version Register -------- */ +#define MATRIX_VERSION_VERSION_Pos 0 +#define MATRIX_VERSION_VERSION_Msk (0xfffu << MATRIX_VERSION_VERSION_Pos) /**< \brief (MATRIX_VERSION) Version of the Hardware Module */ +#define MATRIX_VERSION_MFN_Pos 16 +#define MATRIX_VERSION_MFN_Msk (0x7u << MATRIX_VERSION_MFN_Pos) /**< \brief (MATRIX_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_MATRIX_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/mcan.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/mcan.h new file mode 100644 index 00000000..490dc5c3 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/mcan.h @@ -0,0 +1,940 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_MCAN_COMPONENT_ +#define _SAME70_MCAN_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Controller Area Network */ +/* ============================================================================= */ +/** \addtogroup SAME70_MCAN Controller Area Network */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mcan hardware registers */ +typedef struct { + __I uint32_t MCAN_CREL; /**< \brief (Mcan Offset: 0x00) Core Release Register */ + __I uint32_t MCAN_ENDN; /**< \brief (Mcan Offset: 0x04) Endian Register */ + __IO uint32_t MCAN_CUST; /**< \brief (Mcan Offset: 0x08) Customer Register */ +#if (__SAM_M7_REVB == 1) + __IO uint32_t MCAN_DBTP; /**< \brief (Mcan Offset: 0x0C) Data Bit Timing and Prescaler Register */ +#else + __IO uint32_t MCAN_FBTP; /**< \brief (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register */ +#endif + __IO uint32_t MCAN_TEST; /**< \brief (Mcan Offset: 0x10) Test Register */ + __IO uint32_t MCAN_RWD; /**< \brief (Mcan Offset: 0x14) RAM Watchdog Register */ + __IO uint32_t MCAN_CCCR; /**< \brief (Mcan Offset: 0x18) CC Control Register */ +#if (__SAM_M7_REVB == 1) + __IO uint32_t MCAN_NBTP; /**< \brief (Mcan Offset: 0x1C) Nominal Bit Timing and Prescaler Register */ +#else + __IO uint32_t MCAN_BTP; /**< \brief (Mcan Offset: 0x1C) Bit Timing and Prescaler Register */ +#endif + __IO uint32_t MCAN_TSCC; /**< \brief (Mcan Offset: 0x20) Timestamp Counter Configuration Register */ + __IO uint32_t MCAN_TSCV; /**< \brief (Mcan Offset: 0x24) Timestamp Counter Value Register */ + __IO uint32_t MCAN_TOCC; /**< \brief (Mcan Offset: 0x28) Timeout Counter Configuration Register */ + __IO uint32_t MCAN_TOCV; /**< \brief (Mcan Offset: 0x2C) Timeout Counter Value Register */ + __I uint32_t Reserved1[4]; + __I uint32_t MCAN_ECR; /**< \brief (Mcan Offset: 0x40) Error Counter Register */ + __I uint32_t MCAN_PSR; /**< \brief (Mcan Offset: 0x44) Protocol Status Register */ +#if (__SAM_M7_REVB == 1) + __IO uint32_t MCAN_TDCR; /**< \brief (Mcan Offset: 0x48) Transmit Delay Compensation Register */ + __I uint32_t Reserved2[1]; +#else + __I uint32_t Reserved2[2]; +#endif + __IO uint32_t MCAN_IR; /**< \brief (Mcan Offset: 0x50) Interrupt Register */ + __IO uint32_t MCAN_IE; /**< \brief (Mcan Offset: 0x54) Interrupt Enable Register */ + __IO uint32_t MCAN_ILS; /**< \brief (Mcan Offset: 0x58) Interrupt Line Select Register */ + __IO uint32_t MCAN_ILE; /**< \brief (Mcan Offset: 0x5C) Interrupt Line Enable Register */ + __I uint32_t Reserved3[8]; + __IO uint32_t MCAN_GFC; /**< \brief (Mcan Offset: 0x80) Global Filter Configuration Register */ + __IO uint32_t MCAN_SIDFC; /**< \brief (Mcan Offset: 0x84) Standard ID Filter Configuration Register */ + __IO uint32_t MCAN_XIDFC; /**< \brief (Mcan Offset: 0x88) Extended ID Filter Configuration Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t MCAN_XIDAM; /**< \brief (Mcan Offset: 0x90) Extended ID AND Mask Register */ + __I uint32_t MCAN_HPMS; /**< \brief (Mcan Offset: 0x94) High Priority Message Status Register */ + __IO uint32_t MCAN_NDAT1; /**< \brief (Mcan Offset: 0x98) New Data 1 Register */ + __IO uint32_t MCAN_NDAT2; /**< \brief (Mcan Offset: 0x9C) New Data 2 Register */ + __IO uint32_t MCAN_RXF0C; /**< \brief (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register */ + __I uint32_t MCAN_RXF0S; /**< \brief (Mcan Offset: 0xA4) Receive FIFO 0 Status Register */ + __IO uint32_t MCAN_RXF0A; /**< \brief (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register */ + __IO uint32_t MCAN_RXBC; /**< \brief (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register */ + __IO uint32_t MCAN_RXF1C; /**< \brief (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register */ + __I uint32_t MCAN_RXF1S; /**< \brief (Mcan Offset: 0xB4) Receive FIFO 1 Status Register */ + __IO uint32_t MCAN_RXF1A; /**< \brief (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register */ + __IO uint32_t MCAN_RXESC; /**< \brief (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */ + __IO uint32_t MCAN_TXBC; /**< \brief (Mcan Offset: 0xC0) Transmit Buffer Configuration Register */ + __I uint32_t MCAN_TXFQS; /**< \brief (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register */ + __IO uint32_t MCAN_TXESC; /**< \brief (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register */ + __I uint32_t MCAN_TXBRP; /**< \brief (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register */ + __IO uint32_t MCAN_TXBAR; /**< \brief (Mcan Offset: 0xD0) Transmit Buffer Add Request Register */ + __IO uint32_t MCAN_TXBCR; /**< \brief (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register */ + __I uint32_t MCAN_TXBTO; /**< \brief (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register */ + __I uint32_t MCAN_TXBCF; /**< \brief (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register */ + __IO uint32_t MCAN_TXBTIE; /**< \brief (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */ + __IO uint32_t MCAN_TXBCIE; /**< \brief (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint32_t Reserved5[2]; + __IO uint32_t MCAN_TXEFC; /**< \brief (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register */ + __I uint32_t MCAN_TXEFS; /**< \brief (Mcan Offset: 0xF4) Transmit Event FIFO Status Register */ + __IO uint32_t MCAN_TXEFA; /**< \brief (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register */ +} Mcan; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MCAN_CREL : (MCAN Offset: 0x00) Core Release Register -------- */ +#define MCAN_CREL_DAY_Pos 0 +#define MCAN_CREL_DAY_Msk (0xffu << MCAN_CREL_DAY_Pos) /**< \brief (MCAN_CREL) Timestamp Day */ +#define MCAN_CREL_MON_Pos 8 +#define MCAN_CREL_MON_Msk (0xffu << MCAN_CREL_MON_Pos) /**< \brief (MCAN_CREL) Timestamp Month */ +#define MCAN_CREL_YEAR_Pos 16 +#define MCAN_CREL_YEAR_Msk (0xfu << MCAN_CREL_YEAR_Pos) /**< \brief (MCAN_CREL) Timestamp Year */ +#define MCAN_CREL_SUBSTEP_Pos 20 +#define MCAN_CREL_SUBSTEP_Msk (0xfu << MCAN_CREL_SUBSTEP_Pos) /**< \brief (MCAN_CREL) Sub-step of Core Release */ +#define MCAN_CREL_STEP_Pos 24 +#define MCAN_CREL_STEP_Msk (0xfu << MCAN_CREL_STEP_Pos) /**< \brief (MCAN_CREL) Step of Core Release */ +#define MCAN_CREL_REL_Pos 28 +#define MCAN_CREL_REL_Msk (0xfu << MCAN_CREL_REL_Pos) /**< \brief (MCAN_CREL) Core Release */ +/* -------- MCAN_ENDN : (MCAN Offset: 0x04) Endian Register -------- */ +#define MCAN_ENDN_ETV_Pos 0 +#define MCAN_ENDN_ETV_Msk (0xffffffffu << MCAN_ENDN_ETV_Pos) /**< \brief (MCAN_ENDN) Endianness Test Value */ +/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */ +#define MCAN_CUST_CSV_Pos 0 +#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos) /**< \brief (MCAN_CUST) Customer-specific Value */ +#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos))) +/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */ +#define MCAN_FBTP_FSJW_Pos 0 +#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ +#define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos))) +#define MCAN_FBTP_FTSEG2_Pos 4 +#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ +#define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos))) +#define MCAN_FBTP_FTSEG1_Pos 8 +#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ +#define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos))) +#define MCAN_FBTP_FBRP_Pos 16 +#define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /**< \brief (MCAN_FBTP) Fast Baud Rate Prescaler */ +#define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos))) +#define MCAN_FBTP_TDC (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation */ +#define MCAN_FBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation disabled. */ +#define MCAN_FBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation enabled. */ +#define MCAN_FBTP_TDCO_Pos 24 +#define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos) /**< \brief (MCAN_FBTP) Transce iver Delay Compensation Offset */ +#define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos))) +/* -------- MCAN_DBTP : (MCAN Offset: 0x0C) Data Bit Timing and Prescaler Register -------- */ +#define MCAN_DBTP_DSJW_Pos 0 +#define MCAN_DBTP_DSJW_Msk (0x7u << MCAN_DBTP_DSJW_Pos) /**< \brief (MCAN_DBTP) Data (Re) Synchronization Jump Width */ +#define MCAN_DBTP_DSJW(value) ((MCAN_DBTP_DSJW_Msk & ((value) << MCAN_DBTP_DSJW_Pos))) +#define MCAN_DBTP_DTSEG2_Pos 4 +#define MCAN_DBTP_DTSEG2_Msk (0xfu << MCAN_DBTP_DTSEG2_Pos) /**< \brief (MCAN_DBTP) Data Time Segment After Sample Point */ +#define MCAN_DBTP_DTSEG2(value) ((MCAN_DBTP_DTSEG2_Msk & ((value) << MCAN_DBTP_DTSEG2_Pos))) +#define MCAN_DBTP_DTSEG1_Pos 8 +#define MCAN_DBTP_DTSEG1_Msk (0x1fu << MCAN_DBTP_DTSEG1_Pos) /**< \brief (MCAN_DBTP) Data Time Segment Before Sample Point */ +#define MCAN_DBTP_DTSEG1(value) ((MCAN_DBTP_DTSEG1_Msk & ((value) << MCAN_DBTP_DTSEG1_Pos))) +#define MCAN_DBTP_DBRP_Pos 16 +#define MCAN_DBTP_DBRP_Msk (0x1fu << MCAN_DBTP_DBRP_Pos) /**< \brief (MCAN_DBTP) Data Bit Rate Prescaler */ +#define MCAN_DBTP_DBRP(value) ((MCAN_DBTP_DBRP_Msk & ((value) << MCAN_DBTP_DBRP_Pos))) +#define MCAN_DBTP_TDC (0x1u << 23) /**< \brief (MCAN_DBTP) Transmitter Delay Compensation */ +#define MCAN_DBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_DBTP) Transmitter Delay Compensation disabled. */ +#define MCAN_DBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_DBTP) Transmitter Delay Compensation enabled. */ +/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */ +#define MCAN_TEST_LBCK (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back Mode (read/write) */ +#define MCAN_TEST_LBCK_DISABLED (0x0u << 4) /**< \brief (MCAN_TEST) Reset value. Loop Back mode is disabled. */ +#define MCAN_TEST_LBCK_ENABLED (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back mode is enabled (see Section 6.1.9). */ +#define MCAN_TEST_TX_Pos 5 +#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos) /**< \brief (MCAN_TEST) Control of Transmit Pin (read/write) */ +#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos))) +#define MCAN_TEST_TX_RESET (0x0u << 5) /**< \brief (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5) /**< \brief (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ +#define MCAN_TEST_TX_DOMINANT (0x2u << 5) /**< \brief (MCAN_TEST) Dominant ('0') level at pin CANTX. */ +#define MCAN_TEST_TX_RECESSIVE (0x3u << 5) /**< \brief (MCAN_TEST) Recessive ('1') at pin CANTX. */ +#define MCAN_TEST_RX (0x1u << 7) /**< \brief (MCAN_TEST) Receive Pin (read-only) */ +#define MCAN_TEST_TDCV_Pos 8 +#define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos) /**< \brief (MCAN_TEST) Transceiver Delay Compensation Value (read-only) */ +#define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos))) +/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */ +#define MCAN_RWD_WDC_Pos 0 +#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos) /**< \brief (MCAN_RWD) Watchdog Configuration (read/write) */ +#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos))) +#define MCAN_RWD_WDV_Pos 8 +#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos) /**< \brief (MCAN_RWD) Watchdog Value (read-only) */ +#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos))) +/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */ +#define MCAN_CCCR_INIT (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization (read/write) */ +#define MCAN_CCCR_INIT_DISABLED (0x0u << 0) /**< \brief (MCAN_CCCR) Normal operation. */ +#define MCAN_CCCR_INIT_ENABLED (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization is started. */ +#define MCAN_CCCR_CCE (0x1u << 1) /**< \brief (MCAN_CCCR) Configuration Change Enable (read/write, write protection) */ +#define MCAN_CCCR_CCE_PROTECTED (0x0u << 1) /**< \brief (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ +#define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1) /**< \brief (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ +#define MCAN_CCCR_ASM (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_ASM_NORMAL (0x0u << 2) /**< \brief (MCAN_CCCR) Normal CAN operation. */ +#define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted operation mode active. */ +#define MCAN_CCCR_CSA (0x1u << 3) /**< \brief (MCAN_CCCR) Clock Stop Acknowledge (read-only) */ +#define MCAN_CCCR_CSR (0x1u << 4) /**< \brief (MCAN_CCCR) Clock Stop Request (read/write) */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4) /**< \brief (MCAN_CCCR) No clock stop is requested. */ +#define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4) /**< \brief (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ +#define MCAN_CCCR_MON (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_MON_DISABLED (0x0u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is disabled. */ +#define MCAN_CCCR_MON_ENABLED (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is enabled. */ +#define MCAN_CCCR_DAR (0x1u << 6) /**< \brief (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) */ +#define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission disabled. */ +#define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */ +#define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ +#define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ +#define MCAN_CCCR_CME_Pos 8 +#define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /**< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) */ +#define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos))) +#define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /**< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */ +#define MCAN_CCCR_CME_FD (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD operation enabled */ +#define MCAN_CCCR_CMR_Pos 10 +#define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos) /**< \brief (MCAN_CCCR) CAN Mode Request (read/write) */ +#define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos))) +#define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10) /**< \brief (MCAN_CCCR) No mode change */ +#define MCAN_CCCR_CMR_FD (0x1u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation */ +#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation with bit rate switching */ +#define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10) /**< \brief (MCAN_CCCR) Request CAN operation according ISO11898-1 */ +#define MCAN_CCCR_FDO (0x1u << 12) /**< \brief (MCAN_CCCR) CAN FD Operation (read-only) */ +#define MCAN_CCCR_FDBS (0x1u << 13) /**< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) */ +#define MCAN_CCCR_FDOE (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD Operation Enable (read/write, write protection) */ +#define MCAN_CCCR_FDOE_DISABLED (0x0u << 8) /**< \brief (MCAN_CCCR) FD operation disabled. */ +#define MCAN_CCCR_FDOE_ENABLED (0x1u << 8) /**< \brief (MCAN_CCCR) FD operation enabled. */ +#define MCAN_CCCR_BRSE (0x1u << 9) /**< \brief (MCAN_CCCR) Bit Rate Switching Enable (read/write, write protection) */ +#define MCAN_CCCR_BRSE_DISABLED (0x0u << 9) /**< \brief (MCAN_CCCR) Bit rate switching for transmissions disabled. */ +#define MCAN_CCCR_BRSE_ENABLED (0x1u << 9) /**< \brief (MCAN_CCCR) Bit rate switching for transmissions enabled. */ +#define MCAN_CCCR_PXHD (0x1u << 12) /**< \brief (MCAN_CCCR) Protocol Exception Event Handling (read/write, write protection) */ +#define MCAN_CCCR_EFBI (0x1u << 13) /**< \brief (MCAN_CCCR) Edge Filtering during Bus Integration (read/write, write protection) */ +#define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */ +#define MCAN_CCCR_NISO (0x1u << 15) /**< \brief (MCAN_CCCR) Non-ISO Operation */ +/* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */ +#define MCAN_BTP_SJW_Pos 0 +#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ +#define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos))) +#define MCAN_BTP_TSEG2_Pos 4 +#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ +#define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos))) +#define MCAN_BTP_TSEG1_Pos 8 +#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ +#define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos))) +#define MCAN_BTP_BRP_Pos 16 +#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ +#define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos))) +/* -------- MCAN_NBTP : (MCAN Offset: 0x1C) Nominal Bit Timing and Prescaler Register -------- */ +#define MCAN_NBTP_NTSEG2_Pos 0 +#define MCAN_NBTP_NTSEG2_Msk (0x7fu << MCAN_NBTP_NTSEG2_Pos) /**< \brief (MCAN_NBTP) Nominal Time Segment After Sample Point */ +#define MCAN_NBTP_NTSEG2(value) ((MCAN_NBTP_NTSEG2_Msk & ((value) << MCAN_NBTP_NTSEG2_Pos))) +#define MCAN_NBTP_NTSEG1_Pos 8 +#define MCAN_NBTP_NTSEG1_Msk (0xffu << MCAN_NBTP_NTSEG1_Pos) /**< \brief (MCAN_NBTP) Nominal Time Segment Before Sample Point */ +#define MCAN_NBTP_NTSEG1(value) ((MCAN_NBTP_NTSEG1_Msk & ((value) << MCAN_NBTP_NTSEG1_Pos))) +#define MCAN_NBTP_NBRP_Pos 16 +#define MCAN_NBTP_NBRP_Msk (0x1ffu << MCAN_NBTP_NBRP_Pos) /**< \brief (MCAN_NBTP) Nominal Bit Rate Prescaler */ +#define MCAN_NBTP_NBRP(value) ((MCAN_NBTP_NBRP_Msk & ((value) << MCAN_NBTP_NBRP_Pos))) +#define MCAN_NBTP_NSJW_Pos 25 +#define MCAN_NBTP_NSJW_Msk (0x7fu << MCAN_NBTP_NSJW_Pos) /**< \brief (MCAN_NBTP) Nominal (Re) Synchronization Jump Width */ +#define MCAN_NBTP_NSJW(value) ((MCAN_NBTP_NSJW_Msk & ((value) << MCAN_NBTP_NSJW_Pos))) +/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */ +#define MCAN_TSCC_TSS_Pos 0 +#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos) /**< \brief (MCAN_TSCC) Timestamp Select */ +#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos))) +#define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value always 0x0000 */ +#define MCAN_TSCC_TSS_TCP_INC (0x1u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value incremented according to TCP */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0) /**< \brief (MCAN_TSCC) External timestamp counter value used */ +#define MCAN_TSCC_TCP_Pos 16 +#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos) /**< \brief (MCAN_TSCC) Timestamp Counter Prescaler */ +#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos))) +/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */ +#define MCAN_TSCV_TSC_Pos 0 +#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos) /**< \brief (MCAN_TSCV) Timestamp Counter (cleared on write) */ +#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos))) +/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */ +#define MCAN_TOCC_ETOC (0x1u << 0) /**< \brief (MCAN_TOCC) Enable Timeout Counter */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0) /**< \brief (MCAN_TOCC) Timeout Counter disabled. */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0) /**< \brief (MCAN_TOCC) Timeout Counter enabled. */ +#define MCAN_TOCC_TOS_Pos 1 +#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos) /**< \brief (MCAN_TOCC) Timeout Select */ +#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos))) +#define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1) /**< \brief (MCAN_TOCC) Continuous operation */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ +#define MCAN_TOCC_TOP_Pos 16 +#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos) /**< \brief (MCAN_TOCC) Timeout Period */ +#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos))) +/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */ +#define MCAN_TOCV_TOC_Pos 0 +#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos) /**< \brief (MCAN_TOCV) Timeout Counter (cleared on write) */ +#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos))) +/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */ +#define MCAN_ECR_TEC_Pos 0 +#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos) /**< \brief (MCAN_ECR) Transmit Error Counter */ +#define MCAN_ECR_REC_Pos 8 +#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos) /**< \brief (MCAN_ECR) Receive Error Counter */ +#define MCAN_ECR_RP (0x1u << 15) /**< \brief (MCAN_ECR) Receive Error Passive */ +#define MCAN_ECR_CEL_Pos 16 +#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos) /**< \brief (MCAN_ECR) CAN Error Logging (cleared on read) */ +/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */ +#define MCAN_PSR_LEC_Pos 0 +#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos) /**< \brief (MCAN_PSR) Last Error Code (set to 111 on read) */ +#define MCAN_PSR_LEC_NO_ERROR (0x0u << 0) /**< \brief (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ +#define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0) /**< \brief (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received meSsage where this is not allowed. */ +#define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0) /**< \brief (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ +#define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0) /**< \brief (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ +#define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ +#define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ +#define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0) /**< \brief (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. */ +#define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0) /**< \brief (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ +#define MCAN_PSR_ACT_Pos 3 +#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos) /**< \brief (MCAN_PSR) Activity */ +#define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3) /**< \brief (MCAN_PSR) Node is synchronizing on CAN communication */ +#define MCAN_PSR_ACT_IDLE (0x1u << 3) /**< \brief (MCAN_PSR) Node is neither receiver nor transmitter */ +#define MCAN_PSR_ACT_RECEIVER (0x2u << 3) /**< \brief (MCAN_PSR) Node is operating as receiver */ +#define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3) /**< \brief (MCAN_PSR) Node is operating as transmitter */ +#define MCAN_PSR_EP (0x1u << 5) /**< \brief (MCAN_PSR) Error Passive */ +#define MCAN_PSR_EW (0x1u << 6) /**< \brief (MCAN_PSR) Warning Status */ +#define MCAN_PSR_BO (0x1u << 7) /**< \brief (MCAN_PSR) Bus_Off Status */ +#define MCAN_PSR_FLEC_Pos 8 +#define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos) /**< \brief (MCAN_PSR) Fast Last Error Code (set to 111 on read) */ +#define MCAN_PSR_DLEC_Pos 8 +#define MCAN_PSR_DLEC_Msk (0x7u << MCAN_PSR_DLEC_Pos) /**< \brief (MCAN_PSR) Data Phase Last Error Code (set to 111 on read) */ +#define MCAN_PSR_RESI (0x1u << 11) /**< \brief (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_RBRS (0x1u << 12) /**< \brief (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_REDL (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */ +#define MCAN_PSR_RFDF (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */ +#define MCAN_PSR_PXE (0x1u << 14) /**< \brief (MCAN_PSR) Protocol Exception Event (cleared on read) */ +#define MCAN_PSR_TDCV_Pos 16 +#define MCAN_PSR_TDCV_Msk (0x7fu << MCAN_PSR_TDCV_Pos) /**< \brief (MCAN_PSR) Transmitter Delay Compensation Value */ +/* -------- MCAN_TDCR : (MCAN Offset: 0x48) Transmit Delay Compensation Register -------- */ +#define MCAN_TDCR_TDCF_Pos 0 +#define MCAN_TDCR_TDCF_Msk (0x7fu << MCAN_TDCR_TDCF_Pos) /**< \brief (MCAN_TDCR) Transmitter Delay Compensation Filter */ +#define MCAN_TDCR_TDCF(value) ((MCAN_TDCR_TDCF_Msk & ((value) << MCAN_TDCR_TDCF_Pos))) +#define MCAN_TDCR_TDCO_Pos 8 +#define MCAN_TDCR_TDCO_Msk (0x7fu << MCAN_TDCR_TDCO_Pos) /**< \brief (MCAN_TDCR) Transmitter Delay Compensation Offset */ +#define MCAN_TDCR_TDCO(value) ((MCAN_TDCR_TDCO_Msk & ((value) << MCAN_TDCR_TDCO_Pos))) +/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */ +#define MCAN_IR_RF0N (0x1u << 0) /**< \brief (MCAN_IR) Receive FIFO 0 New Message */ +#define MCAN_IR_RF0W (0x1u << 1) /**< \brief (MCAN_IR) Receive FIFO 0 Watermark Reached */ +#define MCAN_IR_RF0F (0x1u << 2) /**< \brief (MCAN_IR) Receive FIFO 0 Full */ +#define MCAN_IR_RF0L (0x1u << 3) /**< \brief (MCAN_IR) Receive FIFO 0 Message Lost */ +#define MCAN_IR_RF1N (0x1u << 4) /**< \brief (MCAN_IR) Receive FIFO 1 New Message */ +#define MCAN_IR_RF1W (0x1u << 5) /**< \brief (MCAN_IR) Receive FIFO 1 Watermark Reached */ +#define MCAN_IR_RF1F (0x1u << 6) /**< \brief (MCAN_IR) Receive FIFO 1 Full */ +#define MCAN_IR_RF1L (0x1u << 7) /**< \brief (MCAN_IR) Receive FIFO 1 Message Lost */ +#define MCAN_IR_HPM (0x1u << 8) /**< \brief (MCAN_IR) High Priority Message */ +#define MCAN_IR_TC (0x1u << 9) /**< \brief (MCAN_IR) Transmission Completed */ +#define MCAN_IR_TCF (0x1u << 10) /**< \brief (MCAN_IR) Transmission Cancellation Finished */ +#define MCAN_IR_TFE (0x1u << 11) /**< \brief (MCAN_IR) Tx FIFO Empty */ +#define MCAN_IR_TEFN (0x1u << 12) /**< \brief (MCAN_IR) Tx Event FIFO New Entry */ +#define MCAN_IR_TEFW (0x1u << 13) /**< \brief (MCAN_IR) Tx Event FIFO Watermark Reached */ +#define MCAN_IR_TEFF (0x1u << 14) /**< \brief (MCAN_IR) Tx Event FIFO Full */ +#define MCAN_IR_TEFL (0x1u << 15) /**< \brief (MCAN_IR) Tx Event FIFO Element Lost */ +#define MCAN_IR_TSW (0x1u << 16) /**< \brief (MCAN_IR) Timestamp Wraparound */ +#define MCAN_IR_MRAF (0x1u << 17) /**< \brief (MCAN_IR) Message RAM Access Failure */ +#define MCAN_IR_TOO (0x1u << 18) /**< \brief (MCAN_IR) Timeout Occurred */ +#define MCAN_IR_DRX (0x1u << 19) /**< \brief (MCAN_IR) Message stored to Dedicated Receive Buffer */ +#define MCAN_IR_ELO (0x1u << 22) /**< \brief (MCAN_IR) Error Logging Overflow */ +#define MCAN_IR_EP (0x1u << 23) /**< \brief (MCAN_IR) Error Passive */ +#define MCAN_IR_EW (0x1u << 24) /**< \brief (MCAN_IR) Warning Status */ +#define MCAN_IR_BO (0x1u << 25) /**< \brief (MCAN_IR) Bus_Off Status */ +#define MCAN_IR_WDI (0x1u << 26) /**< \brief (MCAN_IR) Watchdog Interrupt */ +#define MCAN_IR_CRCE (0x1u << 27) /**< \brief (MCAN_IR) CRC Error */ +#define MCAN_IR_BE (0x1u << 28) /**< \brief (MCAN_IR) Bit Error */ +#define MCAN_IR_ACKE (0x1u << 29) /**< \brief (MCAN_IR) Acknowledge Error */ +#define MCAN_IR_FOE (0x1u << 30) /**< \brief (MCAN_IR) Format Error */ +#define MCAN_IR_STE (0x1u << 31) /**< \brief (MCAN_IR) Stuff Error */ +#define MCAN_IR_PEA (0x1u << 27) /**< \brief (MCAN_IR) Protocol Error in Arbitration Phase */ +#define MCAN_IR_PED (0x1u << 28) /**< \brief (MCAN_IR) Protocol Error in Data Phase */ +#define MCAN_IR_ARA (0x1u << 29) /**< \brief (MCAN_IR) Access to Reserved Address */ +/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */ +#define MCAN_IE_RF0NE (0x1u << 0) /**< \brief (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable */ +#define MCAN_IE_RF0WE (0x1u << 1) /**< \brief (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF0FE (0x1u << 2) /**< \brief (MCAN_IE) Receive FIFO 0 Full Interrupt Enable */ +#define MCAN_IE_RF0LE (0x1u << 3) /**< \brief (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable */ +#define MCAN_IE_RF1NE (0x1u << 4) /**< \brief (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable */ +#define MCAN_IE_RF1WE (0x1u << 5) /**< \brief (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF1FE (0x1u << 6) /**< \brief (MCAN_IE) Receive FIFO 1 Full Interrupt Enable */ +#define MCAN_IE_RF1LE (0x1u << 7) /**< \brief (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable */ +#define MCAN_IE_HPME (0x1u << 8) /**< \brief (MCAN_IE) High Priority Message Interrupt Enable */ +#define MCAN_IE_TCE (0x1u << 9) /**< \brief (MCAN_IE) Transmission Completed Interrupt Enable */ +#define MCAN_IE_TCFE (0x1u << 10) /**< \brief (MCAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define MCAN_IE_TFEE (0x1u << 11) /**< \brief (MCAN_IE) Tx FIFO Empty Interrupt Enable */ +#define MCAN_IE_TEFNE (0x1u << 12) /**< \brief (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define MCAN_IE_TEFWE (0x1u << 13) /**< \brief (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define MCAN_IE_TEFFE (0x1u << 14) /**< \brief (MCAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define MCAN_IE_TEFLE (0x1u << 15) /**< \brief (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable */ +#define MCAN_IE_TSWE (0x1u << 16) /**< \brief (MCAN_IE) Timestamp Wraparound Interrupt Enable */ +#define MCAN_IE_MRAFE (0x1u << 17) /**< \brief (MCAN_IE) Message RAM Access Failure Interrupt Enable */ +#define MCAN_IE_TOOE (0x1u << 18) /**< \brief (MCAN_IE) Timeout Occurred Interrupt Enable */ +#define MCAN_IE_DRXE (0x1u << 19) /**< \brief (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable */ +#define MCAN_IE_ELOE (0x1u << 22) /**< \brief (MCAN_IE) Error Logging Overflow Interrupt Enable */ +#define MCAN_IE_EPE (0x1u << 23) /**< \brief (MCAN_IE) Error Passive Interrupt Enable */ +#define MCAN_IE_EWE (0x1u << 24) /**< \brief (MCAN_IE) Warning Status Interrupt Enable */ +#define MCAN_IE_BOE (0x1u << 25) /**< \brief (MCAN_IE) Bus_Off Status Interrupt Enable */ +#define MCAN_IE_WDIE (0x1u << 26) /**< \brief (MCAN_IE) Watchdog Interrupt Enable */ +#define MCAN_IE_CRCEE (0x1u << 27) /**< \brief (MCAN_IE) CRC Error Interrupt Enable */ +#define MCAN_IE_BEE (0x1u << 28) /**< \brief (MCAN_IE) Bit Error Interrupt Enable */ +#define MCAN_IE_ACKEE (0x1u << 29) /**< \brief (MCAN_IE) Acknowledge Error Interrupt Enable */ +#define MCAN_IE_FOEE (0x1u << 30) /**< \brief (MCAN_IE) Format Error Interrupt Enable */ +#define MCAN_IE_STEE (0x1u << 31) /**< \brief (MCAN_IE) Stuff Error Interrupt Enable */ +#define MCAN_IE_PEAE (0x1u << 27) /**< \brief (MCAN_IE) Protocol Error in Arbitration Phase Enable */ +#define MCAN_IE_PEDE (0x1u << 28) /**< \brief (MCAN_IE) Protocol Error in Data Phase Enable */ +#define MCAN_IE_ARAE (0x1u << 29) /**< \brief (MCAN_IE) Access to Reserved Address Enable */ +/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */ +#define MCAN_ILS_RF0NL (0x1u << 0) /**< \brief (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line */ +#define MCAN_ILS_RF0WL (0x1u << 1) /**< \brief (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF0FL (0x1u << 2) /**< \brief (MCAN_ILS) Receive FIFO 0 Full Interrupt Line */ +#define MCAN_ILS_RF0LL (0x1u << 3) /**< \brief (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line */ +#define MCAN_ILS_RF1NL (0x1u << 4) /**< \brief (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line */ +#define MCAN_ILS_RF1WL (0x1u << 5) /**< \brief (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF1FL (0x1u << 6) /**< \brief (MCAN_ILS) Receive FIFO 1 Full Interrupt Line */ +#define MCAN_ILS_RF1LL (0x1u << 7) /**< \brief (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line */ +#define MCAN_ILS_HPML (0x1u << 8) /**< \brief (MCAN_ILS) High Priority Message Interrupt Line */ +#define MCAN_ILS_TCL (0x1u << 9) /**< \brief (MCAN_ILS) Transmission Completed Interrupt Line */ +#define MCAN_ILS_TCFL (0x1u << 10) /**< \brief (MCAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define MCAN_ILS_TFEL (0x1u << 11) /**< \brief (MCAN_ILS) Tx FIFO Empty Interrupt Line */ +#define MCAN_ILS_TEFNL (0x1u << 12) /**< \brief (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define MCAN_ILS_TEFWL (0x1u << 13) /**< \brief (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define MCAN_ILS_TEFFL (0x1u << 14) /**< \brief (MCAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define MCAN_ILS_TEFLL (0x1u << 15) /**< \brief (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line */ +#define MCAN_ILS_TSWL (0x1u << 16) /**< \brief (MCAN_ILS) Timestamp Wraparound Interrupt Line */ +#define MCAN_ILS_MRAFL (0x1u << 17) /**< \brief (MCAN_ILS) Message RAM Access Failure Interrupt Line */ +#define MCAN_ILS_TOOL (0x1u << 18) /**< \brief (MCAN_ILS) Timeout Occurred Interrupt Line */ +#define MCAN_ILS_DRXL (0x1u << 19) /**< \brief (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line */ +#define MCAN_ILS_ELOL (0x1u << 22) /**< \brief (MCAN_ILS) Error Logging Overflow Interrupt Line */ +#define MCAN_ILS_EPL (0x1u << 23) /**< \brief (MCAN_ILS) Error Passive Interrupt Line */ +#define MCAN_ILS_EWL (0x1u << 24) /**< \brief (MCAN_ILS) Warning Status Interrupt Line */ +#define MCAN_ILS_BOL (0x1u << 25) /**< \brief (MCAN_ILS) Bus_Off Status Interrupt Line */ +#define MCAN_ILS_WDIL (0x1u << 26) /**< \brief (MCAN_ILS) Watchdog Interrupt Line */ +#define MCAN_ILS_CRCEL (0x1u << 27) /**< \brief (MCAN_ILS) CRC Error Interrupt Line */ +#define MCAN_ILS_BEL (0x1u << 28) /**< \brief (MCAN_ILS) Bit Error Interrupt Line */ +#define MCAN_ILS_ACKEL (0x1u << 29) /**< \brief (MCAN_ILS) Acknowledge Error Interrupt Line */ +#define MCAN_ILS_FOEL (0x1u << 30) /**< \brief (MCAN_ILS) Format Error Interrupt Line */ +#define MCAN_ILS_STEL (0x1u << 31) /**< \brief (MCAN_ILS) Stuff Error Interrupt Line */ +#define MCAN_ILS_PEAL (0x1u << 27) /**< \brief (MCAN_ILS) Protocol Error in Arbitration Phase Line */ +#define MCAN_ILS_PEDL (0x1u << 28) /**< \brief (MCAN_ILS) Protocol Error in Data Phase Line */ +#define MCAN_ILS_ARAL (0x1u << 29) /**< \brief (MCAN_ILS) Access to Reserved Address Line */ +/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */ +#define MCAN_ILE_EINT0 (0x1u << 0) /**< \brief (MCAN_ILE) Enable Interrupt Line 0 */ +#define MCAN_ILE_EINT1 (0x1u << 1) /**< \brief (MCAN_ILE) Enable Interrupt Line 1 */ +/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */ +#define MCAN_GFC_RRFE (0x1u << 0) /**< \brief (MCAN_GFC) Reject Remote Frames Extended */ +#define MCAN_GFC_RRFE_FILTER (0x0u << 0) /**< \brief (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_REJECT (0x1u << 0) /**< \brief (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFS (0x1u << 1) /**< \brief (MCAN_GFC) Reject Remote Frames Standard */ +#define MCAN_GFC_RRFS_FILTER (0x0u << 1) /**< \brief (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_REJECT (0x1u << 1) /**< \brief (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_ANFE_Pos 2 +#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Extended */ +#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos))) +#define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +#define MCAN_GFC_ANFS_Pos 4 +#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Standard */ +#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos))) +#define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */ +#define MCAN_SIDFC_FLSSA_Pos 2 +#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos) /**< \brief (MCAN_SIDFC) Filter List Standard Start Address */ +#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos))) +#define MCAN_SIDFC_LSS_Pos 16 +#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos) /**< \brief (MCAN_SIDFC) List Size Standard */ +#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos))) +/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */ +#define MCAN_XIDFC_FLESA_Pos 2 +#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos) /**< \brief (MCAN_XIDFC) Filter List Extended Start Address */ +#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos))) +#define MCAN_XIDFC_LSE_Pos 16 +#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos) /**< \brief (MCAN_XIDFC) List Size Extended */ +#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos))) +/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */ +#define MCAN_XIDAM_EIDM_Pos 0 +#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos) /**< \brief (MCAN_XIDAM) Extended ID Mask */ +#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos))) +/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */ +#define MCAN_HPMS_BIDX_Pos 0 +#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos) /**< \brief (MCAN_HPMS) Buffer Index */ +#define MCAN_HPMS_MSI_Pos 6 +#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos) /**< \brief (MCAN_HPMS) Message Storage Indicator */ +#define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6) /**< \brief (MCAN_HPMS) No FIFO selected. */ +#define MCAN_HPMS_MSI_LOST (0x1u << 6) /**< \brief (MCAN_HPMS) FIFO message lost. */ +#define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 0. */ +#define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 1. */ +#define MCAN_HPMS_FIDX_Pos 8 +#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos) /**< \brief (MCAN_HPMS) Filter Index */ +#define MCAN_HPMS_FLST (0x1u << 15) /**< \brief (MCAN_HPMS) Filter List */ +/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */ +#define MCAN_NDAT1_ND0 (0x1u << 0) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND1 (0x1u << 1) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND2 (0x1u << 2) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND3 (0x1u << 3) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND4 (0x1u << 4) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND5 (0x1u << 5) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND6 (0x1u << 6) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND7 (0x1u << 7) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND8 (0x1u << 8) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND9 (0x1u << 9) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND10 (0x1u << 10) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND11 (0x1u << 11) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND12 (0x1u << 12) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND13 (0x1u << 13) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND14 (0x1u << 14) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND15 (0x1u << 15) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND16 (0x1u << 16) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND17 (0x1u << 17) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND18 (0x1u << 18) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND19 (0x1u << 19) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND20 (0x1u << 20) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND21 (0x1u << 21) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND22 (0x1u << 22) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND23 (0x1u << 23) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND24 (0x1u << 24) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND25 (0x1u << 25) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND26 (0x1u << 26) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND27 (0x1u << 27) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND28 (0x1u << 28) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND29 (0x1u << 29) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND30 (0x1u << 30) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND31 (0x1u << 31) /**< \brief (MCAN_NDAT1) New Data */ +/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */ +#define MCAN_NDAT2_ND32 (0x1u << 0) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND33 (0x1u << 1) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND34 (0x1u << 2) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND35 (0x1u << 3) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND36 (0x1u << 4) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND37 (0x1u << 5) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND38 (0x1u << 6) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND39 (0x1u << 7) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND40 (0x1u << 8) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND41 (0x1u << 9) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND42 (0x1u << 10) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND43 (0x1u << 11) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND44 (0x1u << 12) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND45 (0x1u << 13) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND46 (0x1u << 14) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND47 (0x1u << 15) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND48 (0x1u << 16) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND49 (0x1u << 17) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND50 (0x1u << 18) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND51 (0x1u << 19) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND52 (0x1u << 20) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND53 (0x1u << 21) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND54 (0x1u << 22) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND55 (0x1u << 23) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND56 (0x1u << 24) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND57 (0x1u << 25) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND58 (0x1u << 26) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND59 (0x1u << 27) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND60 (0x1u << 28) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND61 (0x1u << 29) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND62 (0x1u << 30) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND63 (0x1u << 31) /**< \brief (MCAN_NDAT2) New Data */ +/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */ +#define MCAN_RXF0C_F0SA_Pos 2 +#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos))) +#define MCAN_RXF0C_F0S_Pos 16 +#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos))) +#define MCAN_RXF0C_F0WM_Pos 24 +#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Watermark */ +#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos))) +#define MCAN_RXF0C_F0OM (0x1u << 31) /**< \brief (MCAN_RXF0C) FIFO 0 Operation Mode */ +/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */ +#define MCAN_RXF0S_F0FL_Pos 0 +#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_F0GI_Pos 8 +#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Get Index */ +#define MCAN_RXF0S_F0PI_Pos 16 +#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Put Index */ +#define MCAN_RXF0S_F0F (0x1u << 24) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_RF0L (0x1u << 25) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Message Lost */ +/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */ +#define MCAN_RXF0A_F0AI_Pos 0 +#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos) /**< \brief (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index */ +#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos))) +/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */ +#define MCAN_RXBC_RBSA_Pos 2 +#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos) /**< \brief (MCAN_RXBC) Receive Buffer Start Address */ +#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos))) +/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */ +#define MCAN_RXF1C_F1SA_Pos 2 +#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos))) +#define MCAN_RXF1C_F1S_Pos 16 +#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos))) +#define MCAN_RXF1C_F1WM_Pos 24 +#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Watermark */ +#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos))) +#define MCAN_RXF1C_F1OM (0x1u << 31) /**< \brief (MCAN_RXF1C) FIFO 1 Operation Mode */ +/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */ +#define MCAN_RXF1S_F1FL_Pos 0 +#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_F1GI_Pos 8 +#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Get Index */ +#define MCAN_RXF1S_F1PI_Pos 16 +#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Put Index */ +#define MCAN_RXF1S_F1F (0x1u << 24) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_RF1L (0x1u << 25) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Message Lost */ +#define MCAN_RXF1S_DMS_Pos 30 +#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos) /**< \brief (MCAN_RXF1S) Debug Message Status */ +#define MCAN_RXF1S_DMS_IDLE (0x0u << 30) /**< \brief (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ +#define MCAN_RXF1S_DMS_MSG_A (0x1u << 30) /**< \brief (MCAN_RXF1S) Debug message A received. */ +#define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B received. */ +#define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ +/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */ +#define MCAN_RXF1A_F1AI_Pos 0 +#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos) /**< \brief (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index */ +#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos))) +/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */ +#define MCAN_RXESC_F0DS_Pos 0 +#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 0 Data Field Size */ +#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos))) +#define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F1DS_Pos 4 +#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 1 Data Field Size */ +#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos))) +#define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_RBDS_Pos 8 +#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos) /**< \brief (MCAN_RXESC) Receive Buffer Data Field Size */ +#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos))) +#define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8) /**< \brief (MCAN_RXESC) 64-byte data field */ +/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */ +#define MCAN_TXBC_TBSA_Pos 2 +#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos) /**< \brief (MCAN_TXBC) Tx Buffers Start Address */ +#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos))) +#define MCAN_TXBC_NDTB_Pos 16 +#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos) /**< \brief (MCAN_TXBC) Number of Dedicated Transmit Buffers */ +#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos))) +#define MCAN_TXBC_TFQS_Pos 24 +#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos) /**< \brief (MCAN_TXBC) Transmit FIFO/Queue Size */ +#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos))) +#define MCAN_TXBC_TFQM (0x1u << 30) /**< \brief (MCAN_TXBC) Tx FIFO/Queue Mode */ +/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */ +#define MCAN_TXFQS_TFFL_Pos 0 +#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Free Level */ +#define MCAN_TXFQS_TFGI_Pos 8 +#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Get Index */ +#define MCAN_TXFQS_TFQPI_Pos 16 +#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Put Index */ +#define MCAN_TXFQS_TFQF (0x1u << 21) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Full */ +/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */ +#define MCAN_TXESC_TBDS_Pos 0 +#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos) /**< \brief (MCAN_TXESC) Tx Buffer Data Field Size */ +#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos))) +#define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0) /**< \brief (MCAN_TXESC) 8-byte data field */ +#define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0) /**< \brief (MCAN_TXESC) 12-byte data field */ +#define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0) /**< \brief (MCAN_TXESC) 16-byte data field */ +#define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0) /**< \brief (MCAN_TXESC) 20-byte data field */ +#define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0) /**< \brief (MCAN_TXESC) 24-byte data field */ +#define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0) /**< \brief (MCAN_TXESC) 32-byte data field */ +#define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0) /**< \brief (MCAN_TXESC) 48- byte data field */ +#define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0) /**< \brief (MCAN_TXESC) 64-byte data field */ +/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */ +#define MCAN_TXBRP_TRP0 (0x1u << 0) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 0 */ +#define MCAN_TXBRP_TRP1 (0x1u << 1) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 1 */ +#define MCAN_TXBRP_TRP2 (0x1u << 2) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 2 */ +#define MCAN_TXBRP_TRP3 (0x1u << 3) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 3 */ +#define MCAN_TXBRP_TRP4 (0x1u << 4) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 4 */ +#define MCAN_TXBRP_TRP5 (0x1u << 5) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 5 */ +#define MCAN_TXBRP_TRP6 (0x1u << 6) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 6 */ +#define MCAN_TXBRP_TRP7 (0x1u << 7) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 7 */ +#define MCAN_TXBRP_TRP8 (0x1u << 8) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 8 */ +#define MCAN_TXBRP_TRP9 (0x1u << 9) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 9 */ +#define MCAN_TXBRP_TRP10 (0x1u << 10) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 10 */ +#define MCAN_TXBRP_TRP11 (0x1u << 11) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 11 */ +#define MCAN_TXBRP_TRP12 (0x1u << 12) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 12 */ +#define MCAN_TXBRP_TRP13 (0x1u << 13) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 13 */ +#define MCAN_TXBRP_TRP14 (0x1u << 14) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 14 */ +#define MCAN_TXBRP_TRP15 (0x1u << 15) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 15 */ +#define MCAN_TXBRP_TRP16 (0x1u << 16) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 16 */ +#define MCAN_TXBRP_TRP17 (0x1u << 17) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 17 */ +#define MCAN_TXBRP_TRP18 (0x1u << 18) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 18 */ +#define MCAN_TXBRP_TRP19 (0x1u << 19) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 19 */ +#define MCAN_TXBRP_TRP20 (0x1u << 20) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 20 */ +#define MCAN_TXBRP_TRP21 (0x1u << 21) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 21 */ +#define MCAN_TXBRP_TRP22 (0x1u << 22) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 22 */ +#define MCAN_TXBRP_TRP23 (0x1u << 23) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 23 */ +#define MCAN_TXBRP_TRP24 (0x1u << 24) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 24 */ +#define MCAN_TXBRP_TRP25 (0x1u << 25) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 25 */ +#define MCAN_TXBRP_TRP26 (0x1u << 26) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 26 */ +#define MCAN_TXBRP_TRP27 (0x1u << 27) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 27 */ +#define MCAN_TXBRP_TRP28 (0x1u << 28) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 28 */ +#define MCAN_TXBRP_TRP29 (0x1u << 29) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 29 */ +#define MCAN_TXBRP_TRP30 (0x1u << 30) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 30 */ +#define MCAN_TXBRP_TRP31 (0x1u << 31) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 31 */ +/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */ +#define MCAN_TXBAR_AR0 (0x1u << 0) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 0 */ +#define MCAN_TXBAR_AR1 (0x1u << 1) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 1 */ +#define MCAN_TXBAR_AR2 (0x1u << 2) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 2 */ +#define MCAN_TXBAR_AR3 (0x1u << 3) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 3 */ +#define MCAN_TXBAR_AR4 (0x1u << 4) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 4 */ +#define MCAN_TXBAR_AR5 (0x1u << 5) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 5 */ +#define MCAN_TXBAR_AR6 (0x1u << 6) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 6 */ +#define MCAN_TXBAR_AR7 (0x1u << 7) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 7 */ +#define MCAN_TXBAR_AR8 (0x1u << 8) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 8 */ +#define MCAN_TXBAR_AR9 (0x1u << 9) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 9 */ +#define MCAN_TXBAR_AR10 (0x1u << 10) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 10 */ +#define MCAN_TXBAR_AR11 (0x1u << 11) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 11 */ +#define MCAN_TXBAR_AR12 (0x1u << 12) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 12 */ +#define MCAN_TXBAR_AR13 (0x1u << 13) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 13 */ +#define MCAN_TXBAR_AR14 (0x1u << 14) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 14 */ +#define MCAN_TXBAR_AR15 (0x1u << 15) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 15 */ +#define MCAN_TXBAR_AR16 (0x1u << 16) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 16 */ +#define MCAN_TXBAR_AR17 (0x1u << 17) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 17 */ +#define MCAN_TXBAR_AR18 (0x1u << 18) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 18 */ +#define MCAN_TXBAR_AR19 (0x1u << 19) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 19 */ +#define MCAN_TXBAR_AR20 (0x1u << 20) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 20 */ +#define MCAN_TXBAR_AR21 (0x1u << 21) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 21 */ +#define MCAN_TXBAR_AR22 (0x1u << 22) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 22 */ +#define MCAN_TXBAR_AR23 (0x1u << 23) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 23 */ +#define MCAN_TXBAR_AR24 (0x1u << 24) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 24 */ +#define MCAN_TXBAR_AR25 (0x1u << 25) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 25 */ +#define MCAN_TXBAR_AR26 (0x1u << 26) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 26 */ +#define MCAN_TXBAR_AR27 (0x1u << 27) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 27 */ +#define MCAN_TXBAR_AR28 (0x1u << 28) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 28 */ +#define MCAN_TXBAR_AR29 (0x1u << 29) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 29 */ +#define MCAN_TXBAR_AR30 (0x1u << 30) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 30 */ +#define MCAN_TXBAR_AR31 (0x1u << 31) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */ +#define MCAN_TXBCR_CR0 (0x1u << 0) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 */ +#define MCAN_TXBCR_CR1 (0x1u << 1) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 */ +#define MCAN_TXBCR_CR2 (0x1u << 2) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 */ +#define MCAN_TXBCR_CR3 (0x1u << 3) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 */ +#define MCAN_TXBCR_CR4 (0x1u << 4) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 */ +#define MCAN_TXBCR_CR5 (0x1u << 5) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 */ +#define MCAN_TXBCR_CR6 (0x1u << 6) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 */ +#define MCAN_TXBCR_CR7 (0x1u << 7) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 */ +#define MCAN_TXBCR_CR8 (0x1u << 8) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 */ +#define MCAN_TXBCR_CR9 (0x1u << 9) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 */ +#define MCAN_TXBCR_CR10 (0x1u << 10) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 */ +#define MCAN_TXBCR_CR11 (0x1u << 11) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 */ +#define MCAN_TXBCR_CR12 (0x1u << 12) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 */ +#define MCAN_TXBCR_CR13 (0x1u << 13) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 */ +#define MCAN_TXBCR_CR14 (0x1u << 14) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 */ +#define MCAN_TXBCR_CR15 (0x1u << 15) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 */ +#define MCAN_TXBCR_CR16 (0x1u << 16) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 */ +#define MCAN_TXBCR_CR17 (0x1u << 17) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 */ +#define MCAN_TXBCR_CR18 (0x1u << 18) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 */ +#define MCAN_TXBCR_CR19 (0x1u << 19) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 */ +#define MCAN_TXBCR_CR20 (0x1u << 20) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 */ +#define MCAN_TXBCR_CR21 (0x1u << 21) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 */ +#define MCAN_TXBCR_CR22 (0x1u << 22) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 */ +#define MCAN_TXBCR_CR23 (0x1u << 23) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 */ +#define MCAN_TXBCR_CR24 (0x1u << 24) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 */ +#define MCAN_TXBCR_CR25 (0x1u << 25) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 */ +#define MCAN_TXBCR_CR26 (0x1u << 26) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 */ +#define MCAN_TXBCR_CR27 (0x1u << 27) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 */ +#define MCAN_TXBCR_CR28 (0x1u << 28) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 */ +#define MCAN_TXBCR_CR29 (0x1u << 29) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 */ +#define MCAN_TXBCR_CR30 (0x1u << 30) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 */ +#define MCAN_TXBCR_CR31 (0x1u << 31) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */ +#define MCAN_TXBTO_TO0 (0x1u << 0) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 0 */ +#define MCAN_TXBTO_TO1 (0x1u << 1) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 1 */ +#define MCAN_TXBTO_TO2 (0x1u << 2) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 2 */ +#define MCAN_TXBTO_TO3 (0x1u << 3) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 3 */ +#define MCAN_TXBTO_TO4 (0x1u << 4) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 4 */ +#define MCAN_TXBTO_TO5 (0x1u << 5) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 5 */ +#define MCAN_TXBTO_TO6 (0x1u << 6) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 6 */ +#define MCAN_TXBTO_TO7 (0x1u << 7) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 7 */ +#define MCAN_TXBTO_TO8 (0x1u << 8) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 8 */ +#define MCAN_TXBTO_TO9 (0x1u << 9) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 9 */ +#define MCAN_TXBTO_TO10 (0x1u << 10) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 10 */ +#define MCAN_TXBTO_TO11 (0x1u << 11) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 11 */ +#define MCAN_TXBTO_TO12 (0x1u << 12) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 12 */ +#define MCAN_TXBTO_TO13 (0x1u << 13) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 13 */ +#define MCAN_TXBTO_TO14 (0x1u << 14) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 14 */ +#define MCAN_TXBTO_TO15 (0x1u << 15) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 15 */ +#define MCAN_TXBTO_TO16 (0x1u << 16) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 16 */ +#define MCAN_TXBTO_TO17 (0x1u << 17) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 17 */ +#define MCAN_TXBTO_TO18 (0x1u << 18) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 18 */ +#define MCAN_TXBTO_TO19 (0x1u << 19) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 19 */ +#define MCAN_TXBTO_TO20 (0x1u << 20) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 20 */ +#define MCAN_TXBTO_TO21 (0x1u << 21) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 21 */ +#define MCAN_TXBTO_TO22 (0x1u << 22) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 22 */ +#define MCAN_TXBTO_TO23 (0x1u << 23) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 23 */ +#define MCAN_TXBTO_TO24 (0x1u << 24) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 24 */ +#define MCAN_TXBTO_TO25 (0x1u << 25) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 25 */ +#define MCAN_TXBTO_TO26 (0x1u << 26) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 26 */ +#define MCAN_TXBTO_TO27 (0x1u << 27) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 27 */ +#define MCAN_TXBTO_TO28 (0x1u << 28) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 28 */ +#define MCAN_TXBTO_TO29 (0x1u << 29) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 29 */ +#define MCAN_TXBTO_TO30 (0x1u << 30) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 30 */ +#define MCAN_TXBTO_TO31 (0x1u << 31) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 31 */ +/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */ +#define MCAN_TXBCF_CF0 (0x1u << 0) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 */ +#define MCAN_TXBCF_CF1 (0x1u << 1) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 */ +#define MCAN_TXBCF_CF2 (0x1u << 2) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 */ +#define MCAN_TXBCF_CF3 (0x1u << 3) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 */ +#define MCAN_TXBCF_CF4 (0x1u << 4) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 */ +#define MCAN_TXBCF_CF5 (0x1u << 5) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 */ +#define MCAN_TXBCF_CF6 (0x1u << 6) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 */ +#define MCAN_TXBCF_CF7 (0x1u << 7) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 */ +#define MCAN_TXBCF_CF8 (0x1u << 8) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 */ +#define MCAN_TXBCF_CF9 (0x1u << 9) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 */ +#define MCAN_TXBCF_CF10 (0x1u << 10) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 */ +#define MCAN_TXBCF_CF11 (0x1u << 11) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 */ +#define MCAN_TXBCF_CF12 (0x1u << 12) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 */ +#define MCAN_TXBCF_CF13 (0x1u << 13) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 */ +#define MCAN_TXBCF_CF14 (0x1u << 14) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 */ +#define MCAN_TXBCF_CF15 (0x1u << 15) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 */ +#define MCAN_TXBCF_CF16 (0x1u << 16) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 */ +#define MCAN_TXBCF_CF17 (0x1u << 17) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 */ +#define MCAN_TXBCF_CF18 (0x1u << 18) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 */ +#define MCAN_TXBCF_CF19 (0x1u << 19) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 */ +#define MCAN_TXBCF_CF20 (0x1u << 20) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 */ +#define MCAN_TXBCF_CF21 (0x1u << 21) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 */ +#define MCAN_TXBCF_CF22 (0x1u << 22) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 */ +#define MCAN_TXBCF_CF23 (0x1u << 23) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 */ +#define MCAN_TXBCF_CF24 (0x1u << 24) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 */ +#define MCAN_TXBCF_CF25 (0x1u << 25) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 */ +#define MCAN_TXBCF_CF26 (0x1u << 26) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 */ +#define MCAN_TXBCF_CF27 (0x1u << 27) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 */ +#define MCAN_TXBCF_CF28 (0x1u << 28) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 */ +#define MCAN_TXBCF_CF29 (0x1u << 29) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 */ +#define MCAN_TXBCF_CF30 (0x1u << 30) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 */ +#define MCAN_TXBCF_CF31 (0x1u << 31) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 */ +/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */ +#define MCAN_TXBTIE_TIE0 (0x1u << 0) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 */ +#define MCAN_TXBTIE_TIE1 (0x1u << 1) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 */ +#define MCAN_TXBTIE_TIE2 (0x1u << 2) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 */ +#define MCAN_TXBTIE_TIE3 (0x1u << 3) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 */ +#define MCAN_TXBTIE_TIE4 (0x1u << 4) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 */ +#define MCAN_TXBTIE_TIE5 (0x1u << 5) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 */ +#define MCAN_TXBTIE_TIE6 (0x1u << 6) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 */ +#define MCAN_TXBTIE_TIE7 (0x1u << 7) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 */ +#define MCAN_TXBTIE_TIE8 (0x1u << 8) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 */ +#define MCAN_TXBTIE_TIE9 (0x1u << 9) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 */ +#define MCAN_TXBTIE_TIE10 (0x1u << 10) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 */ +#define MCAN_TXBTIE_TIE11 (0x1u << 11) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 */ +#define MCAN_TXBTIE_TIE12 (0x1u << 12) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 */ +#define MCAN_TXBTIE_TIE13 (0x1u << 13) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 */ +#define MCAN_TXBTIE_TIE14 (0x1u << 14) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 */ +#define MCAN_TXBTIE_TIE15 (0x1u << 15) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 */ +#define MCAN_TXBTIE_TIE16 (0x1u << 16) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 */ +#define MCAN_TXBTIE_TIE17 (0x1u << 17) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 */ +#define MCAN_TXBTIE_TIE18 (0x1u << 18) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 */ +#define MCAN_TXBTIE_TIE19 (0x1u << 19) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 */ +#define MCAN_TXBTIE_TIE20 (0x1u << 20) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 */ +#define MCAN_TXBTIE_TIE21 (0x1u << 21) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 */ +#define MCAN_TXBTIE_TIE22 (0x1u << 22) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 */ +#define MCAN_TXBTIE_TIE23 (0x1u << 23) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 */ +#define MCAN_TXBTIE_TIE24 (0x1u << 24) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 */ +#define MCAN_TXBTIE_TIE25 (0x1u << 25) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 */ +#define MCAN_TXBTIE_TIE26 (0x1u << 26) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 */ +#define MCAN_TXBTIE_TIE27 (0x1u << 27) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 */ +#define MCAN_TXBTIE_TIE28 (0x1u << 28) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 */ +#define MCAN_TXBTIE_TIE29 (0x1u << 29) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 */ +#define MCAN_TXBTIE_TIE30 (0x1u << 30) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 */ +#define MCAN_TXBTIE_TIE31 (0x1u << 31) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 */ +/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ +#define MCAN_TXBCIE_CFIE0 (0x1u << 0) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 */ +#define MCAN_TXBCIE_CFIE1 (0x1u << 1) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 */ +#define MCAN_TXBCIE_CFIE2 (0x1u << 2) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 */ +#define MCAN_TXBCIE_CFIE3 (0x1u << 3) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 */ +#define MCAN_TXBCIE_CFIE4 (0x1u << 4) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 */ +#define MCAN_TXBCIE_CFIE5 (0x1u << 5) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 */ +#define MCAN_TXBCIE_CFIE6 (0x1u << 6) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 */ +#define MCAN_TXBCIE_CFIE7 (0x1u << 7) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 */ +#define MCAN_TXBCIE_CFIE8 (0x1u << 8) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 */ +#define MCAN_TXBCIE_CFIE9 (0x1u << 9) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 */ +#define MCAN_TXBCIE_CFIE10 (0x1u << 10) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 */ +#define MCAN_TXBCIE_CFIE11 (0x1u << 11) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 */ +#define MCAN_TXBCIE_CFIE12 (0x1u << 12) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 */ +#define MCAN_TXBCIE_CFIE13 (0x1u << 13) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 */ +#define MCAN_TXBCIE_CFIE14 (0x1u << 14) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 */ +#define MCAN_TXBCIE_CFIE15 (0x1u << 15) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 */ +#define MCAN_TXBCIE_CFIE16 (0x1u << 16) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 */ +#define MCAN_TXBCIE_CFIE17 (0x1u << 17) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 */ +#define MCAN_TXBCIE_CFIE18 (0x1u << 18) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 */ +#define MCAN_TXBCIE_CFIE19 (0x1u << 19) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 */ +#define MCAN_TXBCIE_CFIE20 (0x1u << 20) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 */ +#define MCAN_TXBCIE_CFIE21 (0x1u << 21) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 */ +#define MCAN_TXBCIE_CFIE22 (0x1u << 22) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 */ +#define MCAN_TXBCIE_CFIE23 (0x1u << 23) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 */ +#define MCAN_TXBCIE_CFIE24 (0x1u << 24) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 */ +#define MCAN_TXBCIE_CFIE25 (0x1u << 25) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 */ +#define MCAN_TXBCIE_CFIE26 (0x1u << 26) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 */ +#define MCAN_TXBCIE_CFIE27 (0x1u << 27) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 */ +#define MCAN_TXBCIE_CFIE28 (0x1u << 28) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 */ +#define MCAN_TXBCIE_CFIE29 (0x1u << 29) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 */ +#define MCAN_TXBCIE_CFIE30 (0x1u << 30) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 */ +#define MCAN_TXBCIE_CFIE31 (0x1u << 31) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 */ +/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */ +#define MCAN_TXEFC_EFSA_Pos 2 +#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Start Address */ +#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos))) +#define MCAN_TXEFC_EFS_Pos 16 +#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Size */ +#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos))) +#define MCAN_TXEFC_EFWM_Pos 24 +#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Watermark */ +#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos))) +/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */ +#define MCAN_TXEFS_EFFL_Pos 0 +#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Fill Level */ +#define MCAN_TXEFS_EFGI_Pos 8 +#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Get Index */ +#define MCAN_TXEFS_EFPI_Pos 16 +#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Put Index */ +#define MCAN_TXEFS_EFF (0x1u << 24) /**< \brief (MCAN_TXEFS) Event FIFO Full */ +#define MCAN_TXEFS_TEFL (0x1u << 25) /**< \brief (MCAN_TXEFS) Tx Event FIFO Element Lost */ +/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */ +#define MCAN_TXEFA_EFAI_Pos 0 +#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos) /**< \brief (MCAN_TXEFA) Event FIFO Acknowledge Index */ +#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos))) + +/*@}*/ + + +#endif /* _SAME70_MCAN_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pio.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pio.h new file mode 100644 index 00000000..ac8663a6 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pio.h @@ -0,0 +1,1722 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIO_COMPONENT_ +#define _SAME70_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[1]; + __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved12[4]; + __I uint32_t PIO_VERSION; /**< \brief (Pio Offset: 0x00FC) Version Register */ + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __I uint32_t Reserved13[5]; + __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */ + __I uint32_t Reserved14[13]; + __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */ +/* -------- PIO_VERSION : (PIO Offset: 0x00FC) Version Register -------- */ +#define PIO_VERSION_VERSION_Pos 0 +#define PIO_VERSION_VERSION_Msk (0xfffu << PIO_VERSION_VERSION_Pos) /**< \brief (PIO_VERSION) Hardware Module Version */ +#define PIO_VERSION_MFN_Pos 16 +#define PIO_VERSION_MFN_Msk (0x7u << PIO_VERSION_MFN_Pos) /**< \brief (PIO_VERSION) Metal Fix Number */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +/* -------- PIO_DRIVER : (PIO Offset: 0x0118) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0 (0x1u << 0) /**< \brief (PIO_DRIVER) Drive of PIO Line 0 */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1 (0x1u << 1) /**< \brief (PIO_DRIVER) Drive of PIO Line 1 */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2 (0x1u << 2) /**< \brief (PIO_DRIVER) Drive of PIO Line 2 */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3 (0x1u << 3) /**< \brief (PIO_DRIVER) Drive of PIO Line 3 */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4 (0x1u << 4) /**< \brief (PIO_DRIVER) Drive of PIO Line 4 */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5 (0x1u << 5) /**< \brief (PIO_DRIVER) Drive of PIO Line 5 */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6 (0x1u << 6) /**< \brief (PIO_DRIVER) Drive of PIO Line 6 */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7 (0x1u << 7) /**< \brief (PIO_DRIVER) Drive of PIO Line 7 */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8 (0x1u << 8) /**< \brief (PIO_DRIVER) Drive of PIO Line 8 */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9 (0x1u << 9) /**< \brief (PIO_DRIVER) Drive of PIO Line 9 */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10 (0x1u << 10) /**< \brief (PIO_DRIVER) Drive of PIO Line 10 */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11 (0x1u << 11) /**< \brief (PIO_DRIVER) Drive of PIO Line 11 */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12 (0x1u << 12) /**< \brief (PIO_DRIVER) Drive of PIO Line 12 */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13 (0x1u << 13) /**< \brief (PIO_DRIVER) Drive of PIO Line 13 */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14 (0x1u << 14) /**< \brief (PIO_DRIVER) Drive of PIO Line 14 */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15 (0x1u << 15) /**< \brief (PIO_DRIVER) Drive of PIO Line 15 */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16 (0x1u << 16) /**< \brief (PIO_DRIVER) Drive of PIO Line 16 */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17 (0x1u << 17) /**< \brief (PIO_DRIVER) Drive of PIO Line 17 */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18 (0x1u << 18) /**< \brief (PIO_DRIVER) Drive of PIO Line 18 */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19 (0x1u << 19) /**< \brief (PIO_DRIVER) Drive of PIO Line 19 */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20 (0x1u << 20) /**< \brief (PIO_DRIVER) Drive of PIO Line 20 */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21 (0x1u << 21) /**< \brief (PIO_DRIVER) Drive of PIO Line 21 */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22 (0x1u << 22) /**< \brief (PIO_DRIVER) Drive of PIO Line 22 */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23 (0x1u << 23) /**< \brief (PIO_DRIVER) Drive of PIO Line 23 */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24 (0x1u << 24) /**< \brief (PIO_DRIVER) Drive of PIO Line 24 */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25 (0x1u << 25) /**< \brief (PIO_DRIVER) Drive of PIO Line 25 */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26 (0x1u << 26) /**< \brief (PIO_DRIVER) Drive of PIO Line 26 */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27 (0x1u << 27) /**< \brief (PIO_DRIVER) Drive of PIO Line 27 */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28 (0x1u << 28) /**< \brief (PIO_DRIVER) Drive of PIO Line 28 */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29 (0x1u << 29) /**< \brief (PIO_DRIVER) Drive of PIO Line 29 */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30 (0x1u << 30) /**< \brief (PIO_DRIVER) Drive of PIO Line 30 */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31 (0x1u << 31) /**< \brief (PIO_DRIVER) Drive of PIO Line 31 */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31) /**< \brief (PIO_DRIVER) Highest drive */ +/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_Pos 4 +#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) +#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */ +/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos 0 +#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */ + +/*@}*/ + + +#endif /* _SAME70_PIO_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pmc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pmc.h new file mode 100644 index 00000000..ea4579b8 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pmc.h @@ -0,0 +1,774 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PMC_COMPONENT_ +#define _SAME70_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK[8]; /**< \brief (Pmc Offset: 0x40) Programmable Clock Register (chid = 0) */ + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved5[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved6[4]; + __I uint32_t PMC_VERSION; /**< \brief (Pmc Offset: 0x00FC) Version Register */ + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */ + __I uint32_t Reserved7[3]; + __IO uint32_t PMC_PMMR; /**< \brief (Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register */ + __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */ + __I uint32_t Reserved8[4]; + __IO uint32_t PMC_APLLACR; /**< \brief (Pmc Offset: 0x0158) Audio PLL Analog Configuration Register */ + __IO uint32_t PMC_WMST; /**< \brief (Pmc Offset: 0x015C) Wait Mode Startup Time Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */ +#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */ +#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */ +#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */ +#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */ +#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */ +#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_HCLKS (0x1u << 0) /**< \brief (PMC_SCSR) Processor Clock Status */ +#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */ +#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */ +#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */ +#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) Slow Crystal Oscillator Frequency Monitoring Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */ +#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ +#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos))) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_MDIV_Pos 8 +#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */ +#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos))) +#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[8] : (PMC Offset: 0x40) Programmable Clock Register (chid = 0) -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[8]) Programmable Clock Source Selection */ +#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos))) +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[8]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[8]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[8]) PLLA Clock is selected */ +#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[8]) Divided UPLL Clock is selected */ +#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[8]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[8]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */ +#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */ +#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */ +#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) Slow Crystal Oscillator Error Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */ +#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */ +#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */ +#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) Slow Crystal Oscillator Error Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main Crystal Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask */ +#define PMC_IMR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask */ +#define PMC_IMR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask */ +#define PMC_IMR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) Slow Crystal Oscillator Error Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */ +#define PMC_FSMR_FLPM_Pos 21 +#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */ +#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos))) +#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */ +/* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */ +#define PMC_VERSION_VERSION_Pos 0 +#define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) /**< \brief (PMC_VERSION) Version of the Hardware Module */ +#define PMC_VERSION_MFN_Pos 16 +#define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) /**< \brief (PMC_VERSION) Metal Fix Number */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x7fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_GCLKCSS_Pos 8 +#define PMC_PCR_GCLKCSS_Msk (0x7u << PMC_PCR_GCLKCSS_Pos) /**< \brief (PMC_PCR) Generic Clock Source Selection */ +#define PMC_PCR_GCLKCSS(value) ((PMC_PCR_GCLKCSS_Msk & ((value) << PMC_PCR_GCLKCSS_Pos))) +#define PMC_PCR_GCLKCSS_SLOW_CLK (0x0u << 8) /**< \brief (PMC_PCR) Slow clock is selected */ +#define PMC_PCR_GCLKCSS_MAIN_CLK (0x1u << 8) /**< \brief (PMC_PCR) Main clock is selected */ +#define PMC_PCR_GCLKCSS_PLLA_CLK (0x2u << 8) /**< \brief (PMC_PCR) PLLACK is selected */ +#define PMC_PCR_GCLKCSS_UPLL_CLK (0x3u << 8) /**< \brief (PMC_PCR) UPLL Clock is selected */ +#define PMC_PCR_GCLKCSS_MCK_CLK (0x4u << 8) /**< \brief (PMC_PCR) Master Clock is selected */ +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_DIV_Pos 16 +#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */ +#define PMC_PCR_DIV(value) ((PMC_PCR_DIV_Msk & ((value) << PMC_PCR_DIV_Pos))) +#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */ +#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */ +#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */ +#define PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/8 */ +#define PMC_PCR_GCLKDIV_Pos 20 +#define PMC_PCR_GCLKDIV_Msk (0xffu << PMC_PCR_GCLKDIV_Pos) /**< \brief (PMC_PCR) Generic Clock Division Ratio */ +#define PMC_PCR_GCLKDIV(value) ((PMC_PCR_GCLKDIV_Msk & ((value) << PMC_PCR_GCLKDIV_Pos))) +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ +#define PMC_PCR_GCLKEN (0x1u << 29) /**< \brief (PMC_PCR) Generic Clock Enable */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */ +#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */ +#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */ +#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */ +#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */ +#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */ +#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */ +#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */ +#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */ +#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */ +#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */ +#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */ +#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */ +#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */ +#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */ +#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */ +#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */ +#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */ +#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */ +#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */ +#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */ +#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */ +#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */ +#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */ +#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */ +/* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */ +#define PMC_PMMR_PLLA_MMAX_Pos 0 +#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /**< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value */ +#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos))) +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */ +#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */ +#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */ +#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */ +#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */ +#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */ +#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */ +#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */ +#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */ +#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */ +#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */ +#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */ +#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */ +#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */ +#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */ +#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */ +#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */ +#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */ +#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */ +#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */ +#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */ +#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */ +#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */ +#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */ +#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */ +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */ +/* -------- PMC_APLLACR : (PMC Offset: 0x0158) Audio PLL Analog Configuration Register -------- */ +#define PMC_APLLACR_DCOFLTSEL_Pos 0 +#define PMC_APLLACR_DCOFLTSEL_Msk (0xfu << PMC_APLLACR_DCOFLTSEL_Pos) /**< \brief (PMC_APLLACR) DCO Filter Selection */ +#define PMC_APLLACR_DCOFLTSEL(value) ((PMC_APLLACR_DCOFLTSEL_Msk & ((value) << PMC_APLLACR_DCOFLTSEL_Pos))) +#define PMC_APLLACR_FLTSEL_Pos 4 +#define PMC_APLLACR_FLTSEL_Msk (0xfu << PMC_APLLACR_FLTSEL_Pos) /**< \brief (PMC_APLLACR) PLL Filter Selection */ +#define PMC_APLLACR_FLTSEL(value) ((PMC_APLLACR_FLTSEL_Msk & ((value) << PMC_APLLACR_FLTSEL_Pos))) +#define PMC_APLLACR_BIAS_Pos 8 +#define PMC_APLLACR_BIAS_Msk (0x3u << PMC_APLLACR_BIAS_Pos) /**< \brief (PMC_APLLACR) Bias Voltage Selection */ +#define PMC_APLLACR_BIAS(value) ((PMC_APLLACR_BIAS_Msk & ((value) << PMC_APLLACR_BIAS_Pos))) +/* -------- PMC_WMST : (PMC Offset: 0x015C) Wait Mode Startup Time Register -------- */ +#define PMC_WMST_WMST_Pos 0 +#define PMC_WMST_WMST_Msk (0xffu << PMC_WMST_WMST_Pos) /**< \brief (PMC_WMST) Wait Mode Startup Time */ +#define PMC_WMST_WMST(value) ((PMC_WMST_WMST_Msk & ((value) << PMC_WMST_WMST_Pos))) +#define PMC_WMST_KEY_Pos 24 +#define PMC_WMST_KEY_Msk (0xffu << PMC_WMST_KEY_Pos) /**< \brief (PMC_WMST) Write Access Password */ +#define PMC_WMST_KEY(value) ((PMC_WMST_KEY_Msk & ((value) << PMC_WMST_KEY_Pos))) +#define PMC_WMST_KEY_PASSWD (0x5Au << 24) /**< \brief (PMC_WMST) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_PMC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pwm.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pwm.h new file mode 100644 index 00000000..f9dbdcd2 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pwm.h @@ -0,0 +1,656 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PWM_COMPONENT_ +#define _SAME70_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t PWM_ELMR[8]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ + __I uint32_t Reserved5[8]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */ + __I uint32_t Reserved6[4]; + __I uint32_t PWM_VERSION; /**< \brief (Pwm Offset: 0xFC) Version Register */ + __I uint32_t Reserved7[12]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + __I uint32_t Reserved8[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ + __I uint32_t Reserved9[96]; + __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint32_t Reserved10[7]; + __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint32_t Reserved11[2]; + __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint32_t Reserved12[3]; + __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint32_t Reserved13[2]; + __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint32_t Reserved14[3]; + __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos 0 +#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */ +#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[8] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[8]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[8]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[8]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[8]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[8]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[8]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[8]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[8]) Comparison 7 Selection */ +/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos 0 +#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */ +#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) +#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */ +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos 0 +#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */ +#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ +#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ +#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ +#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ +#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ +#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ +#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ +#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_VERSION : (PWM Offset: 0xFC) Version Register -------- */ +#define PWM_VERSION_VERSION_Pos 0 +#define PWM_VERSION_VERSION_Msk (0xfffu << PWM_VERSION_VERSION_Pos) /**< \brief (PWM_VERSION) Version of the Hardware Module */ +#define PWM_VERSION_MFN_Pos 16 +#define PWM_VERSION_MFN_Msk (0x7u << PWM_VERSION_MFN_Pos) /**< \brief (PWM_VERSION) Metal Fix Number */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */ +#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */ +#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */ +#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */ +#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos 0 +#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */ +#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) +#define PWM_ETRG1_TRGMODE_Pos 24 +#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */ +#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) +#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */ +#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */ +#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */ +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos 0 +#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) +#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */ +#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */ +#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */ +#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */ +#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos 0 +#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */ +#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) +#define PWM_ETRG2_TRGMODE_Pos 24 +#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */ +#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) +#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */ +#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */ +#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */ +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos 0 +#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) +#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */ +#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */ +#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */ +#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */ +#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */ + +/*@}*/ + + +#endif /* _SAME70_PWM_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/qspi.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/qspi.h new file mode 100644 index 00000000..f10534c5 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/qspi.h @@ -0,0 +1,235 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_QSPI_COMPONENT_ +#define _SAME70_QSPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_QSPI Quad Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Qspi hardware registers */ +typedef struct { + __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */ + __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */ + __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */ + __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */ + __I uint32_t Reserved3[39]; + __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t QSPI_VERSION; /**< \brief (Qspi Offset: 0x00FC) Version Register */ +} Qspi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */ +#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */ +#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */ +#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */ +#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */ +/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */ +#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */ +#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */ +#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */ +#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_CSMODE_Pos 4 +#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */ +#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))) +#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_NBBITS_Pos 8 +#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */ +#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))) +#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_9_BIT (0x1u << 8) /**< \brief (QSPI_MR) 9 bits for transfer */ +#define QSPI_MR_NBBITS_10_BIT (0x2u << 8) /**< \brief (QSPI_MR) 10 bits for transfer */ +#define QSPI_MR_NBBITS_11_BIT (0x3u << 8) /**< \brief (QSPI_MR) 11 bits for transfer */ +#define QSPI_MR_NBBITS_12_BIT (0x4u << 8) /**< \brief (QSPI_MR) 12 bits for transfer */ +#define QSPI_MR_NBBITS_13_BIT (0x5u << 8) /**< \brief (QSPI_MR) 13 bits for transfer */ +#define QSPI_MR_NBBITS_14_BIT (0x6u << 8) /**< \brief (QSPI_MR) 14 bits for transfer */ +#define QSPI_MR_NBBITS_15_BIT (0x7u << 8) /**< \brief (QSPI_MR) 15 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_DLYBCT_Pos 16 +#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */ +#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))) +#define QSPI_MR_DLYCS_Pos 24 +#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */ +#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))) +/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos 0 +#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */ +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos 0 +#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */ +#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))) +/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */ +#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status (cleared on read) */ +#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */ +#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */ +#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */ +#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */ +/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */ +#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */ +#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */ +#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */ +#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */ +#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */ +#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */ +/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */ +#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */ +#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */ +#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */ +#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */ +#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */ +#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */ +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */ +#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */ +#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */ +#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */ +#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */ +#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */ +#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */ +/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */ +#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */ +#define QSPI_SCR_SCBR_Pos 8 +#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */ +#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))) +#define QSPI_SCR_DLYBS_Pos 16 +#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */ +#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))) +/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos 0 +#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */ +#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))) +/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos 0 +#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */ +#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))) +#define QSPI_ICR_OPT_Pos 16 +#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */ +#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))) +/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos 0 +#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */ +#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */ +#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */ +#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */ +#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */ +#define QSPI_IFR_OPTL_Pos 8 +#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */ +#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))) +#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */ +#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_TFRTYP_Pos 12 +#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */ +#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))) +#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */ +#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_NBDUM_Pos 16 +#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */ +#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))) +/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */ +#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */ +/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos 0 +#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */ +#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))) +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */ +#define QSPI_WPMR_WPKEY_Pos 8 +#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */ +#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))) +#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */ +#define QSPI_WPSR_WPVSRC_Pos 8 +#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */ +/* -------- QSPI_VERSION : (QSPI Offset: 0x00FC) Version Register -------- */ +#define QSPI_VERSION_VERSION_Pos 0 +#define QSPI_VERSION_VERSION_Msk (0xfffu << QSPI_VERSION_VERSION_Pos) /**< \brief (QSPI_VERSION) Hardware Module Version */ +#define QSPI_VERSION_MFN_Pos 16 +#define QSPI_VERSION_MFN_Msk (0x7u << QSPI_VERSION_MFN_Pos) /**< \brief (QSPI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_QSPI_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rstc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rstc.h new file mode 100644 index 00000000..bd639b9c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rstc.h @@ -0,0 +1,84 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RSTC_COMPONENT_ +#define _SAME70_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) +#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_RSTC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rswdt.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rswdt.h new file mode 100644 index 00000000..129c659e --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rswdt.h @@ -0,0 +1,77 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RSWDT_COMPONENT_ +#define _SAME70_RSWDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_RSWDT Reinforced Safety Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rswdt hardware registers */ +typedef struct { + __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */ + __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */ + __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */ +} Rswdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */ +#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */ +#define RSWDT_CR_KEY_Pos 24 +#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */ +#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) +#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos 0 +#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */ +#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) +#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */ +#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */ +#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */ +#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */ +#define RSWDT_MR_ALLONES_Pos 16 +#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */ +#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) +#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */ +#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */ +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */ +#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */ + +/*@}*/ + + +#endif /* _SAME70_RSWDT_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rtc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rtc.h new file mode 100644 index 00000000..bdf89283 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rtc.h @@ -0,0 +1,246 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RTC_COMPONENT_ +#define _SAME70_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAME70_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ + __I uint32_t Reserved1[45]; + __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t RTC_VERSION; /**< \brief (Rtc Offset: 0xFC) Version Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ +#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ +#define RTC_MR_CORRECTION_Pos 8 +#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ +#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) +#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ +#define RTC_MR_OUT0_Pos 16 +#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */ +#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos))) +#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_Pos 20 +#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ +#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos))) +#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_THIGH_Pos 24 +#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ +#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos))) +#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ +#define RTC_MR_TPERIOD_Pos 28 +#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ +#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos))) +#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ +#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ +/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */ +#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */ +#define RTC_WPMR_WPKEY_Pos 8 +#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */ +#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))) +#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- RTC_VERSION : (RTC Offset: 0xFC) Version Register -------- */ +#define RTC_VERSION_VERSION_Pos 0 +#define RTC_VERSION_VERSION_Msk (0xfffu << RTC_VERSION_VERSION_Pos) /**< \brief (RTC_VERSION) Version of the Hardware Module */ +#define RTC_VERSION_MFN_Pos 16 +#define RTC_VERSION_MFN_Msk (0x7u << RTC_VERSION_MFN_Pos) /**< \brief (RTC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_RTC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rtt.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rtt.h new file mode 100644 index 00000000..8ceea226 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/rtt.h @@ -0,0 +1,76 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RTT_COMPONENT_ +#define _SAME70_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ +#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */ + +/*@}*/ + + +#endif /* _SAME70_RTT_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/sdramc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/sdramc.h new file mode 100644 index 00000000..e9d0e349 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/sdramc.h @@ -0,0 +1,185 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SDRAMC_COMPONENT_ +#define _SAME70_SDRAMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SDRAMC SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sdramc hardware registers */ +typedef struct { + __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */ + __I uint32_t Reserved2[49]; + __I uint32_t SDRAMC_VERSION; /**< \brief (Sdramc Offset: 0xFC) SDRAMC Version Register */ +} Sdramc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos 0 +#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */ +#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos))) +#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos 0 +#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */ +#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))) +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos 0 +#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */ +#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos))) +#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NR_Pos 2 +#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */ +#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos))) +#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */ +#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_CAS_Pos 5 +#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */ +#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos))) +#define SDRAMC_CR_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */ +#define SDRAMC_CR_TWR_Pos 8 +#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */ +#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))) +#define SDRAMC_CR_TRC_TRFC_Pos 12 +#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))) +#define SDRAMC_CR_TRP_Pos 16 +#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */ +#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))) +#define SDRAMC_CR_TRCD_Pos 20 +#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */ +#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))) +#define SDRAMC_CR_TRAS_Pos 24 +#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */ +#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))) +#define SDRAMC_CR_TXSR_Pos 28 +#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))) +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos 0 +#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */ +#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos))) +#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_PASR_Pos 4 +#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))) +#define SDRAMC_LPR_TCSR_Pos 8 +#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))) +#define SDRAMC_LPR_DS_Pos 10 +#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */ +#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))) +#define SDRAMC_LPR_TIMEOUT_Pos 12 +#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */ +#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos))) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */ +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */ +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */ +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */ +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos 0 +#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */ +#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos))) +#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */ +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos 0 +#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */ +#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos))) +#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */ +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */ +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 +#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */ +#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos))) +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 +#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */ +#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos))) +/* -------- SDRAMC_VERSION : (SDRAMC Offset: 0xFC) SDRAMC Version Register -------- */ +#define SDRAMC_VERSION_VERSION_Pos 0 +#define SDRAMC_VERSION_VERSION_Msk (0xfffu << SDRAMC_VERSION_VERSION_Pos) /**< \brief (SDRAMC_VERSION) Version of the Hardware Module */ +#define SDRAMC_VERSION_MFN_Pos 16 +#define SDRAMC_VERSION_MFN_Msk (0x7u << SDRAMC_VERSION_MFN_Pos) /**< \brief (SDRAMC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_SDRAMC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/smc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/smc.h new file mode 100644 index 00000000..d71158d0 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/smc.h @@ -0,0 +1,160 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SMC_COMPONENT_ +#define _SAME70_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC Off-Chip Memory Scrambling Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC Off-Chip Memory Scrambling KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t SMC_VERSION; /**< \brief (Smc Offset: 0xFC) SMC Version Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled-The NWAIT input signal is ignored on the corresponding chip select. */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))) +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC Off-Chip Memory Scrambling Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_CS0SE (0x1u << 8) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS1SE (0x1u << 9) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS2SE (0x1u << 10) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS3SE (0x1u << 11) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off-Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC Off-Chip Memory Scrambling KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off-Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ +/* -------- SMC_VERSION : (SMC Offset: 0xFC) SMC Version Register -------- */ +#define SMC_VERSION_VERSION_Pos 0 +#define SMC_VERSION_VERSION_Msk (0xfffu << SMC_VERSION_VERSION_Pos) /**< \brief (SMC_VERSION) Hardware Module Version */ +#define SMC_VERSION_MFN_Pos 16 +#define SMC_VERSION_MFN_Msk (0x7u << SMC_VERSION_MFN_Pos) /**< \brief (SMC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_SMC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/spi.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/spi.h new file mode 100644 index 00000000..79806a2d --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/spi.h @@ -0,0 +1,178 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SPI_COMPONENT_ +#define _SAME70_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register (CS_number = 0) */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t SPI_VERSION; /**< \brief (Spi Offset: 0xFC) Version Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_REQCLR (0x1u << 12) /**< \brief (SPI_CR) Request to Clear the Comparison Trigger */ +#define SPI_CR_TXFCLR (0x1u << 16) /**< \brief (SPI_CR) Transmit FIFO Clear */ +#define SPI_CR_RXFCLR (0x1u << 17) /**< \brief (SPI_CR) Receive FIFO Clear */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +#define SPI_CR_FIFOEN (0x1u << 30) /**< \brief (SPI_CR) FIFO Enable */ +#define SPI_CR_FIFODIS (0x1u << 31) /**< \brief (SPI_CR) FIFO Disable */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register (CS_number = 0) -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ +/* -------- SPI_VERSION : (SPI Offset: 0xFC) Version Register -------- */ +#define SPI_VERSION_VERSION_Pos 0 +#define SPI_VERSION_VERSION_Msk (0xfffu << SPI_VERSION_VERSION_Pos) /**< \brief (SPI_VERSION) Version of the Hardware Module */ +#define SPI_VERSION_MFN_Pos 16 +#define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos) /**< \brief (SPI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_SPI_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/ssc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/ssc.h new file mode 100644 index 00000000..a0a89d6c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/ssc.h @@ -0,0 +1,292 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SSC_COMPONENT_ +#define _SAME70_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t SSC_VERSION; /**< \brief (Ssc Offset: 0xFC) Version Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))) +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))) +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))) +#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))) +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))) +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))) +#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ +/* -------- SSC_VERSION : (SSC Offset: 0xFC) Version Register -------- */ +#define SSC_VERSION_VERSION_Pos 0 +#define SSC_VERSION_VERSION_Msk (0xffffu << SSC_VERSION_VERSION_Pos) /**< \brief (SSC_VERSION) Version of the Hardware Module */ +#define SSC_VERSION_MFN_Pos 16 +#define SSC_VERSION_MFN_Msk (0x7u << SSC_VERSION_MFN_Pos) /**< \brief (SSC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_SSC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/supc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/supc.h new file mode 100644 index 00000000..a1d84869 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/supc.h @@ -0,0 +1,306 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70_SUPC_COMPONENT_ +#define _SAME70_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ + __I uint32_t Reserved1[57]; + __I uint32_t SYSC_VERSION; /**< \brief (Supc Offset: 0xFC) Version Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_LPDBC_Pos 16 +#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */ +#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos))) +#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */ +#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */ +#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */ +#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */ +#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */ +#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */ +#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */ +#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */ +#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */ +#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */ +#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */ +#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */ +#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */ +#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */ +#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */ +#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */ +#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +/* -------- SYSC_VERSION : (SUPC Offset: 0xFC) Version Register -------- */ +#define SYSC_VERSION_VERSION_Pos 0 +#define SYSC_VERSION_VERSION_Msk (0xfffu << SYSC_VERSION_VERSION_Pos) /**< \brief (SYSC_VERSION) Version of the Hardware Module */ +#define SYSC_VERSION_MFN_Pos 16 +#define SYSC_VERSION_MFN_Msk (0x7u << SYSC_VERSION_MFN_Pos) /**< \brief (SYSC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_SUPC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/tc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/tc.h new file mode 100644 index 00000000..8dfa807c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/tc.h @@ -0,0 +1,365 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TC_COMPONENT_ +#define _SAME70_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAME70_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ + __I uint32_t Reserved1[3]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_SBSMPLR_Pos 20 +#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) +#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ +/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ +#define TC_RAB_RAB_Pos 0 +#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ +#define TC_EMR_TRIGSRCA_Pos 0 +#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ +#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCB_Pos 4 +#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ +#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven internally by PWMx */ +#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +#define TC_BMR_MAXCMP_Pos 26 /**< (TC_BMR) Maximum Consecutive Missing Pulses Position */ +#define TC_BMR_MAXCMP_Msk (0xfu << TC_BMR_MAXCMP_Pos) /**< (TC_BMR) Maximum Consecutive Missing Pulses Mask */ +#define TC_BMR_MAXCMP(value) (TC_BMR_MAXCMP_Msk & ((value) << TC_BMR_MAXCMP_Pos)) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ +#define TC_QIER_MPE (0x1u << 3) /**< \brief (TC_QIER) Consecutive Missing Pulse Error */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ +#define TC_QIDR_MPE (0x1u << 3) /**< \brief (TC_QIDR) Consecutive Missing Pulse Error */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ +#define TC_QIMR_MPE (0x1u << 3) /**< \brief (TC_QIMR) Consecutive Missing Pulse Error */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ +#define TC_QISR_MPE (0x1u << 3) /**< \brief (TC_QISR) Consecutive Missing Pulse Error */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) +#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ +#define TC_VER_VERSION_Pos 0 +#define TC_VER_VERSION_Msk (0xfffu << TC_VER_VERSION_Pos) /**< \brief (TC_VER) Version of the Hardware Module */ +#define TC_VER_MFN_Pos 16 +#define TC_VER_MFN_Msk (0x7u << TC_VER_MFN_Pos) /**< \brief (TC_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_TC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/trng.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/trng.h new file mode 100644 index 00000000..4ae37db9 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/trng.h @@ -0,0 +1,85 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TRNG_COMPONENT_ +#define _SAME70_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAME70_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + __I uint32_t Reserved1[3]; + __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + __I uint32_t Reserved2[12]; + __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ + __I uint32_t Reserved3[42]; + __I uint32_t TRNG_VERSION; /**< \brief (Trng Offset: 0xFC) Version Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key. */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */ +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ +/* -------- TRNG_VERSION : (TRNG Offset: 0xFC) Version Register -------- */ +#define TRNG_VERSION_VERSION_Pos 0 +#define TRNG_VERSION_VERSION_Msk (0xfffu << TRNG_VERSION_VERSION_Pos) /**< \brief (TRNG_VERSION) Version of the Hardware Module */ +#define TRNG_VERSION_MFN_Pos 16 +#define TRNG_VERSION_MFN_Msk (0x7u << TRNG_VERSION_MFN_Pos) /**< \brief (TRNG_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_TRNG_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/twihs.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/twihs.h new file mode 100644 index 00000000..548854dc --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/twihs.h @@ -0,0 +1,275 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TWIHS_COMPONENT_ +#define _SAME70_TWIHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */ +/* ============================================================================= */ +/** \addtogroup SAME70_TWIHS Two-wire Interface High Speed */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twihs hardware registers */ +typedef struct { + __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */ + __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */ + __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */ + __I uint32_t Reserved4[32]; + __I uint32_t TWIHS_DR; /**< \brief (Twihs Offset: 0xD0) Debug Register */ + __I uint32_t Reserved5[4]; + __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved6[4]; + __I uint32_t TWIHS_VER; /**< \brief (Twihs Offset: 0xFC) Version Register */ +} Twihs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */ +#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */ +#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */ +#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */ +#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */ +#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */ +#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */ +#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */ +#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */ +#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */ +#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */ +#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */ +#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */ +#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */ +#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */ +#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */ +#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */ +#define TWIHS_CR_ACMEN (0x1u << 16) /**< \brief (TWIHS_CR) Alternative Command Mode Enable */ +#define TWIHS_CR_ACMDIS (0x1u << 17) /**< \brief (TWIHS_CR) Alternative Command Mode Disable */ +#define TWIHS_CR_THRCLR (0x1u << 24) /**< \brief (TWIHS_CR) Transmit Holding Register Clear */ +#define TWIHS_CR_LOCKCLR (0x1u << 26) /**< \brief (TWIHS_CR) Lock Clear */ +#define TWIHS_CR_FIFOEN (0x1u << 28) /**< \brief (TWIHS_CR) FIFO Enable */ +#define TWIHS_CR_FIFODIS (0x1u << 29) /**< \brief (TWIHS_CR) FIFO Disable */ +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos 8 +#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */ +#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) +#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */ +#define TWIHS_MMR_DADR_Pos 16 +#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */ +#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */ +#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */ +#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */ +#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */ +#define TWIHS_SMR_MASK_Pos 8 +#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) +#define TWIHS_SMR_SADR_Pos 16 +#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */ +#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) +#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */ +#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */ +#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */ +#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */ +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos 0 +#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */ +#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos 0 +#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */ +#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) +#define TWIHS_CWGR_CHDIV_Pos 8 +#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */ +#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) +#define TWIHS_CWGR_CKDIV_Pos 16 +#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */ +#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) +#define TWIHS_CWGR_HOLD_Pos 24 +#define TWIHS_CWGR_HOLD_Msk (0x3fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */ +#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */ +#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ +#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */ +#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */ +#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */ +#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */ +#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */ +#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */ +#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */ +#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */ +#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */ +#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */ +#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */ +#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */ +#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */ +#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */ +#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL line value */ +#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA line value */ +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */ +#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */ +#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */ +#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */ +#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */ +#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */ +#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */ +#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */ +#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */ +#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */ +#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */ +#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */ +#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */ +#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */ +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */ +#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */ +#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */ +#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */ +#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */ +#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */ +#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */ +#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */ +#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */ +#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */ +#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */ +#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */ +#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */ +#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */ +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */ +#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */ +#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */ +#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */ +#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */ +#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */ +#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */ +#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */ +#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */ +#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */ +#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */ +#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */ +#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */ +#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */ +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos 0 +#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */ +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos 0 +#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */ +#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos 0 +#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */ +#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) +#define TWIHS_SMBTR_TLOWS_Pos 8 +#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) +#define TWIHS_SMBTR_TLOWM_Pos 16 +#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) +#define TWIHS_SMBTR_THMAX_Pos 24 +#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */ +#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */ +#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */ +#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */ +#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */ +#define TWIHS_FILTR_THRES_Pos 8 +#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */ +#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos 0 +#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */ +#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) +#define TWIHS_SWMR_SADR2_Pos 8 +#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */ +#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) +#define TWIHS_SWMR_SADR3_Pos 16 +#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */ +#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) +#define TWIHS_SWMR_DATAM_Pos 24 +#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */ +#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) +/* -------- TWIHS_DR : (TWIHS Offset: 0xD0) Debug Register -------- */ +#define TWIHS_DR_SWEN (0x1u << 0) /**< \brief (TWIHS_DR) SleepWalking Enable */ +#define TWIHS_DR_CLKRQ (0x1u << 1) /**< \brief (TWIHS_DR) Clock Request */ +#define TWIHS_DR_SWMATCH (0x1u << 2) /**< \brief (TWIHS_DR) SleepWalking Match */ +#define TWIHS_DR_TRP (0x1u << 3) /**< \brief (TWIHS_DR) Transfer Pending */ +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */ +#define TWIHS_WPMR_WPKEY_Pos 8 +#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */ +#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) +#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */ +#define TWIHS_WPSR_WPVSRC_Pos 8 +#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */ +/* -------- TWIHS_VER : (TWIHS Offset: 0xFC) Version Register -------- */ +#define TWIHS_VER_VERSION_Pos 0 +#define TWIHS_VER_VERSION_Msk (0xfffu << TWIHS_VER_VERSION_Pos) /**< \brief (TWIHS_VER) Version of the Hardware Module */ +#define TWIHS_VER_MFN_Pos 16 +#define TWIHS_VER_MFN_Msk (0x7u << TWIHS_VER_MFN_Pos) /**< \brief (TWIHS_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_TWIHS_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/uart.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/uart.h new file mode 100644 index 00000000..b9d81010 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/uart.h @@ -0,0 +1,167 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UART_COMPONENT_ +#define _SAME70_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAME70_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ + __I uint32_t Reserved1[47]; + __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t UART_VERSION; /**< \brief (Uart Offset: 0x00FC) Version Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ +#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ +#define UART_CR_DBGE (0x1u << 15) /**< \brief (UART_CR) Debug Enable */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ +#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ +#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ +#define UART_SR_SWES (0x1u << 21) /**< \brief (UART_SR) SleepWalking Enable Status */ +#define UART_SR_CLKREQ (0x1u << 22) /**< \brief (UART_SR) Clock Request */ +#define UART_SR_WKUPREQ (0x1u << 23) /**< \brief (UART_SR) Wake-Up Request */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos 0 +#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ +#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) +#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ +#define UART_CMPR_VAL2_Pos 16 +#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ +#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) +/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ +#define UART_WPMR_WPKEY_Pos 8 +#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ +#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) +#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +/* -------- UART_VERSION : (UART Offset: 0x00FC) Version Register -------- */ +#define UART_VERSION_VERSION_Pos 0 +#define UART_VERSION_VERSION_Msk (0xfffu << UART_VERSION_VERSION_Pos) /**< \brief (UART_VERSION) Hardware Module Version */ +#define UART_VERSION_MFN_Pos 16 +#define UART_VERSION_MFN_Msk (0x7u << UART_VERSION_MFN_Pos) /**< \brief (UART_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_UART_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/usart.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/usart.h new file mode 100644 index 00000000..6785c9b4 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/usart.h @@ -0,0 +1,492 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USART_COMPONENT_ +#define _SAME70_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAME70_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */ + __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */ + __I uint32_t Reserved3[22]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t US_VERSION; /**< \brief (Usart Offset: 0x00FC) Version Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */ +#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ +#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */ +#define US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN Master mode */ +#define US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave mode */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave mode */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))) +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */ +#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ +#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))) +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))) +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))) +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +#define US_IER_NSSE (0x1u << 19) /**< \brief (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable */ +#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ +#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ +#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ +#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ +#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ +#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ +#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ +#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ +#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */ +#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */ +#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */ +#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */ +#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */ +#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */ +#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */ +#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */ +#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +#define US_IDR_NSSE (0x1u << 19) /**< \brief (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable */ +#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ +#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ +#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ +#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ +#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ +#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ +#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ +#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ +#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */ +#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */ +#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */ +#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */ +#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */ +#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */ +#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */ +#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */ +#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +#define US_IMR_NSSE (0x1u << 19) /**< \brief (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask */ +#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ +#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ +#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ +#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ +#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ +#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ +#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ +#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ +#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */ +#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */ +#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */ +#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */ +#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */ +#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */ +#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */ +#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */ +#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) */ +#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag (cleared on read) */ +#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag (cleared on read) */ +#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */ +#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_NSSE (0x1u << 19) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_NSS (0x1u << 23) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ +#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */ +/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +#define US_TTGR_PCYCLE_Pos 0 +#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */ +#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +#define US_FIDI_BETA2_Pos 0 +#define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos) /**< \brief (US_FIDI) LON BETA2 Length */ +#define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ +#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */ +/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos 0 +#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ +#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos))) +#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ +#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ +#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ +#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ +#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ +#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ +#define US_LINMR_DLC_Pos 8 +#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ +#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) +#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */ +#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */ +/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos 0 +#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ +#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) +/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos 0 +#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ +#define US_LINBRR_LINFP_Pos 16 +#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ +/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */ +#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */ +#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */ +#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */ +#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */ +#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */ +#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */ +#define US_LONMR_EOFS_Pos 16 +#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */ +#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos))) +/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos 0 +#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */ +#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos))) +/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos 0 +#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */ +#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos))) +/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos 0 +#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */ +#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos))) +#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */ +#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */ +/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos 0 +#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */ +/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos 0 +#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */ +#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos))) +/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos 0 +#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */ +#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos))) +/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos 0 +#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */ +#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos))) +#define US_LONPRIO_NPS_Pos 8 +#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */ +#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos))) +/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos 0 +#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */ +#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos))) +/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos 0 +#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */ +#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos))) +/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos 0 +#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */ +#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos))) +/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ +/* -------- US_VERSION : (USART Offset: 0x00FC) Version Register -------- */ +#define US_VERSION_VERSION_Pos 0 +#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) Hardware Module Version */ +#define US_VERSION_MFN_Pos 16 +#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_USART_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h new file mode 100644 index 00000000..b75cacd2 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h @@ -0,0 +1,952 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USBHS_COMPONENT_ +#define _SAME70_USBHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_USBHS USB High-Speed Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UsbhsDevdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UsbhsDevdma; +/** \brief UsbhsHstdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UsbhsHstdma; +/** \brief Usbhs hardware registers */ +#define USBHSDEVDMA_NUMBER 7 +#define USBHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t Reserved2[2]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __I uint32_t Reserved3[2]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __I uint32_t Reserved4[2]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t Reserved5[2]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __I uint32_t Reserved6[2]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __I uint32_t Reserved7[2]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved8[50]; + UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved9[32]; + __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved10[52]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t Reserved11[2]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __I uint32_t Reserved12[2]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __I uint32_t Reserved13[2]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t Reserved14[2]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __I uint32_t Reserved15[2]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __I uint32_t Reserved16[2]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __I uint32_t Reserved17[2]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __I uint32_t Reserved18[2]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved19[26]; + UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved20[32]; + __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */ + __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */ + __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */ + __IO uint32_t USBHS_TSTA1; /**< \brief (Usbhs Offset: 0x0810) General Test A1 Register */ + __IO uint32_t USBHS_TSTA2; /**< \brief (Usbhs Offset: 0x0814) General Test A2 Register */ + __I uint32_t USBHS_VERSION; /**< \brief (Usbhs Offset: 0x0818) General Version Register */ + __I uint32_t Reserved21[4]; + __I uint32_t USBHS_FSM; /**< \brief (Usbhs Offset: 0x082C) General Finite State Machine Register */ +} Usbhs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos 0 +#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */ +#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos))) +#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */ +#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */ +#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */ +#define USBHS_DEVCTRL_SPDCONF_Pos 10 +#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */ +#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos))) +#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (USBHS_DEVCTRL) Forced high speed. */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ +#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */ +#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */ +#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */ +#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */ +#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */ +/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */ +#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */ +#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */ +#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */ +#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */ +#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */ +#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */ +#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */ +#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */ +#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */ +#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */ +#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */ +#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */ +#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */ +#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */ +#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */ +#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */ +#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */ +#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */ +#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */ +#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */ +#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */ +#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */ +#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */ +#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */ +#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */ +#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */ +#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */ +#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */ +#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */ +#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */ +#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */ +#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */ +#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */ +#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */ +#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */ +#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */ +#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */ +#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */ +#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */ +#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */ +#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */ +#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */ +#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */ +#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */ +#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */ +#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */ +#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */ +#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */ +#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */ +#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */ +#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */ +#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */ +#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */ +#define USBHS_DEVEPT_EPEN9 (0x1u << 9) /**< \brief (USBHS_DEVEPT) Endpoint 9 Enable */ +#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */ +#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */ +#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */ +#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */ +#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */ +#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */ +#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */ +#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */ +#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */ +#define USBHS_DEVEPT_EPRST9 (0x1u << 25) /**< \brief (USBHS_DEVEPT) Endpoint 9 Reset */ +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos 0 +#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */ +#define USBHS_DEVFNUM_FNUM_Pos 3 +#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */ +#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */ +/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */ +#define USBHS_DEVEPTCFG_EPBK_Pos 2 +#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */ +#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos))) +#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos 4 +#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */ +#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos))) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */ +#define USBHS_DEVEPTCFG_EPTYPE_Pos 11 +#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */ +#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos))) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos 13 +#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */ +#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos))) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTISR_DTSEQ_Pos 8 +#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos 12 +#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */ +#define USBHS_DEVEPTISR_CURRBK_Pos 14 +#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */ +#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */ +#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */ +#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */ +#define USBHS_DEVEPTISR_BYCT_Pos 20 +#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */ +#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */ +#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */ +#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */ +#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */ +#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */ +#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */ +#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */ +#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */ +#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */ +#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */ +#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */ +#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */ +#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */ +#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */ +#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */ +#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */ +#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */ +#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */ +#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */ +#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */ +#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */ +#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */ +#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */ +#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */ +#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */ +#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */ +#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */ +#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */ +#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */ +#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */ +/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */ +#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */ +#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */ +#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */ +#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */ +#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */ +#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */ +#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */ +#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */ +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */ +#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */ +#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */ +#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */ +#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */ +#define USBHS_HSTCTRL_SPDCONF_Pos 12 +#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */ +#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos))) +#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (USBHS_HSTCTRL) Forced high speed. */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ +/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */ +#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */ +#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */ +#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */ +#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */ +#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */ +#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */ +#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */ +#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */ +#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */ +#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */ +#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */ +#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */ +#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */ +#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */ +#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */ +#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */ +#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */ +#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */ +#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */ +#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */ +#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */ +#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */ +#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */ +#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */ +#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */ +#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */ +#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */ +#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */ +#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */ +#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */ +#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */ +#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */ +#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */ +#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */ +#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */ +#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */ +#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */ +#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */ +#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */ +#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */ +#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */ +#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */ +#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */ +#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */ +#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */ +#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */ +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos 0 +#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */ +#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos))) +#define USBHS_HSTFNUM_FNUM_Pos 3 +#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */ +#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos))) +#define USBHS_HSTFNUM_FLENHIGH_Pos 16 +#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */ +#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos 0 +#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos))) +#define USBHS_HSTADDR1_HSTADDRP1_Pos 8 +#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos))) +#define USBHS_HSTADDR1_HSTADDRP2_Pos 16 +#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos))) +#define USBHS_HSTADDR1_HSTADDRP3_Pos 24 +#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos 0 +#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos))) +#define USBHS_HSTADDR2_HSTADDRP5_Pos 8 +#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos))) +#define USBHS_HSTADDR2_HSTADDRP6_Pos 16 +#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos))) +#define USBHS_HSTADDR2_HSTADDRP7_Pos 24 +#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos 0 +#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos))) +#define USBHS_HSTADDR3_HSTADDRP9_Pos 8 +#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */ +#define USBHS_HSTPIPCFG_PBK_Pos 2 +#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */ +#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos))) +#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PSIZE_Pos 4 +#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */ +#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos))) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos 8 +#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */ +#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos))) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */ +#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */ +#define USBHS_HSTPIPCFG_PTYPE_Pos 12 +#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */ +#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos))) +#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos 16 +#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */ +#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos))) +#define USBHS_HSTPIPCFG_INTFRQ_Pos 24 +#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */ +#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos))) +#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */ +#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */ +#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */ +#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */ +#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */ +#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */ +#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */ +#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */ +#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */ +#define USBHS_HSTPIPISR_DTSEQ_Pos 8 +#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos 12 +#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */ +#define USBHS_HSTPIPISR_CURRBK_Pos 14 +#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */ +#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */ +#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */ +#define USBHS_HSTPIPISR_PBYCT_Pos 20 +#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */ +#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */ +#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */ +/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */ +#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */ +#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */ +#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */ +#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */ +#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */ +#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */ +#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */ +#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */ +#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */ +#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */ +#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */ +#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */ +#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */ +#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */ +#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */ +#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */ +#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */ +#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */ +#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */ +#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */ +#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */ +#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */ +#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */ +#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */ +#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */ +#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */ +#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */ +/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos 0 +#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */ +#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos))) +#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */ +/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */ +#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */ +#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */ +#define USBHS_HSTPIPERR_COUNTER_Pos 5 +#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */ +#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos))) +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */ +#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */ +#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */ +#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */ +#define USBHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (USBHS_CTRL) VBUS Hardware Control */ +#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */ +#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */ +#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */ +#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */ +/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */ +#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */ +#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBus Request (Host mode only) */ +#define USBHS_SR_SPEED_Pos 12 +#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */ +#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */ +/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */ +#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBus Request Clear */ +/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */ +#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBus Request Set */ +/* -------- USBHS_TSTA1 : (USBHS Offset: 0x0810) General Test A1 Register -------- */ +#define USBHS_TSTA1_CounterA_Pos 0 +#define USBHS_TSTA1_CounterA_Msk (0x7fffu << USBHS_TSTA1_CounterA_Pos) /**< \brief (USBHS_TSTA1) Counter A */ +#define USBHS_TSTA1_CounterA(value) ((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos))) +#define USBHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (USBHS_TSTA1) Load CounterA */ +#define USBHS_TSTA1_CounterB_Pos 16 +#define USBHS_TSTA1_CounterB_Msk (0x3fu << USBHS_TSTA1_CounterB_Pos) /**< \brief (USBHS_TSTA1) Counter B */ +#define USBHS_TSTA1_CounterB(value) ((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos))) +#define USBHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (USBHS_TSTA1) Load CounterB */ +#define USBHS_TSTA1_SOFCntMa1_Pos 24 +#define USBHS_TSTA1_SOFCntMa1_Msk (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos) /**< \brief (USBHS_TSTA1) SOF Counter Max */ +#define USBHS_TSTA1_SOFCntMa1(value) ((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos))) +#define USBHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (USBHS_TSTA1) Load SOF Counter */ +/* -------- USBHS_TSTA2 : (USBHS Offset: 0x0814) General Test A2 Register -------- */ +#define USBHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (USBHS_TSTA2) Full Detach Enable */ +#define USBHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (USBHS_TSTA2) HS Serial Mode */ +#define USBHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (USBHS_TSTA2) Loop-back Mode */ +#define USBHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (USBHS_TSTA2) Disable Gated Clock */ +#define USBHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (USBHS_TSTA2) Force SuspendM to 1 */ +#define USBHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (USBHS_TSTA2) Bypass DPLL */ +#define USBHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (USBHS_TSTA2) Host HS Disconnect Disable */ +#define USBHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (USBHS_TSTA2) Force HS Reset to 50 ms */ +#define USBHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (USBHS_TSTA2) Remove Pull-up When TX */ +/* -------- USBHS_VERSION : (USBHS Offset: 0x0818) General Version Register -------- */ +#define USBHS_VERSION_VERSION_Pos 0 +#define USBHS_VERSION_VERSION_Msk (0xfffu << USBHS_VERSION_VERSION_Pos) /**< \brief (USBHS_VERSION) Version Number */ +#define USBHS_VERSION_MFN_Pos 16 +#define USBHS_VERSION_MFN_Msk (0xfu << USBHS_VERSION_MFN_Pos) /**< \brief (USBHS_VERSION) Metal Fix Number */ +/* -------- USBHS_FSM : (USBHS Offset: 0x082C) General Finite State Machine Register -------- */ +#define USBHS_FSM_DRDSTATE_Pos 0 +#define USBHS_FSM_DRDSTATE_Msk (0xfu << USBHS_FSM_DRDSTATE_Pos) /**< \brief (USBHS_FSM) Dual Role Device State */ +#define USBHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (USBHS_FSM) This is the start state for A-devices (when the ID pin is 0) */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */ +#define USBHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */ +#define USBHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (USBHS_FSM) In this state, the A-device that operates in Host mode is operational. */ +#define USBHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (USBHS_FSM) The A-device operating as a host is in the Suspend mode. */ +#define USBHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (USBHS_FSM) The A-device operates as a peripheral. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */ +#define USBHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */ +#define USBHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (USBHS_FSM) This is the start state for B-device (when the ID pin is 1). */ +#define USBHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the peripheral. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (USBHS_FSM) In this state, the B-device is in Suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us)) before becoming Host. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */ +#define USBHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the Host. */ +#define USBHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (USBHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */ + +/*@}*/ + + +#endif /* _SAME70_USBHS_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/utmi.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/utmi.h new file mode 100644 index 00000000..89fcd725 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/utmi.h @@ -0,0 +1,68 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UTMI_COMPONENT_ +#define _SAME70_UTMI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */ +/* ============================================================================= */ +/** \addtogroup SAME70_UTMI USB Transmitter Interface Macrocell */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Utmi hardware registers */ +typedef struct { + __I uint32_t Reserved1[4]; + __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */ +} Utmi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */ +#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */ +#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */ +#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */ +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos 0 +#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */ +#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))) +#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */ + +/*@}*/ + + +#endif /* _SAME70_UTMI_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/wdt.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/wdt.h new file mode 100644 index 00000000..655c9934 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/wdt.h @@ -0,0 +1,77 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_WDT_COMPONENT_ +#define _SAME70_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */ + +/*@}*/ + + +#endif /* _SAME70_WDT_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/xdmac.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/xdmac.h new file mode 100644 index 00000000..9c8bd211 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/xdmac.h @@ -0,0 +1,633 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_XDMAC_COMPONENT_ +#define _SAME70_XDMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_XDMAC Extensible DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XdmacChid hardware registers */ +typedef struct { + __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */ + __I uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */ + __I uint32_t Reserved1[2]; +} XdmacChid; +/** \brief Xdmac hardware registers */ +#define XDMACCHID_NUMBER 24 +typedef struct { + __I uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */ + __IO uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */ + __I uint32_t Reserved1[3]; + XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */ + __I uint32_t Reserved2[619]; + __IO uint32_t XDMAC_VERSION; /**< \brief (Xdmac Offset: 0xFFC) XDMAC Version Register */ +} Xdmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos 0 +#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */ +#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) +#define XDMAC_GTYPE_FIFO_SZ_Pos 5 +#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */ +#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) +#define XDMAC_GTYPE_NB_REQ_Pos 16 +#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */ +#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */ +#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */ +#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */ +#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */ +#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilo byte Enable */ +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos 0 +#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */ +#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) +#define XDMAC_GWAC_PW1_Pos 4 +#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */ +#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) +#define XDMAC_GWAC_PW2_Pos 8 +#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */ +#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) +#define XDMAC_GWAC_PW3_Pos 12 +#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */ +#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */ +#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */ +#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */ +#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */ +#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */ +#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */ +#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */ +#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */ +#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */ +#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */ +#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */ +#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */ +#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */ +#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */ +#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */ +#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */ +#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */ +#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */ +#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */ +#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */ +#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */ +#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */ +#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */ +#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */ +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */ +#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */ +#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */ +#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */ +#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */ +#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */ +#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */ +#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */ +#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */ +#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */ +#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */ +#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */ +#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */ +#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */ +#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */ +#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */ +#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */ +#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */ +#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */ +#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */ +#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */ +#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */ +#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */ +#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */ +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */ +#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */ +#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */ +#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */ +#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */ +#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */ +#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */ +#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */ +#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */ +#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */ +#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */ +#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */ +#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */ +#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */ +#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */ +#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */ +#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */ +#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */ +#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */ +#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */ +#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */ +#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */ +#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */ +#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */ +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */ +#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */ +#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */ +#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */ +#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */ +#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */ +#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */ +#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */ +#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */ +#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */ +#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */ +#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */ +#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */ +#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */ +#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */ +#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */ +#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */ +#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */ +#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */ +#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */ +#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */ +#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */ +#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */ +#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */ +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */ +#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */ +#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */ +#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */ +#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */ +#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */ +#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */ +#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */ +#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */ +#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */ +#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */ +#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */ +#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */ +#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */ +#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */ +#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */ +#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */ +#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */ +#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */ +#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */ +#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */ +#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */ +#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */ +#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */ +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */ +#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */ +#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */ +#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */ +#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */ +#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */ +#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */ +#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */ +#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */ +#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */ +#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */ +#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */ +#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */ +#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */ +#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */ +#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */ +#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */ +#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */ +#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */ +#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */ +#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */ +#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */ +#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */ +#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */ +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */ +#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */ +#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */ +#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */ +#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */ +#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */ +#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */ +#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */ +#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */ +#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */ +#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */ +#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */ +#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */ +#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */ +#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */ +#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */ +#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */ +#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */ +#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */ +#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */ +#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */ +#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */ +#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */ +#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */ +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */ +#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */ +#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */ +#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */ +#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */ +#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */ +#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */ +#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */ +#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */ +#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */ +#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */ +#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */ +#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */ +#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */ +#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */ +#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */ +#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */ +#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */ +#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */ +#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */ +#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */ +#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */ +#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */ +#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */ +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */ +#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */ +#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */ +#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */ +#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */ +#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */ +#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */ +#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */ +#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */ +#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */ +#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */ +#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */ +#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */ +#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */ +#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */ +#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */ +#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */ +#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */ +#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */ +#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */ +#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */ +#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */ +#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */ +#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */ +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */ +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */ +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */ +#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */ +#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */ +#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */ +#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */ +#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */ +#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */ +#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */ +#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */ +#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */ +#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */ +#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */ +#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */ +#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */ +#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */ +#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */ +#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */ +#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */ +#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */ +#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */ +#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */ +#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */ +#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */ +#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */ +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */ +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */ +/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */ +#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */ +#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */ +#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */ +#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */ +#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */ +/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */ +#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */ +#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */ +#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */ +#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */ +#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */ +/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */ +#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */ +#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */ +#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */ +#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */ +#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */ +/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */ +#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */ +#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */ +#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */ +#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */ +#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */ +/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */ +#define XDMAC_CSA_SA_Pos 0 +#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */ +#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) +/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */ +#define XDMAC_CDA_DA_Pos 0 +#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */ +#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) +/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */ +#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */ +#define XDMAC_CNDA_NDA_Pos 2 +#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */ +#define XDMAC_CNDA_NDA(value) (XDMAC_CNDA_NDA_Msk & (value)) +/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */ +#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled */ +#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDVIEW_Pos 3 +#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */ +#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) +#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */ +/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */ +#define XDMAC_CUBC_UBLEN_Pos 0 +#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */ +#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) +/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */ +#define XDMAC_CBC_BLEN_Pos 0 +#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */ +#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) +/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */ +#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */ +#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ +#define XDMAC_CC_MBSIZE_Pos 1 +#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */ +#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) +#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */ +#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer */ +#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer */ +#define XDMAC_CC_PROT (0x1u << 5) /**< \brief (XDMAC_CC) Channel x Protection */ +#define XDMAC_CC_PROT_SEC (0x0u << 5) /**< \brief (XDMAC_CC) Channel is secured */ +#define XDMAC_CC_PROT_UNSEC (0x1u << 5) /**< \brief (XDMAC_CC) Channel is unsecured */ +#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated */ +#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */ +#define XDMAC_CC_CSIZE_Pos 8 +#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */ +#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) +#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_DWIDTH_Pos 11 +#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */ +#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) +#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */ +#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0 */ +#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1 */ +#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */ +#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0 */ +#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1 */ +#define XDMAC_CC_SAM_Pos 16 +#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */ +#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) +#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_Pos 18 +#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */ +#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) +#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */ +#define XDMAC_CC_INITD_IN_PROGRESS (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_TERMINATED (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */ +#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */ +#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */ +#define XDMAC_CC_PERID_Pos 24 +#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Identifier */ +#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos 0 +#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) +#define XDMAC_CDS_MSP_DDS_MSP_Pos 16 +#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) +/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */ +#define XDMAC_CSUS_SUBS_Pos 0 +#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */ +#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) +/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */ +#define XDMAC_CDUS_DUBS_Pos 0 +#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */ +#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) +/* -------- XDMAC_VERSION : (XDMAC Offset: 0xFFC) XDMAC Version Register -------- */ +#define XDMAC_VERSION_VERSION_Pos 0 +#define XDMAC_VERSION_VERSION_Msk (0xfffu << XDMAC_VERSION_VERSION_Pos) /**< \brief (XDMAC_VERSION) Version of the Hardware Module */ +#define XDMAC_VERSION_VERSION(value) ((XDMAC_VERSION_VERSION_Msk & ((value) << XDMAC_VERSION_VERSION_Pos))) +#define XDMAC_VERSION_MFN_Pos 16 +#define XDMAC_VERSION_MFN_Msk (0x7u << XDMAC_VERSION_MFN_Pos) /**< \brief (XDMAC_VERSION) Metal Fix Number */ +#define XDMAC_VERSION_MFN(value) ((XDMAC_VERSION_MFN_Msk & ((value) << XDMAC_VERSION_MFN_Pos))) + +/*@}*/ + + +#endif /* _SAME70_XDMAC_COMPONENT_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/acc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/acc.h new file mode 100644 index 00000000..f447d25c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/acc.h @@ -0,0 +1,63 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ACC_INSTANCE_ +#define _SAME70_ACC_INSTANCE_ + +/* ========== Register definition for ACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ACC_CR (0x40044000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (0x40044004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (0x40044024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (0x40044028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (0x40044030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (0x40044094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */ + #define REG_ACC_WPSR (0x400440E8U) /**< \brief (ACC) Write Protection Status Register */ + #define REG_ACC_VER (0x400440FCU) /**< \brief (ACC) Version Register */ +#else + #define REG_ACC_CR (*(__O uint32_t*)0x40044000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (*(__IO uint32_t*)0x40044004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (*(__O uint32_t*)0x40044024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (*(__O uint32_t*)0x40044028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (*(__I uint32_t*)0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (*(__I uint32_t*)0x40044030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (*(__IO uint32_t*)0x40044094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (*(__IO uint32_t*)0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */ + #define REG_ACC_WPSR (*(__I uint32_t*)0x400440E8U) /**< \brief (ACC) Write Protection Status Register */ + #define REG_ACC_VER (*(__I uint32_t*)0x400440FCU) /**< \brief (ACC) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_ACC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/aes.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/aes.h new file mode 100644 index 00000000..713ced12 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/aes.h @@ -0,0 +1,77 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_AES_INSTANCE_ +#define _SAME70_AES_INSTANCE_ + +/* ========== Register definition for AES peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AES_CR (0x4006C000U) /**< \brief (AES) Control Register */ + #define REG_AES_MR (0x4006C004U) /**< \brief (AES) Mode Register */ + #define REG_AES_IER (0x4006C010U) /**< \brief (AES) Interrupt Enable Register */ + #define REG_AES_IDR (0x4006C014U) /**< \brief (AES) Interrupt Disable Register */ + #define REG_AES_IMR (0x4006C018U) /**< \brief (AES) Interrupt Mask Register */ + #define REG_AES_ISR (0x4006C01CU) /**< \brief (AES) Interrupt Status Register */ + #define REG_AES_KEYWR (0x4006C020U) /**< \brief (AES) Key Word Register */ + #define REG_AES_IDATAR (0x4006C040U) /**< \brief (AES) Input Data Register */ + #define REG_AES_ODATAR (0x4006C050U) /**< \brief (AES) Output Data Register */ + #define REG_AES_IVR (0x4006C060U) /**< \brief (AES) Initialization Vector Register */ + #define REG_AES_AADLENR (0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */ + #define REG_AES_CLENR (0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */ + #define REG_AES_GHASHR (0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */ + #define REG_AES_TAGR (0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */ + #define REG_AES_CTRR (0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */ + #define REG_AES_GCMHR (0x4006C09CU) /**< \brief (AES) GCM H Word Register */ + #define REG_AES_VERSION (0x4006C0FCU) /**< \brief (AES) Version Register */ +#else + #define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< \brief (AES) Control Register */ + #define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< \brief (AES) Mode Register */ + #define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< \brief (AES) Interrupt Enable Register */ + #define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< \brief (AES) Interrupt Disable Register */ + #define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< \brief (AES) Interrupt Mask Register */ + #define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< \brief (AES) Interrupt Status Register */ + #define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< \brief (AES) Key Word Register */ + #define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< \brief (AES) Input Data Register */ + #define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< \brief (AES) Output Data Register */ + #define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< \brief (AES) Initialization Vector Register */ + #define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */ + #define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */ + #define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */ + #define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */ + #define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */ + #define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< \brief (AES) GCM H Word Register */ + #define REG_AES_VERSION (*(__I uint32_t*)0x4006C0FCU) /**< \brief (AES) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_AES_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/afec0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/afec0.h new file mode 100644 index 00000000..2bf7de21 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/afec0.h @@ -0,0 +1,103 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_AFEC0_INSTANCE_ +#define _SAME70_AFEC0_INSTANCE_ + +/* ========== Register definition for AFEC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AFEC0_CR (0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */ + #define REG_AFEC0_MR (0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */ + #define REG_AFEC0_EMR (0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */ + #define REG_AFEC0_SEQ1R (0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */ + #define REG_AFEC0_SEQ2R (0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */ + #define REG_AFEC0_CHER (0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */ + #define REG_AFEC0_CHDR (0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */ + #define REG_AFEC0_CHSR (0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */ + #define REG_AFEC0_LCDR (0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */ + #define REG_AFEC0_IER (0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */ + #define REG_AFEC0_IDR (0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */ + #define REG_AFEC0_IMR (0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */ + #define REG_AFEC0_ISR (0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */ + #define REG_AFEC0_OVER (0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */ + #define REG_AFEC0_CWR (0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */ + #define REG_AFEC0_CGR (0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */ + #define REG_AFEC0_DIFFR (0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */ + #define REG_AFEC0_CSELR (0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */ + #define REG_AFEC0_CDR (0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */ + #define REG_AFEC0_COCR (0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */ + #define REG_AFEC0_TEMPMR (0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC0_TEMPCWR (0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */ + #define REG_AFEC0_ACR (0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */ + #define REG_AFEC0_SHMR (0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */ + #define REG_AFEC0_COSR (0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */ + #define REG_AFEC0_CVR (0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */ + #define REG_AFEC0_CECR (0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */ + #define REG_AFEC0_WPMR (0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */ + #define REG_AFEC0_WPSR (0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */ + #define REG_AFEC0_VERSION (0x4003C0FCU) /**< \brief (AFEC0) AFEC Version Register */ +#else + #define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */ + #define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */ + #define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */ + #define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */ + #define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */ + #define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */ + #define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */ + #define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */ + #define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */ + #define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */ + #define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */ + #define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */ + #define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */ + #define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */ + #define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */ + #define REG_AFEC0_CGR (*(__IO uint32_t*)0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */ + #define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */ + #define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */ + #define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */ + #define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */ + #define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */ + #define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */ + #define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */ + #define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */ + #define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */ + #define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */ + #define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */ + #define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */ + #define REG_AFEC0_VERSION (*(__I uint32_t*)0x4003C0FCU) /**< \brief (AFEC0) AFEC Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_AFEC0_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/afec1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/afec1.h new file mode 100644 index 00000000..9713876a --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/afec1.h @@ -0,0 +1,103 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_AFEC1_INSTANCE_ +#define _SAME70_AFEC1_INSTANCE_ + +/* ========== Register definition for AFEC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AFEC1_CR (0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ + #define REG_AFEC1_MR (0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ + #define REG_AFEC1_EMR (0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ + #define REG_AFEC1_SEQ1R (0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ + #define REG_AFEC1_SEQ2R (0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ + #define REG_AFEC1_CHER (0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ + #define REG_AFEC1_CHDR (0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ + #define REG_AFEC1_CHSR (0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ + #define REG_AFEC1_LCDR (0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ + #define REG_AFEC1_IER (0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ + #define REG_AFEC1_IDR (0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ + #define REG_AFEC1_IMR (0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ + #define REG_AFEC1_ISR (0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ + #define REG_AFEC1_OVER (0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ + #define REG_AFEC1_CWR (0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ + #define REG_AFEC1_CGR (0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ + #define REG_AFEC1_DIFFR (0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ + #define REG_AFEC1_CSELR (0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ + #define REG_AFEC1_CDR (0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ + #define REG_AFEC1_COCR (0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ + #define REG_AFEC1_TEMPMR (0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC1_TEMPCWR (0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ + #define REG_AFEC1_ACR (0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ + #define REG_AFEC1_SHMR (0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ + #define REG_AFEC1_COSR (0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ + #define REG_AFEC1_CVR (0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ + #define REG_AFEC1_CECR (0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ + #define REG_AFEC1_WPMR (0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ + #define REG_AFEC1_WPSR (0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ + #define REG_AFEC1_VERSION (0x400640FCU) /**< \brief (AFEC1) AFEC Version Register */ +#else + #define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ + #define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ + #define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ + #define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ + #define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ + #define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ + #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ + #define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ + #define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ + #define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ + #define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ + #define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ + #define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ + #define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ + #define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ + #define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ + #define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ + #define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ + #define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ + #define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ + #define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ + #define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ + #define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ + #define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ + #define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ + #define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ + #define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ + #define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ + #define REG_AFEC1_VERSION (*(__I uint32_t*)0x400640FCU) /**< \brief (AFEC1) AFEC Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_AFEC1_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/chipid.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/chipid.h new file mode 100644 index 00000000..9062e137 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/chipid.h @@ -0,0 +1,47 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_CHIPID_INSTANCE_ +#define _SAME70_CHIPID_INSTANCE_ + +/* ========== Register definition for CHIPID peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_CHIPID_CIDR (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#else + #define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_CHIPID_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/dacc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/dacc.h new file mode 100644 index 00000000..5f7d6827 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/dacc.h @@ -0,0 +1,73 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_DACC_INSTANCE_ +#define _SAME70_DACC_INSTANCE_ + +/* ========== Register definition for DACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_DACC_CR (0x40040000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (0x40040004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_TRIGR (0x40040008U) /**< \brief (DACC) Trigger Register */ + #define REG_DACC_CHER (0x40040010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (0x40040014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (0x40040018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (0x4004001CU) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (0x40040024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (0x40040028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (0x40040030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (0x40040094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (0x400400E4U) /**< \brief (DACC) Write Protection Mode Register */ + #define REG_DACC_WPSR (0x400400E8U) /**< \brief (DACC) Write Protection Status Register */ + #define REG_DACC_VERSION (0x400400FCU) /**< \brief (DACC) Version Register */ +#else + #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< \brief (DACC) Trigger Register */ + #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< \brief (DACC) Write Protection Mode Register */ + #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< \brief (DACC) Write Protection Status Register */ + #define REG_DACC_VERSION (*(__I uint32_t*)0x400400FCU) /**< \brief (DACC) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_DACC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/efc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/efc.h new file mode 100644 index 00000000..966f2d2c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/efc.h @@ -0,0 +1,55 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_EFC_INSTANCE_ +#define _SAME70_EFC_INSTANCE_ + +/* ========== Register definition for EFC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_EFC_FMR (0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */ + #define REG_EFC_VERSION (0x400E0C14U) /**< \brief (EFC) EEFC Version Register */ + #define REG_EFC_WPMR (0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */ +#else + #define REG_EFC_FMR (*(__IO uint32_t*)0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (*(__O uint32_t*)0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (*(__I uint32_t*)0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (*(__I uint32_t*)0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */ + #define REG_EFC_VERSION (*(__I uint32_t*)0x400E0C14U) /**< \brief (EFC) EEFC Version Register */ + #define REG_EFC_WPMR (*(__IO uint32_t*)0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_EFC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/gmac.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/gmac.h new file mode 100644 index 00000000..7da518b7 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/gmac.h @@ -0,0 +1,385 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_GMAC_INSTANCE_ +#define _SAME70_GMAC_INSTANCE_ + +/* ========== Register definition for GMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_GMAC_NCR (0x40050000U) /**< \brief (GMAC) Network Control Register */ + #define REG_GMAC_NCFGR (0x40050004U) /**< \brief (GMAC) Network Configuration Register */ + #define REG_GMAC_NSR (0x40050008U) /**< \brief (GMAC) Network Status Register */ + #define REG_GMAC_UR (0x4005000CU) /**< \brief (GMAC) User Register */ + #define REG_GMAC_DCFGR (0x40050010U) /**< \brief (GMAC) DMA Configuration Register */ + #define REG_GMAC_TSR (0x40050014U) /**< \brief (GMAC) Transmit Status Register */ + #define REG_GMAC_RBQB (0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register */ + #define REG_GMAC_TBQB (0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register */ + #define REG_GMAC_RSR (0x40050020U) /**< \brief (GMAC) Receive Status Register */ + #define REG_GMAC_ISR (0x40050024U) /**< \brief (GMAC) Interrupt Status Register */ + #define REG_GMAC_IER (0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */ + #define REG_GMAC_IDR (0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */ + #define REG_GMAC_IMR (0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */ + #define REG_GMAC_MAN (0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */ + #define REG_GMAC_RPQ (0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */ + #define REG_GMAC_TPQ (0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ + #define REG_GMAC_TPSF (0x40050040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ + #define REG_GMAC_RPSF (0x40050044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ + #define REG_GMAC_RJFML (0x40050048U) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */ + #define REG_GMAC_HRB (0x40050080U) /**< \brief (GMAC) Hash Register Bottom */ + #define REG_GMAC_HRT (0x40050084U) /**< \brief (GMAC) Hash Register Top */ + #define REG_GMAC_SAB1 (0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom Register */ + #define REG_GMAC_SAT1 (0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top Register */ + #define REG_GMAC_SAB2 (0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom Register */ + #define REG_GMAC_SAT2 (0x40050094U) /**< \brief (GMAC) Specific Address 2 Top Register */ + #define REG_GMAC_SAB3 (0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom Register */ + #define REG_GMAC_SAT3 (0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top Register */ + #define REG_GMAC_SAB4 (0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom Register */ + #define REG_GMAC_SAT4 (0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top Register */ + #define REG_GMAC_TIDM1 (0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */ + #define REG_GMAC_TIDM2 (0x400500ACU) /**< \brief (GMAC) Type ID Match 2 Register */ + #define REG_GMAC_TIDM3 (0x400500B0U) /**< \brief (GMAC) Type ID Match 3 Register */ + #define REG_GMAC_TIDM4 (0x400500B4U) /**< \brief (GMAC) Type ID Match 4 Register */ + #define REG_GMAC_WOL (0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */ + #define REG_GMAC_IPGS (0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */ + #define REG_GMAC_SVLAN (0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */ + #define REG_GMAC_TPFCP (0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ + #define REG_GMAC_SAMB1 (0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom Register */ + #define REG_GMAC_SAMT1 (0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top Register */ + #define REG_GMAC_NSC (0x400500DCU) /**< \brief (GMAC) 1588 Timer Nanosecond Comparison Register */ + #define REG_GMAC_SCL (0x400500E0U) /**< \brief (GMAC) 1588 Timer Second Comparison Low Register */ + #define REG_GMAC_SCH (0x400500E4U) /**< \brief (GMAC) 1588 Timer Second Comparison High Register */ + #define REG_GMAC_EFTSH (0x400500E8U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_EFRSH (0x400500ECU) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */ + #define REG_GMAC_PEFTSH (0x400500F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_PEFRSH (0x400500F4U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */ + #define REG_GMAC_MID (0x400500FCU) /**< \brief (GMAC) Module ID Register */ + #define REG_GMAC_OTLO (0x40050100U) /**< \brief (GMAC) Octets Transmitted Low Register */ + #define REG_GMAC_OTHI (0x40050104U) /**< \brief (GMAC) Octets Transmitted High Register */ + #define REG_GMAC_FT (0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */ + #define REG_GMAC_BCFT (0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ + #define REG_GMAC_MFT (0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ + #define REG_GMAC_PFT (0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ + #define REG_GMAC_BFT64 (0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT127 (0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT255 (0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT511 (0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1023 (0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1518 (0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_GTBFT1518 (0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_TUR (0x40050134U) /**< \brief (GMAC) Transmit Underruns Register */ + #define REG_GMAC_SCF (0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */ + #define REG_GMAC_MCF (0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */ + #define REG_GMAC_EC (0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */ + #define REG_GMAC_LC (0x40050144U) /**< \brief (GMAC) Late Collisions Register */ + #define REG_GMAC_DTF (0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ + #define REG_GMAC_CSE (0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register */ + #define REG_GMAC_ORLO (0x40050150U) /**< \brief (GMAC) Octets Received Low Received Register */ + #define REG_GMAC_ORHI (0x40050154U) /**< \brief (GMAC) Octets Received High Received Register */ + #define REG_GMAC_FR (0x40050158U) /**< \brief (GMAC) Frames Received Register */ + #define REG_GMAC_BCFR (0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */ + #define REG_GMAC_MFR (0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */ + #define REG_GMAC_PFR (0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */ + #define REG_GMAC_BFR64 (0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ + #define REG_GMAC_TBFR127 (0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ + #define REG_GMAC_TBFR255 (0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ + #define REG_GMAC_TBFR511 (0x40050174U) /**< \brief (GMAC) 256 to 511 Byte Frames Received Register */ + #define REG_GMAC_TBFR1023 (0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ + #define REG_GMAC_TBFR1518 (0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ + #define REG_GMAC_TMXBFR (0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ + #define REG_GMAC_UFR (0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */ + #define REG_GMAC_OFR (0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */ + #define REG_GMAC_JR (0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */ + #define REG_GMAC_FCSE (0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ + #define REG_GMAC_LFFE (0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */ + #define REG_GMAC_RSE (0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */ + #define REG_GMAC_AE (0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */ + #define REG_GMAC_RRE (0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */ + #define REG_GMAC_ROE (0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */ + #define REG_GMAC_IHCE (0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ + #define REG_GMAC_TCE (0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ + #define REG_GMAC_UCE (0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ + #define REG_GMAC_TISUBN (0x400501BCU) /**< \brief (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ + #define REG_GMAC_TSH (0x400501C0U) /**< \brief (GMAC) 1588 Timer Seconds High Register */ + #define REG_GMAC_TSL (0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Low Register */ + #define REG_GMAC_TN (0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ + #define REG_GMAC_TA (0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ + #define REG_GMAC_TI (0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ + #define REG_GMAC_EFTSL (0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_EFTN (0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_EFRSL (0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */ + #define REG_GMAC_EFRN (0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds Register */ + #define REG_GMAC_PEFTSL (0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_PEFTN (0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_PEFRSL (0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */ + #define REG_GMAC_PEFRN (0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ + #define REG_GMAC_RXLPI (0x40050270U) /**< \brief (GMAC) Received LPI Transitions */ + #define REG_GMAC_RXLPITIME (0x40050274U) /**< \brief (GMAC) Received LPI Time */ + #define REG_GMAC_TXLPI (0x40050278U) /**< \brief (GMAC) Transmit LPI Transitions */ + #define REG_GMAC_TXLPITIME (0x4005027CU) /**< \brief (GMAC) Transmit LPI Time */ + #define REG_GMAC_ISRPQ (0x400503FCU) /**< \brief (GMAC) Interrupt Status Register Priority Queue (index = 1) */ + #define REG_GMAC_TBQBAPQ (0x4005043CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBQBAPQ (0x4005047CU) /**< \brief (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBSRPQ (0x4005049CU) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue (index = 1) */ + #define REG_GMAC_CBSCR (0x400504BCU) /**< \brief (GMAC) Credit-Based Shaping Control Register */ + #define REG_GMAC_CBSISQA (0x400504C0U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ + #define REG_GMAC_CBSISQB (0x400504C4U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ + #define REG_GMAC_ST1RPQ (0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue (index = 0) */ + #define REG_GMAC_ST2RPQ (0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue (index = 0) */ + #define REG_GMAC_IERPQ (0x400505FCU) /**< \brief (GMAC) Interrupt Enable Register Priority Queue (index = 1) */ + #define REG_GMAC_IDRPQ (0x4005061CU) /**< \brief (GMAC) Interrupt Disable Register Priority Queue (index = 1) */ + #define REG_GMAC_IMRPQ (0x4005063CU) /**< \brief (GMAC) Interrupt Mask Register Priority Queue (index = 1) */ + #define REG_GMAC_ST2ER (0x400506E0U) /**< \brief (GMAC) Screening Type 2 Ethertype Register (index = 0) */ + #define REG_GMAC_ST2CW00 (0x40050700U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */ + #define REG_GMAC_ST2CW10 (0x40050704U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */ + #define REG_GMAC_ST2CW01 (0x40050708U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */ + #define REG_GMAC_ST2CW11 (0x4005070CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */ + #define REG_GMAC_ST2CW02 (0x40050710U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */ + #define REG_GMAC_ST2CW12 (0x40050714U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */ + #define REG_GMAC_ST2CW03 (0x40050718U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */ + #define REG_GMAC_ST2CW13 (0x4005071CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */ + #define REG_GMAC_ST2CW04 (0x40050720U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */ + #define REG_GMAC_ST2CW14 (0x40050724U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */ + #define REG_GMAC_ST2CW05 (0x40050728U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */ + #define REG_GMAC_ST2CW15 (0x4005072CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */ + #define REG_GMAC_ST2CW06 (0x40050730U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */ + #define REG_GMAC_ST2CW16 (0x40050734U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */ + #define REG_GMAC_ST2CW07 (0x40050738U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */ + #define REG_GMAC_ST2CW17 (0x4005073CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */ + #define REG_GMAC_ST2CW08 (0x40050740U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */ + #define REG_GMAC_ST2CW18 (0x40050744U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */ + #define REG_GMAC_ST2CW09 (0x40050748U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */ + #define REG_GMAC_ST2CW19 (0x4005074CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */ + #define REG_GMAC_ST2CW010 (0x40050750U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */ + #define REG_GMAC_ST2CW110 (0x40050754U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */ + #define REG_GMAC_ST2CW011 (0x40050758U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */ + #define REG_GMAC_ST2CW111 (0x4005075CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */ + #define REG_GMAC_ST2CW012 (0x40050760U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */ + #define REG_GMAC_ST2CW112 (0x40050764U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */ + #define REG_GMAC_ST2CW013 (0x40050768U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */ + #define REG_GMAC_ST2CW113 (0x4005076CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */ + #define REG_GMAC_ST2CW014 (0x40050770U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */ + #define REG_GMAC_ST2CW114 (0x40050774U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */ + #define REG_GMAC_ST2CW015 (0x40050778U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */ + #define REG_GMAC_ST2CW115 (0x4005077CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */ + #define REG_GMAC_ST2CW016 (0x40050780U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */ + #define REG_GMAC_ST2CW116 (0x40050784U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */ + #define REG_GMAC_ST2CW017 (0x40050788U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */ + #define REG_GMAC_ST2CW117 (0x4005078CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */ + #define REG_GMAC_ST2CW018 (0x40050790U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */ + #define REG_GMAC_ST2CW118 (0x40050794U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */ + #define REG_GMAC_ST2CW019 (0x40050798U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */ + #define REG_GMAC_ST2CW119 (0x4005079CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */ + #define REG_GMAC_ST2CW020 (0x400507A0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */ + #define REG_GMAC_ST2CW120 (0x400507A4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */ + #define REG_GMAC_ST2CW021 (0x400507A8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */ + #define REG_GMAC_ST2CW121 (0x400507ACU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */ + #define REG_GMAC_ST2CW022 (0x400507B0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */ + #define REG_GMAC_ST2CW122 (0x400507B4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */ + #define REG_GMAC_ST2CW023 (0x400507B8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */ + #define REG_GMAC_ST2CW123 (0x400507BCU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */ +#else + #define REG_GMAC_NCR (*(__IO uint32_t*)0x40050000U) /**< \brief (GMAC) Network Control Register */ + #define REG_GMAC_NCFGR (*(__IO uint32_t*)0x40050004U) /**< \brief (GMAC) Network Configuration Register */ + #define REG_GMAC_NSR (*(__I uint32_t*)0x40050008U) /**< \brief (GMAC) Network Status Register */ + #define REG_GMAC_UR (*(__IO uint32_t*)0x4005000CU) /**< \brief (GMAC) User Register */ + #define REG_GMAC_DCFGR (*(__IO uint32_t*)0x40050010U) /**< \brief (GMAC) DMA Configuration Register */ + #define REG_GMAC_TSR (*(__IO uint32_t*)0x40050014U) /**< \brief (GMAC) Transmit Status Register */ + #define REG_GMAC_RBQB (*(__IO uint32_t*)0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register */ + #define REG_GMAC_TBQB (*(__IO uint32_t*)0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register */ + #define REG_GMAC_RSR (*(__IO uint32_t*)0x40050020U) /**< \brief (GMAC) Receive Status Register */ + #define REG_GMAC_ISR (*(__I uint32_t*)0x40050024U) /**< \brief (GMAC) Interrupt Status Register */ + #define REG_GMAC_IER (*(__O uint32_t*)0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */ + #define REG_GMAC_IDR (*(__O uint32_t*)0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */ + #define REG_GMAC_IMR (*(__IO uint32_t*)0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */ + #define REG_GMAC_MAN (*(__IO uint32_t*)0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */ + #define REG_GMAC_RPQ (*(__I uint32_t*)0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */ + #define REG_GMAC_TPQ (*(__IO uint32_t*)0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ + #define REG_GMAC_TPSF (*(__IO uint32_t*)0x40050040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ + #define REG_GMAC_RPSF (*(__IO uint32_t*)0x40050044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ + #define REG_GMAC_RJFML (*(__IO uint32_t*)0x40050048U) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */ + #define REG_GMAC_HRB (*(__IO uint32_t*)0x40050080U) /**< \brief (GMAC) Hash Register Bottom */ + #define REG_GMAC_HRT (*(__IO uint32_t*)0x40050084U) /**< \brief (GMAC) Hash Register Top */ + #define REG_GMAC_SAB1 (*(__IO uint32_t*)0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom Register */ + #define REG_GMAC_SAT1 (*(__IO uint32_t*)0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top Register */ + #define REG_GMAC_SAB2 (*(__IO uint32_t*)0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom Register */ + #define REG_GMAC_SAT2 (*(__IO uint32_t*)0x40050094U) /**< \brief (GMAC) Specific Address 2 Top Register */ + #define REG_GMAC_SAB3 (*(__IO uint32_t*)0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom Register */ + #define REG_GMAC_SAT3 (*(__IO uint32_t*)0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top Register */ + #define REG_GMAC_SAB4 (*(__IO uint32_t*)0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom Register */ + #define REG_GMAC_SAT4 (*(__IO uint32_t*)0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top Register */ + #define REG_GMAC_TIDM1 (*(__IO uint32_t*)0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */ + #define REG_GMAC_TIDM2 (*(__IO uint32_t*)0x400500ACU) /**< \brief (GMAC) Type ID Match 2 Register */ + #define REG_GMAC_TIDM3 (*(__IO uint32_t*)0x400500B0U) /**< \brief (GMAC) Type ID Match 3 Register */ + #define REG_GMAC_TIDM4 (*(__IO uint32_t*)0x400500B4U) /**< \brief (GMAC) Type ID Match 4 Register */ + #define REG_GMAC_WOL (*(__IO uint32_t*)0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */ + #define REG_GMAC_IPGS (*(__IO uint32_t*)0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */ + #define REG_GMAC_SVLAN (*(__IO uint32_t*)0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */ + #define REG_GMAC_TPFCP (*(__IO uint32_t*)0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ + #define REG_GMAC_SAMB1 (*(__IO uint32_t*)0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom Register */ + #define REG_GMAC_SAMT1 (*(__IO uint32_t*)0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top Register */ + #define REG_GMAC_NSC (*(__IO uint32_t*)0x400500DCU) /**< \brief (GMAC) 1588 Timer Nanosecond Comparison Register */ + #define REG_GMAC_SCL (*(__IO uint32_t*)0x400500E0U) /**< \brief (GMAC) 1588 Timer Second Comparison Low Register */ + #define REG_GMAC_SCH (*(__IO uint32_t*)0x400500E4U) /**< \brief (GMAC) 1588 Timer Second Comparison High Register */ + #define REG_GMAC_EFTSH (*(__I uint32_t*)0x400500E8U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_EFRSH (*(__I uint32_t*)0x400500ECU) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */ + #define REG_GMAC_PEFTSH (*(__I uint32_t*)0x400500F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_PEFRSH (*(__I uint32_t*)0x400500F4U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */ + #define REG_GMAC_MID (*(__I uint32_t*)0x400500FCU) /**< \brief (GMAC) Module ID Register */ + #define REG_GMAC_OTLO (*(__I uint32_t*)0x40050100U) /**< \brief (GMAC) Octets Transmitted Low Register */ + #define REG_GMAC_OTHI (*(__I uint32_t*)0x40050104U) /**< \brief (GMAC) Octets Transmitted High Register */ + #define REG_GMAC_FT (*(__I uint32_t*)0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */ + #define REG_GMAC_BCFT (*(__I uint32_t*)0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ + #define REG_GMAC_MFT (*(__I uint32_t*)0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ + #define REG_GMAC_PFT (*(__I uint32_t*)0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ + #define REG_GMAC_BFT64 (*(__I uint32_t*)0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT127 (*(__I uint32_t*)0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT255 (*(__I uint32_t*)0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT511 (*(__I uint32_t*)0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1023 (*(__I uint32_t*)0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1518 (*(__I uint32_t*)0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_GTBFT1518 (*(__I uint32_t*)0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_TUR (*(__I uint32_t*)0x40050134U) /**< \brief (GMAC) Transmit Underruns Register */ + #define REG_GMAC_SCF (*(__I uint32_t*)0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */ + #define REG_GMAC_MCF (*(__I uint32_t*)0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */ + #define REG_GMAC_EC (*(__I uint32_t*)0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */ + #define REG_GMAC_LC (*(__I uint32_t*)0x40050144U) /**< \brief (GMAC) Late Collisions Register */ + #define REG_GMAC_DTF (*(__I uint32_t*)0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ + #define REG_GMAC_CSE (*(__I uint32_t*)0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register */ + #define REG_GMAC_ORLO (*(__I uint32_t*)0x40050150U) /**< \brief (GMAC) Octets Received Low Received Register */ + #define REG_GMAC_ORHI (*(__I uint32_t*)0x40050154U) /**< \brief (GMAC) Octets Received High Received Register */ + #define REG_GMAC_FR (*(__I uint32_t*)0x40050158U) /**< \brief (GMAC) Frames Received Register */ + #define REG_GMAC_BCFR (*(__I uint32_t*)0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */ + #define REG_GMAC_MFR (*(__I uint32_t*)0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */ + #define REG_GMAC_PFR (*(__I uint32_t*)0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */ + #define REG_GMAC_BFR64 (*(__I uint32_t*)0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ + #define REG_GMAC_TBFR127 (*(__I uint32_t*)0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ + #define REG_GMAC_TBFR255 (*(__I uint32_t*)0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ + #define REG_GMAC_TBFR511 (*(__I uint32_t*)0x40050174U) /**< \brief (GMAC) 256 to 511 Byte Frames Received Register */ + #define REG_GMAC_TBFR1023 (*(__I uint32_t*)0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ + #define REG_GMAC_TBFR1518 (*(__I uint32_t*)0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ + #define REG_GMAC_TMXBFR (*(__I uint32_t*)0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ + #define REG_GMAC_UFR (*(__I uint32_t*)0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */ + #define REG_GMAC_OFR (*(__I uint32_t*)0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */ + #define REG_GMAC_JR (*(__I uint32_t*)0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */ + #define REG_GMAC_FCSE (*(__I uint32_t*)0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ + #define REG_GMAC_LFFE (*(__I uint32_t*)0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */ + #define REG_GMAC_RSE (*(__I uint32_t*)0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */ + #define REG_GMAC_AE (*(__I uint32_t*)0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */ + #define REG_GMAC_RRE (*(__I uint32_t*)0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */ + #define REG_GMAC_ROE (*(__I uint32_t*)0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */ + #define REG_GMAC_IHCE (*(__I uint32_t*)0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ + #define REG_GMAC_TCE (*(__I uint32_t*)0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ + #define REG_GMAC_UCE (*(__I uint32_t*)0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ + #define REG_GMAC_TISUBN (*(__IO uint32_t*)0x400501BCU) /**< \brief (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ + #define REG_GMAC_TSH (*(__IO uint32_t*)0x400501C0U) /**< \brief (GMAC) 1588 Timer Seconds High Register */ + #define REG_GMAC_TSL (*(__IO uint32_t*)0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Low Register */ + #define REG_GMAC_TN (*(__IO uint32_t*)0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ + #define REG_GMAC_TA (*(__O uint32_t*)0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ + #define REG_GMAC_TI (*(__IO uint32_t*)0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ + #define REG_GMAC_EFTSL (*(__I uint32_t*)0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_EFTN (*(__I uint32_t*)0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_EFRSL (*(__I uint32_t*)0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */ + #define REG_GMAC_EFRN (*(__I uint32_t*)0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds Register */ + #define REG_GMAC_PEFTSL (*(__I uint32_t*)0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_PEFTN (*(__I uint32_t*)0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_PEFRSL (*(__I uint32_t*)0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */ + #define REG_GMAC_PEFRN (*(__I uint32_t*)0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ + #define REG_GMAC_RXLPI (*(__I uint32_t*)0x40050270U) /**< \brief (GMAC) Received LPI Transitions */ + #define REG_GMAC_RXLPITIME (*(__I uint32_t*)0x40050274U) /**< \brief (GMAC) Received LPI Time */ + #define REG_GMAC_TXLPI (*(__I uint32_t*)0x40050278U) /**< \brief (GMAC) Transmit LPI Transitions */ + #define REG_GMAC_TXLPITIME (*(__I uint32_t*)0x4005027CU) /**< \brief (GMAC) Transmit LPI Time */ + #define REG_GMAC_ISRPQ (*(__I uint32_t*)0x400503FCU) /**< \brief (GMAC) Interrupt Status Register Priority Queue (index = 1) 0 */ + #define REG_GMAC_TBQBAPQ (*(__IO uint32_t*)0x4005043CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBQBAPQ (*(__IO uint32_t*)0x4005047CU) /**< \brief (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBSRPQ (*(__IO uint32_t*)0x4005049CU) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue (index = 1) */ + #define REG_GMAC_CBSCR (*(__IO uint32_t*)0x400504BCU) /**< \brief (GMAC) Credit-Based Shaping Control Register */ + #define REG_GMAC_CBSISQA (*(__IO uint32_t*)0x400504C0U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ + #define REG_GMAC_CBSISQB (*(__IO uint32_t*)0x400504C4U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ + #define REG_GMAC_ST1RPQ (*(__IO uint32_t*)0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue (index = 0) */ + #define REG_GMAC_ST2RPQ (*(__IO uint32_t*)0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue (index = 0) */ + #define REG_GMAC_IERPQ (*(__O uint32_t*)0x400505FCU) /**< \brief (GMAC) Interrupt Enable Register Priority Queue (index = 1) */ + #define REG_GMAC_IDRPQ (*(__O uint32_t*)0x4005061CU) /**< \brief (GMAC) Interrupt Disable Register Priority Queue (index = 1) */ + #define REG_GMAC_IMRPQ (*(__IO uint32_t*)0x4005063CU) /**< \brief (GMAC) Interrupt Mask Register Priority Queue (index = 1) */ + #define REG_GMAC_ST2ER (*(__IO uint32_t*)0x400506E0U) /**< \brief (GMAC) Screening Type 2 Ethertype Register (index = 0) */ + #define REG_GMAC_ST2CW00 (*(__IO uint32_t*)0x40050700U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */ + #define REG_GMAC_ST2CW10 (*(__IO uint32_t*)0x40050704U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */ + #define REG_GMAC_ST2CW01 (*(__IO uint32_t*)0x40050708U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */ + #define REG_GMAC_ST2CW11 (*(__IO uint32_t*)0x4005070CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */ + #define REG_GMAC_ST2CW02 (*(__IO uint32_t*)0x40050710U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */ + #define REG_GMAC_ST2CW12 (*(__IO uint32_t*)0x40050714U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */ + #define REG_GMAC_ST2CW03 (*(__IO uint32_t*)0x40050718U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */ + #define REG_GMAC_ST2CW13 (*(__IO uint32_t*)0x4005071CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */ + #define REG_GMAC_ST2CW04 (*(__IO uint32_t*)0x40050720U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */ + #define REG_GMAC_ST2CW14 (*(__IO uint32_t*)0x40050724U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */ + #define REG_GMAC_ST2CW05 (*(__IO uint32_t*)0x40050728U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */ + #define REG_GMAC_ST2CW15 (*(__IO uint32_t*)0x4005072CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */ + #define REG_GMAC_ST2CW06 (*(__IO uint32_t*)0x40050730U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */ + #define REG_GMAC_ST2CW16 (*(__IO uint32_t*)0x40050734U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */ + #define REG_GMAC_ST2CW07 (*(__IO uint32_t*)0x40050738U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */ + #define REG_GMAC_ST2CW17 (*(__IO uint32_t*)0x4005073CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */ + #define REG_GMAC_ST2CW08 (*(__IO uint32_t*)0x40050740U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */ + #define REG_GMAC_ST2CW18 (*(__IO uint32_t*)0x40050744U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */ + #define REG_GMAC_ST2CW09 (*(__IO uint32_t*)0x40050748U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */ + #define REG_GMAC_ST2CW19 (*(__IO uint32_t*)0x4005074CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */ + #define REG_GMAC_ST2CW010 (*(__IO uint32_t*)0x40050750U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */ + #define REG_GMAC_ST2CW110 (*(__IO uint32_t*)0x40050754U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */ + #define REG_GMAC_ST2CW011 (*(__IO uint32_t*)0x40050758U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */ + #define REG_GMAC_ST2CW111 (*(__IO uint32_t*)0x4005075CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */ + #define REG_GMAC_ST2CW012 (*(__IO uint32_t*)0x40050760U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */ + #define REG_GMAC_ST2CW112 (*(__IO uint32_t*)0x40050764U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */ + #define REG_GMAC_ST2CW013 (*(__IO uint32_t*)0x40050768U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */ + #define REG_GMAC_ST2CW113 (*(__IO uint32_t*)0x4005076CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */ + #define REG_GMAC_ST2CW014 (*(__IO uint32_t*)0x40050770U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */ + #define REG_GMAC_ST2CW114 (*(__IO uint32_t*)0x40050774U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */ + #define REG_GMAC_ST2CW015 (*(__IO uint32_t*)0x40050778U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */ + #define REG_GMAC_ST2CW115 (*(__IO uint32_t*)0x4005077CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */ + #define REG_GMAC_ST2CW016 (*(__IO uint32_t*)0x40050780U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */ + #define REG_GMAC_ST2CW116 (*(__IO uint32_t*)0x40050784U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */ + #define REG_GMAC_ST2CW017 (*(__IO uint32_t*)0x40050788U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */ + #define REG_GMAC_ST2CW117 (*(__IO uint32_t*)0x4005078CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */ + #define REG_GMAC_ST2CW018 (*(__IO uint32_t*)0x40050790U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */ + #define REG_GMAC_ST2CW118 (*(__IO uint32_t*)0x40050794U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */ + #define REG_GMAC_ST2CW019 (*(__IO uint32_t*)0x40050798U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */ + #define REG_GMAC_ST2CW119 (*(__IO uint32_t*)0x4005079CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */ + #define REG_GMAC_ST2CW020 (*(__IO uint32_t*)0x400507A0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */ + #define REG_GMAC_ST2CW120 (*(__IO uint32_t*)0x400507A4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */ + #define REG_GMAC_ST2CW021 (*(__IO uint32_t*)0x400507A8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */ + #define REG_GMAC_ST2CW121 (*(__IO uint32_t*)0x400507ACU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */ + #define REG_GMAC_ST2CW022 (*(__IO uint32_t*)0x400507B0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */ + #define REG_GMAC_ST2CW122 (*(__IO uint32_t*)0x400507B4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */ + #define REG_GMAC_ST2CW023 (*(__IO uint32_t*)0x400507B8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */ + #define REG_GMAC_ST2CW123 (*(__IO uint32_t*)0x400507BCU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_GMAC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/gpbr.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/gpbr.h new file mode 100644 index 00000000..5ac6c8a9 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/gpbr.h @@ -0,0 +1,45 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_GPBR_INSTANCE_ +#define _SAME70_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_GPBR_GPBR (0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */ +#else + #define REG_GPBR_GPBR (*(__IO uint32_t*)0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_GPBR_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/hsmci.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/hsmci.h new file mode 100644 index 00000000..f52aeab2 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/hsmci.h @@ -0,0 +1,85 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_HSMCI_INSTANCE_ +#define _SAME70_HSMCI_INSTANCE_ + +/* ========== Register definition for HSMCI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ + #define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_VERSION (0x400000FCU) /**< \brief (HSMCI) Version Register */ + #define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#else + #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ + #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_VERSION (*(__I uint32_t*)0x400000FCU) /**< \brief (HSMCI) Version Register */ + #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_HSMCI_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/i2sc0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/i2sc0.h new file mode 100644 index 00000000..3f12dac6 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/i2sc0.h @@ -0,0 +1,65 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_I2SC0_INSTANCE_ +#define _SAME70_I2SC0_INSTANCE_ + +/* ========== Register definition for I2SC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_I2SC0_CR (0x4008C000U) /**< \brief (I2SC0) Control Register */ + #define REG_I2SC0_MR (0x4008C004U) /**< \brief (I2SC0) Mode Register */ + #define REG_I2SC0_SR (0x4008C008U) /**< \brief (I2SC0) Status Register */ + #define REG_I2SC0_SCR (0x4008C00CU) /**< \brief (I2SC0) Status Clear Register */ + #define REG_I2SC0_SSR (0x4008C010U) /**< \brief (I2SC0) Status Set Register */ + #define REG_I2SC0_IER (0x4008C014U) /**< \brief (I2SC0) Interrupt Enable Register */ + #define REG_I2SC0_IDR (0x4008C018U) /**< \brief (I2SC0) Interrupt Disable Register */ + #define REG_I2SC0_IMR (0x4008C01CU) /**< \brief (I2SC0) Interrupt Mask Register */ + #define REG_I2SC0_RHR (0x4008C020U) /**< \brief (I2SC0) Receiver Holding Register */ + #define REG_I2SC0_THR (0x4008C024U) /**< \brief (I2SC0) Transmitter Holding Register */ + #define REG_I2SC0_VERSION (0x4008C028U) /**< \brief (I2SC0) Version Register */ +#else + #define REG_I2SC0_CR (*(__O uint32_t*)0x4008C000U) /**< \brief (I2SC0) Control Register */ + #define REG_I2SC0_MR (*(__IO uint32_t*)0x4008C004U) /**< \brief (I2SC0) Mode Register */ + #define REG_I2SC0_SR (*(__I uint32_t*)0x4008C008U) /**< \brief (I2SC0) Status Register */ + #define REG_I2SC0_SCR (*(__O uint32_t*)0x4008C00CU) /**< \brief (I2SC0) Status Clear Register */ + #define REG_I2SC0_SSR (*(__O uint32_t*)0x4008C010U) /**< \brief (I2SC0) Status Set Register */ + #define REG_I2SC0_IER (*(__O uint32_t*)0x4008C014U) /**< \brief (I2SC0) Interrupt Enable Register */ + #define REG_I2SC0_IDR (*(__O uint32_t*)0x4008C018U) /**< \brief (I2SC0) Interrupt Disable Register */ + #define REG_I2SC0_IMR (*(__I uint32_t*)0x4008C01CU) /**< \brief (I2SC0) Interrupt Mask Register */ + #define REG_I2SC0_RHR (*(__I uint32_t*)0x4008C020U) /**< \brief (I2SC0) Receiver Holding Register */ + #define REG_I2SC0_THR (*(__O uint32_t*)0x4008C024U) /**< \brief (I2SC0) Transmitter Holding Register */ + #define REG_I2SC0_VERSION (*(__I uint32_t*)0x4008C028U) /**< \brief (I2SC0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_I2SC0_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/i2sc1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/i2sc1.h new file mode 100644 index 00000000..32d403b5 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/i2sc1.h @@ -0,0 +1,65 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_I2SC1_INSTANCE_ +#define _SAME70_I2SC1_INSTANCE_ + +/* ========== Register definition for I2SC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_I2SC1_CR (0x40090000U) /**< \brief (I2SC1) Control Register */ + #define REG_I2SC1_MR (0x40090004U) /**< \brief (I2SC1) Mode Register */ + #define REG_I2SC1_SR (0x40090008U) /**< \brief (I2SC1) Status Register */ + #define REG_I2SC1_SCR (0x4009000CU) /**< \brief (I2SC1) Status Clear Register */ + #define REG_I2SC1_SSR (0x40090010U) /**< \brief (I2SC1) Status Set Register */ + #define REG_I2SC1_IER (0x40090014U) /**< \brief (I2SC1) Interrupt Enable Register */ + #define REG_I2SC1_IDR (0x40090018U) /**< \brief (I2SC1) Interrupt Disable Register */ + #define REG_I2SC1_IMR (0x4009001CU) /**< \brief (I2SC1) Interrupt Mask Register */ + #define REG_I2SC1_RHR (0x40090020U) /**< \brief (I2SC1) Receiver Holding Register */ + #define REG_I2SC1_THR (0x40090024U) /**< \brief (I2SC1) Transmitter Holding Register */ + #define REG_I2SC1_VERSION (0x40090028U) /**< \brief (I2SC1) Version Register */ +#else + #define REG_I2SC1_CR (*(__O uint32_t*)0x40090000U) /**< \brief (I2SC1) Control Register */ + #define REG_I2SC1_MR (*(__IO uint32_t*)0x40090004U) /**< \brief (I2SC1) Mode Register */ + #define REG_I2SC1_SR (*(__I uint32_t*)0x40090008U) /**< \brief (I2SC1) Status Register */ + #define REG_I2SC1_SCR (*(__O uint32_t*)0x4009000CU) /**< \brief (I2SC1) Status Clear Register */ + #define REG_I2SC1_SSR (*(__O uint32_t*)0x40090010U) /**< \brief (I2SC1) Status Set Register */ + #define REG_I2SC1_IER (*(__O uint32_t*)0x40090014U) /**< \brief (I2SC1) Interrupt Enable Register */ + #define REG_I2SC1_IDR (*(__O uint32_t*)0x40090018U) /**< \brief (I2SC1) Interrupt Disable Register */ + #define REG_I2SC1_IMR (*(__I uint32_t*)0x4009001CU) /**< \brief (I2SC1) Interrupt Mask Register */ + #define REG_I2SC1_RHR (*(__I uint32_t*)0x40090020U) /**< \brief (I2SC1) Receiver Holding Register */ + #define REG_I2SC1_THR (*(__O uint32_t*)0x40090024U) /**< \brief (I2SC1) Transmitter Holding Register */ + #define REG_I2SC1_VERSION (*(__I uint32_t*)0x40090028U) /**< \brief (I2SC1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_I2SC1_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/icm.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/icm.h new file mode 100644 index 00000000..7225400a --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/icm.h @@ -0,0 +1,73 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ICM_INSTANCE_ +#define _SAME70_ICM_INSTANCE_ + +/* ========== Register definition for ICM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ICM_CFG (0x40048000U) /**< \brief (ICM) Configuration Register */ + #define REG_ICM_CTRL (0x40048004U) /**< \brief (ICM) Control Register */ + #define REG_ICM_SR (0x40048008U) /**< \brief (ICM) Status Register */ + #define REG_ICM_IER (0x40048010U) /**< \brief (ICM) Interrupt Enable Register */ + #define REG_ICM_IDR (0x40048014U) /**< \brief (ICM) Interrupt Disable Register */ + #define REG_ICM_IMR (0x40048018U) /**< \brief (ICM) Interrupt Mask Register */ + #define REG_ICM_ISR (0x4004801CU) /**< \brief (ICM) Interrupt Status Register */ + #define REG_ICM_UASR (0x40048020U) /**< \brief (ICM) Undefined Access Status Register */ + #define REG_ICM_DSCR (0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */ + #define REG_ICM_HASH (0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */ + #define REG_ICM_UIHVAL (0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */ + #define REG_ICM_ADDRSIZE (0x400480ECU) /**< \brief (ICM) Address Size Register */ + #define REG_ICM_IPNAME (0x400480F0U) /**< \brief (ICM) IP Name 1 Register */ + #define REG_ICM_FEATURES (0x400480F8U) /**< \brief (ICM) Feature Register */ + #define REG_ICM_VERSION (0x400480FCU) /**< \brief (ICM) Version Register */ +#else + #define REG_ICM_CFG (*(__IO uint32_t*)0x40048000U) /**< \brief (ICM) Configuration Register */ + #define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< \brief (ICM) Control Register */ + #define REG_ICM_SR (*(__I uint32_t*)0x40048008U) /**< \brief (ICM) Status Register */ + #define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< \brief (ICM) Interrupt Enable Register */ + #define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< \brief (ICM) Interrupt Disable Register */ + #define REG_ICM_IMR (*(__I uint32_t*)0x40048018U) /**< \brief (ICM) Interrupt Mask Register */ + #define REG_ICM_ISR (*(__I uint32_t*)0x4004801CU) /**< \brief (ICM) Interrupt Status Register */ + #define REG_ICM_UASR (*(__I uint32_t*)0x40048020U) /**< \brief (ICM) Undefined Access Status Register */ + #define REG_ICM_DSCR (*(__IO uint32_t*)0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */ + #define REG_ICM_HASH (*(__IO uint32_t*)0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */ + #define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */ + #define REG_ICM_ADDRSIZE (*(__I uint32_t*)0x400480ECU) /**< \brief (ICM) Address Size Register */ + #define REG_ICM_IPNAME (*(__I uint32_t*)0x400480F0U) /**< \brief (ICM) IP Name 1 Register */ + #define REG_ICM_FEATURES (*(__I uint32_t*)0x400480F8U) /**< \brief (ICM) Feature Register */ + #define REG_ICM_VERSION (*(__I uint32_t*)0x400480FCU) /**< \brief (ICM) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_ICM_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/isi.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/isi.h new file mode 100644 index 00000000..e35ba5d0 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/isi.h @@ -0,0 +1,95 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ISI_INSTANCE_ +#define _SAME70_ISI_INSTANCE_ + +/* ========== Register definition for ISI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ISI_CFG1 (0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */ + #define REG_ISI_CFG2 (0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */ + #define REG_ISI_PSIZE (0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */ + #define REG_ISI_PDECF (0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ + #define REG_ISI_Y2R_SET0 (0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + #define REG_ISI_Y2R_SET1 (0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + #define REG_ISI_R2Y_SET0 (0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + #define REG_ISI_R2Y_SET1 (0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + #define REG_ISI_R2Y_SET2 (0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + #define REG_ISI_CR (0x4004C024U) /**< \brief (ISI) ISI Control Register */ + #define REG_ISI_SR (0x4004C028U) /**< \brief (ISI) ISI Status Register */ + #define REG_ISI_IER (0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */ + #define REG_ISI_IDR (0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */ + #define REG_ISI_IMR (0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */ + #define REG_ISI_DMA_CHER (0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */ + #define REG_ISI_DMA_CHDR (0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */ + #define REG_ISI_DMA_CHSR (0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */ + #define REG_ISI_DMA_P_ADDR (0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */ + #define REG_ISI_DMA_P_CTRL (0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */ + #define REG_ISI_DMA_P_DSCR (0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ + #define REG_ISI_DMA_C_ADDR (0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */ + #define REG_ISI_DMA_C_CTRL (0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */ + #define REG_ISI_DMA_C_DSCR (0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ + #define REG_ISI_WPMR (0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */ + #define REG_ISI_WPSR (0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */ + #define REG_ISI_VERSION (0x4004C0FCU) /**< \brief (ISI) Version Register */ +#else + #define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */ + #define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */ + #define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */ + #define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ + #define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + #define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + #define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + #define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + #define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + #define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< \brief (ISI) ISI Control Register */ + #define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< \brief (ISI) ISI Status Register */ + #define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */ + #define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */ + #define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */ + #define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */ + #define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */ + #define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */ + #define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */ + #define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */ + #define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ + #define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */ + #define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */ + #define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ + #define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */ + #define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */ + #define REG_ISI_VERSION (*(__I uint32_t*)0x4004C0FCU) /**< \brief (ISI) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_ISI_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/matrix.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/matrix.h new file mode 100644 index 00000000..fdae66e1 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/matrix.h @@ -0,0 +1,123 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_MATRIX_INSTANCE_ +#define _SAME70_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MATRIX_MCFG0 (0x40088000U) /**< \brief (MATRIX) Master Configuration Register 0 */ + #define REG_MATRIX_MCFG1 (0x40088004U) /**< \brief (MATRIX) Master Configuration Register 1 */ + #define REG_MATRIX_MCFG2 (0x40088008U) /**< \brief (MATRIX) Master Configuration Register 2 */ + #define REG_MATRIX_MCFG3 (0x4008800CU) /**< \brief (MATRIX) Master Configuration Register 3 */ + #define REG_MATRIX_MCFG4 (0x40088010U) /**< \brief (MATRIX) Master Configuration Register 4 */ + #define REG_MATRIX_MCFG5 (0x40088014U) /**< \brief (MATRIX) Master Configuration Register 5 */ + #define REG_MATRIX_MCFG6 (0x40088018U) /**< \brief (MATRIX) Master Configuration Register 6 */ + #define REG_MATRIX_MCFG8 (0x40088020U) /**< \brief (MATRIX) Master Configuration Register 8 */ + #define REG_MATRIX_MCFG9 (0x40088024U) /**< \brief (MATRIX) Master Configuration Register 9 */ + #define REG_MATRIX_MCFG10 (0x40088028U) /**< \brief (MATRIX) Master Configuration Register 10 */ + #define REG_MATRIX_MCFG11 (0x4008802CU) /**< \brief (MATRIX) Master Configuration Register 11 */ + #define REG_MATRIX_MCFG12 (0x40088030U) /**< \brief (MATRIX) Master Configuration Register 12 */ + #define REG_MATRIX_SCFG (0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRBS0 (0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ + #define REG_MATRIX_PRAS1 (0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRBS1 (0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ + #define REG_MATRIX_PRAS2 (0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRBS2 (0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ + #define REG_MATRIX_PRAS3 (0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRBS3 (0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ + #define REG_MATRIX_PRAS4 (0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_MATRIX_PRBS4 (0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ + #define REG_MATRIX_PRAS5 (0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ + #define REG_MATRIX_PRBS5 (0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ + #define REG_MATRIX_PRAS6 (0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ + #define REG_MATRIX_PRBS6 (0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ + #define REG_MATRIX_PRAS7 (0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ + #define REG_MATRIX_PRBS7 (0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ + #define REG_MATRIX_PRAS8 (0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ + #define REG_MATRIX_PRBS8 (0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ + #define REG_MATRIX_MRCR (0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */ + #define REG_CCFG_CAN0 (0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */ + #define REG_CCFG_SYSIO (0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */ + #define REG_CCFG_PCCR (0x40088118U) /**< \brief (MATRIX) Peripheral Clock Configuration Register */ + #define REG_CCFG_DYNCKG (0x4008811CU) /**< \brief (MATRIX) Dynamic Clock Gating Register */ + #define REG_CCFG_SMCNFCS (0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ + #define REG_MATRIX_WPMR (0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */ + #define REG_MATRIX_WPSR (0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */ + #define REG_MATRIX_VERSION (0x400881FCU) /**< \brief (MATRIX) Version Register */ +#else + #define REG_MATRIX_MCFG0 (*(__IO uint32_t*)0x40088000U) /**< \brief (MATRIX) Master Configuration Register 0 */ + #define REG_MATRIX_MCFG1 (*(__IO uint32_t*)0x40088004U) /**< \brief (MATRIX) Master Configuration Register 1 */ + #define REG_MATRIX_MCFG2 (*(__IO uint32_t*)0x40088008U) /**< \brief (MATRIX) Master Configuration Register 2 */ + #define REG_MATRIX_MCFG3 (*(__IO uint32_t*)0x4008800CU) /**< \brief (MATRIX) Master Configuration Register 3 */ + #define REG_MATRIX_MCFG4 (*(__IO uint32_t*)0x40088010U) /**< \brief (MATRIX) Master Configuration Register 4 */ + #define REG_MATRIX_MCFG5 (*(__IO uint32_t*)0x40088014U) /**< \brief (MATRIX) Master Configuration Register 5 */ + #define REG_MATRIX_MCFG6 (*(__IO uint32_t*)0x40088018U) /**< \brief (MATRIX) Master Configuration Register 6 */ + #define REG_MATRIX_MCFG8 (*(__IO uint32_t*)0x40088020U) /**< \brief (MATRIX) Master Configuration Register 8 */ + #define REG_MATRIX_MCFG9 (*(__IO uint32_t*)0x40088024U) /**< \brief (MATRIX) Master Configuration Register 9 */ + #define REG_MATRIX_MCFG10 (*(__IO uint32_t*)0x40088028U) /**< \brief (MATRIX) Master Configuration Register 10 */ + #define REG_MATRIX_MCFG11 (*(__IO uint32_t*)0x4008802CU) /**< \brief (MATRIX) Master Configuration Register 11 */ + #define REG_MATRIX_MCFG12 (*(__IO uint32_t*)0x40088030U) /**< \brief (MATRIX) Master Configuration Register 12 */ + #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ + #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ + #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ + #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ + #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ + #define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ + #define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ + #define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ + #define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ + #define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ + #define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ + #define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ + #define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ + #define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */ + #define REG_CCFG_CAN0 (*(__IO uint32_t*)0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */ + #define REG_CCFG_SYSIO (*(__IO uint32_t*)0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */ + #define REG_CCFG_PCCR (*(__IO uint32_t*)0x40088118U) /**< \brief (MATRIX) Peripheral Clock Configuration Register */ + #define REG_CCFG_DYNCKG (*(__IO uint32_t*)0x4008811CU) /**< \brief (MATRIX) Dynamic Clock Gating Register */ + #define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ + #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */ + #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */ + #define REG_MATRIX_VERSION (*(__I uint32_t*)0x400881FCU) /**< \brief (MATRIX) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_MATRIX_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/mcan0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/mcan0.h new file mode 100644 index 00000000..c8819b34 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/mcan0.h @@ -0,0 +1,141 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_MCAN0_INSTANCE_ +#define _SAME70_MCAN0_INSTANCE_ + +/* ========== Register definition for MCAN0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MCAN0_CREL (0x40030000U) /**< \brief (MCAN0) Core Release Register */ + #define REG_MCAN0_ENDN (0x40030004U) /**< \brief (MCAN0) Endian Register */ + #define REG_MCAN0_CUST (0x40030008U) /**< \brief (MCAN0) Customer Register */ + #define REG_MCAN0_FBTP (0x4003000CU) /**< \brief (MCAN0) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN0_DBTP (0x4003000CU) /**< \brief (MCAN0) Data Bit Timing and Prescaler Register */ + #define REG_MCAN0_TEST (0x40030010U) /**< \brief (MCAN0) Test Register */ + #define REG_MCAN0_RWD (0x40030014U) /**< \brief (MCAN0) RAM Watchdog Register */ + #define REG_MCAN0_CCCR (0x40030018U) /**< \brief (MCAN0) CC Control Register */ + #define REG_MCAN0_BTP (0x4003001CU) /**< \brief (MCAN0) Bit Timing and Prescaler Register */ + #define REG_MCAN0_NBTP (0x4003001CU) /**< \brief (MCAN0) Nominal Bit Timing and Prescaler Register */ + #define REG_MCAN0_TSCC (0x40030020U) /**< \brief (MCAN0) Timestamp Counter Configuration Register */ + #define REG_MCAN0_TSCV (0x40030024U) /**< \brief (MCAN0) Timestamp Counter Value Register */ + #define REG_MCAN0_TOCC (0x40030028U) /**< \brief (MCAN0) Timeout Counter Configuration Register */ + #define REG_MCAN0_TOCV (0x4003002CU) /**< \brief (MCAN0) Timeout Counter Value Register */ + #define REG_MCAN0_ECR (0x40030040U) /**< \brief (MCAN0) Error Counter Register */ + #define REG_MCAN0_PSR (0x40030044U) /**< \brief (MCAN0) Protocol Status Register */ + #define REG_MCAN0_TDCR (0x40030048U) /**< \brief (MCAN0) Transmit Delay Compensation Register */ + #define REG_MCAN0_IR (0x40030050U) /**< \brief (MCAN0) Interrupt Register */ + #define REG_MCAN0_IE (0x40030054U) /**< \brief (MCAN0) Interrupt Enable Register */ + #define REG_MCAN0_ILS (0x40030058U) /**< \brief (MCAN0) Interrupt Line Select Register */ + #define REG_MCAN0_ILE (0x4003005CU) /**< \brief (MCAN0) Interrupt Line Enable Register */ + #define REG_MCAN0_GFC (0x40030080U) /**< \brief (MCAN0) Global Filter Configuration Register */ + #define REG_MCAN0_SIDFC (0x40030084U) /**< \brief (MCAN0) Standard ID Filter Configuration Register */ + #define REG_MCAN0_XIDFC (0x40030088U) /**< \brief (MCAN0) Extended ID Filter Configuration Register */ + #define REG_MCAN0_XIDAM (0x40030090U) /**< \brief (MCAN0) Extended ID AND Mask Register */ + #define REG_MCAN0_HPMS (0x40030094U) /**< \brief (MCAN0) High Priority Message Status Register */ + #define REG_MCAN0_NDAT1 (0x40030098U) /**< \brief (MCAN0) New Data 1 Register */ + #define REG_MCAN0_NDAT2 (0x4003009CU) /**< \brief (MCAN0) New Data 2 Register */ + #define REG_MCAN0_RXF0C (0x400300A0U) /**< \brief (MCAN0) Receive FIFO 0 Configuration Register */ + #define REG_MCAN0_RXF0S (0x400300A4U) /**< \brief (MCAN0) Receive FIFO 0 Status Register */ + #define REG_MCAN0_RXF0A (0x400300A8U) /**< \brief (MCAN0) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN0_RXBC (0x400300ACU) /**< \brief (MCAN0) Receive Rx Buffer Configuration Register */ + #define REG_MCAN0_RXF1C (0x400300B0U) /**< \brief (MCAN0) Receive FIFO 1 Configuration Register */ + #define REG_MCAN0_RXF1S (0x400300B4U) /**< \brief (MCAN0) Receive FIFO 1 Status Register */ + #define REG_MCAN0_RXF1A (0x400300B8U) /**< \brief (MCAN0) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN0_RXESC (0x400300BCU) /**< \brief (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN0_TXBC (0x400300C0U) /**< \brief (MCAN0) Transmit Buffer Configuration Register */ + #define REG_MCAN0_TXFQS (0x400300C4U) /**< \brief (MCAN0) Transmit FIFO/Queue Status Register */ + #define REG_MCAN0_TXESC (0x400300C8U) /**< \brief (MCAN0) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN0_TXBRP (0x400300CCU) /**< \brief (MCAN0) Transmit Buffer Request Pending Register */ + #define REG_MCAN0_TXBAR (0x400300D0U) /**< \brief (MCAN0) Transmit Buffer Add Request Register */ + #define REG_MCAN0_TXBCR (0x400300D4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN0_TXBTO (0x400300D8U) /**< \brief (MCAN0) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN0_TXBCF (0x400300DCU) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN0_TXBTIE (0x400300E0U) /**< \brief (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN0_TXBCIE (0x400300E4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN0_TXEFC (0x400300F0U) /**< \brief (MCAN0) Transmit Event FIFO Configuration Register */ + #define REG_MCAN0_TXEFS (0x400300F4U) /**< \brief (MCAN0) Transmit Event FIFO Status Register */ + #define REG_MCAN0_TXEFA (0x400300F8U) /**< \brief (MCAN0) Transmit Event FIFO Acknowledge Register */ +#else + #define REG_MCAN0_CREL (*(__I uint32_t*)0x40030000U) /**< \brief (MCAN0) Core Release Register */ + #define REG_MCAN0_ENDN (*(__I uint32_t*)0x40030004U) /**< \brief (MCAN0) Endian Register */ + #define REG_MCAN0_CUST (*(__IO uint32_t*)0x40030008U) /**< \brief (MCAN0) Customer Register */ + #define REG_MCAN0_FBTP (*(__IO uint32_t*)0x4003000CU) /**< \brief (MCAN0) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN0_DBTP (*(__IO uint32_t*)0x4003000CU) /**< \brief (MCAN0) Data Bit Timing and Prescaler Register */ + #define REG_MCAN0_TEST (*(__IO uint32_t*)0x40030010U) /**< \brief (MCAN0) Test Register */ + #define REG_MCAN0_RWD (*(__IO uint32_t*)0x40030014U) /**< \brief (MCAN0) RAM Watchdog Register */ + #define REG_MCAN0_CCCR (*(__IO uint32_t*)0x40030018U) /**< \brief (MCAN0) CC Control Register */ + #define REG_MCAN0_BTP (*(__IO uint32_t*)0x4003001CU) /**< \brief (MCAN0) Bit Timing and Prescaler Register */ + #define REG_MCAN0_NBTP (*(__IO uint32_t*)0x4003001CU) /**< \brief (MCAN0) Nominal Bit Timing and Prescaler Register */ + #define REG_MCAN0_TSCC (*(__IO uint32_t*)0x40030020U) /**< \brief (MCAN0) Timestamp Counter Configuration Register */ + #define REG_MCAN0_TSCV (*(__IO uint32_t*)0x40030024U) /**< \brief (MCAN0) Timestamp Counter Value Register */ + #define REG_MCAN0_TOCC (*(__IO uint32_t*)0x40030028U) /**< \brief (MCAN0) Timeout Counter Configuration Register */ + #define REG_MCAN0_TOCV (*(__IO uint32_t*)0x4003002CU) /**< \brief (MCAN0) Timeout Counter Value Register */ + #define REG_MCAN0_ECR (*(__I uint32_t*)0x40030040U) /**< \brief (MCAN0) Error Counter Register */ + #define REG_MCAN0_PSR (*(__I uint32_t*)0x40030044U) /**< \brief (MCAN0) Protocol Status Register */ + #define REG_MCAN0_TDCR (*(__IO uint32_t*)0x40030048U) /**< \brief (MCAN0) Transmit Delay Compensation Register */ + #define REG_MCAN0_IR (*(__IO uint32_t*)0x40030050U) /**< \brief (MCAN0) Interrupt Register */ + #define REG_MCAN0_IE (*(__IO uint32_t*)0x40030054U) /**< \brief (MCAN0) Interrupt Enable Register */ + #define REG_MCAN0_ILS (*(__IO uint32_t*)0x40030058U) /**< \brief (MCAN0) Interrupt Line Select Register */ + #define REG_MCAN0_ILE (*(__IO uint32_t*)0x4003005CU) /**< \brief (MCAN0) Interrupt Line Enable Register */ + #define REG_MCAN0_GFC (*(__IO uint32_t*)0x40030080U) /**< \brief (MCAN0) Global Filter Configuration Register */ + #define REG_MCAN0_SIDFC (*(__IO uint32_t*)0x40030084U) /**< \brief (MCAN0) Standard ID Filter Configuration Register */ + #define REG_MCAN0_XIDFC (*(__IO uint32_t*)0x40030088U) /**< \brief (MCAN0) Extended ID Filter Configuration Register */ + #define REG_MCAN0_XIDAM (*(__IO uint32_t*)0x40030090U) /**< \brief (MCAN0) Extended ID AND Mask Register */ + #define REG_MCAN0_HPMS (*(__I uint32_t*)0x40030094U) /**< \brief (MCAN0) High Priority Message Status Register */ + #define REG_MCAN0_NDAT1 (*(__IO uint32_t*)0x40030098U) /**< \brief (MCAN0) New Data 1 Register */ + #define REG_MCAN0_NDAT2 (*(__IO uint32_t*)0x4003009CU) /**< \brief (MCAN0) New Data 2 Register */ + #define REG_MCAN0_RXF0C (*(__IO uint32_t*)0x400300A0U) /**< \brief (MCAN0) Receive FIFO 0 Configuration Register */ + #define REG_MCAN0_RXF0S (*(__I uint32_t*)0x400300A4U) /**< \brief (MCAN0) Receive FIFO 0 Status Register */ + #define REG_MCAN0_RXF0A (*(__IO uint32_t*)0x400300A8U) /**< \brief (MCAN0) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN0_RXBC (*(__IO uint32_t*)0x400300ACU) /**< \brief (MCAN0) Receive Rx Buffer Configuration Register */ + #define REG_MCAN0_RXF1C (*(__IO uint32_t*)0x400300B0U) /**< \brief (MCAN0) Receive FIFO 1 Configuration Register */ + #define REG_MCAN0_RXF1S (*(__I uint32_t*)0x400300B4U) /**< \brief (MCAN0) Receive FIFO 1 Status Register */ + #define REG_MCAN0_RXF1A (*(__IO uint32_t*)0x400300B8U) /**< \brief (MCAN0) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN0_RXESC (*(__IO uint32_t*)0x400300BCU) /**< \brief (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN0_TXBC (*(__IO uint32_t*)0x400300C0U) /**< \brief (MCAN0) Transmit Buffer Configuration Register */ + #define REG_MCAN0_TXFQS (*(__I uint32_t*)0x400300C4U) /**< \brief (MCAN0) Transmit FIFO/Queue Status Register */ + #define REG_MCAN0_TXESC (*(__IO uint32_t*)0x400300C8U) /**< \brief (MCAN0) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN0_TXBRP (*(__I uint32_t*)0x400300CCU) /**< \brief (MCAN0) Transmit Buffer Request Pending Register */ + #define REG_MCAN0_TXBAR (*(__IO uint32_t*)0x400300D0U) /**< \brief (MCAN0) Transmit Buffer Add Request Register */ + #define REG_MCAN0_TXBCR (*(__IO uint32_t*)0x400300D4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN0_TXBTO (*(__I uint32_t*)0x400300D8U) /**< \brief (MCAN0) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN0_TXBCF (*(__I uint32_t*)0x400300DCU) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN0_TXBTIE (*(__IO uint32_t*)0x400300E0U) /**< \brief (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN0_TXBCIE (*(__IO uint32_t*)0x400300E4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN0_TXEFC (*(__IO uint32_t*)0x400300F0U) /**< \brief (MCAN0) Transmit Event FIFO Configuration Register */ + #define REG_MCAN0_TXEFS (*(__I uint32_t*)0x400300F4U) /**< \brief (MCAN0) Transmit Event FIFO Status Register */ + #define REG_MCAN0_TXEFA (*(__IO uint32_t*)0x400300F8U) /**< \brief (MCAN0) Transmit Event FIFO Acknowledge Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_MCAN0_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/mcan1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/mcan1.h new file mode 100644 index 00000000..2c81491a --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/mcan1.h @@ -0,0 +1,141 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_MCAN1_INSTANCE_ +#define _SAME70_MCAN1_INSTANCE_ + +/* ========== Register definition for MCAN1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MCAN1_CREL (0x40034000U) /**< \brief (MCAN1) Core Release Register */ + #define REG_MCAN1_ENDN (0x40034004U) /**< \brief (MCAN1) Endian Register */ + #define REG_MCAN1_CUST (0x40034008U) /**< \brief (MCAN1) Customer Register */ + #define REG_MCAN1_FBTP (0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN1_DBTP (0x4003400CU) /**< \brief (MCAN1) Data Bit Timing and Prescaler Register */ + #define REG_MCAN1_TEST (0x40034010U) /**< \brief (MCAN1) Test Register */ + #define REG_MCAN1_RWD (0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ + #define REG_MCAN1_CCCR (0x40034018U) /**< \brief (MCAN1) CC Control Register */ + #define REG_MCAN1_BTP (0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ + #define REG_MCAN1_NBTP (0x4003401CU) /**< \brief (MCAN1) Nominal Bit Timing and Prescaler Register */ + #define REG_MCAN1_TSCC (0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ + #define REG_MCAN1_TSCV (0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ + #define REG_MCAN1_TOCC (0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ + #define REG_MCAN1_TOCV (0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ + #define REG_MCAN1_ECR (0x40034040U) /**< \brief (MCAN1) Error Counter Register */ + #define REG_MCAN1_PSR (0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ + #define REG_MCAN1_TDCR (0x40034048U) /**< \brief (MCAN1) Transmit Delay Compensation Register */ + #define REG_MCAN1_IR (0x40034050U) /**< \brief (MCAN1) Interrupt Register */ + #define REG_MCAN1_IE (0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ + #define REG_MCAN1_ILS (0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ + #define REG_MCAN1_ILE (0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ + #define REG_MCAN1_GFC (0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ + #define REG_MCAN1_SIDFC (0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ + #define REG_MCAN1_XIDFC (0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ + #define REG_MCAN1_XIDAM (0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ + #define REG_MCAN1_HPMS (0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ + #define REG_MCAN1_NDAT1 (0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ + #define REG_MCAN1_NDAT2 (0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ + #define REG_MCAN1_RXF0C (0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ + #define REG_MCAN1_RXF0S (0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ + #define REG_MCAN1_RXF0A (0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN1_RXBC (0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ + #define REG_MCAN1_RXF1C (0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ + #define REG_MCAN1_RXF1S (0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ + #define REG_MCAN1_RXF1A (0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN1_RXESC (0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN1_TXBC (0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ + #define REG_MCAN1_TXFQS (0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ + #define REG_MCAN1_TXESC (0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN1_TXBRP (0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ + #define REG_MCAN1_TXBAR (0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ + #define REG_MCAN1_TXBCR (0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN1_TXBTO (0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN1_TXBCF (0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN1_TXBTIE (0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN1_TXBCIE (0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN1_TXEFC (0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ + #define REG_MCAN1_TXEFS (0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ + #define REG_MCAN1_TXEFA (0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ +#else + #define REG_MCAN1_CREL (*(__I uint32_t*)0x40034000U) /**< \brief (MCAN1) Core Release Register */ + #define REG_MCAN1_ENDN (*(__I uint32_t*)0x40034004U) /**< \brief (MCAN1) Endian Register */ + #define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U) /**< \brief (MCAN1) Customer Register */ + #define REG_MCAN1_FBTP (*(__IO uint32_t*)0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN1_DBTP (*(__IO uint32_t*)0x4003400CU) /**< \brief (MCAN1) Data Bit Timing and Prescaler Register */ + #define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U) /**< \brief (MCAN1) Test Register */ + #define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ + #define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U) /**< \brief (MCAN1) CC Control Register */ + #define REG_MCAN1_BTP (*(__IO uint32_t*)0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ + #define REG_MCAN1_NBTP (*(__IO uint32_t*)0x4003401CU) /**< \brief (MCAN1) Nominal Bit Timing and Prescaler Register */ + #define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ + #define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ + #define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ + #define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ + #define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U) /**< \brief (MCAN1) Error Counter Register */ + #define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ + #define REG_MCAN1_TDCR (*(__IO uint32_t*)0x40034048U) /**< \brief (MCAN1) Transmit Delay Compensation Register */ + #define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U) /**< \brief (MCAN1) Interrupt Register */ + #define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ + #define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ + #define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ + #define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ + #define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ + #define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ + #define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ + #define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ + #define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ + #define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ + #define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ + #define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ + #define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ + #define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ + #define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ + #define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ + #define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ + #define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ + #define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ + #define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ + #define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ + #define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_MCAN1_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioa.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioa.h new file mode 100644 index 00000000..8aac50ff --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioa.h @@ -0,0 +1,171 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIOA_INSTANCE_ +#define _SAME70_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ + #define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ + #define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ + #define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */ + #define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ + #define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ + #define REG_PIOA_VERSION (0x400E0EFCU) /**< \brief (PIOA) Version Register */ + #define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_DRIVER (0x400E0F18U) /**< \brief (PIOA) PIO I/O Drive Register */ + #define REG_PIOA_KER (0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */ + #define REG_PIOA_KRCR (0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */ + #define REG_PIOA_KDR (0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */ + #define REG_PIOA_KIER (0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */ + #define REG_PIOA_KIDR (0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */ + #define REG_PIOA_KIMR (0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */ + #define REG_PIOA_KSR (0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */ + #define REG_PIOA_KKPR (0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */ + #define REG_PIOA_KKRR (0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */ + #define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ + #define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ + #define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ + #define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ + #define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ + #define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ + #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ + #define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ + #define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */ + #define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ + #define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ + #define REG_PIOA_VERSION (*(__I uint32_t*)0x400E0EFCU) /**< \brief (PIOA) Version Register */ + #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_DRIVER (*(__IO uint32_t*)0x400E0F18U) /**< \brief (PIOA) PIO I/O Drive Register */ + #define REG_PIOA_KER (*(__IO uint32_t*)0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */ + #define REG_PIOA_KRCR (*(__IO uint32_t*)0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */ + #define REG_PIOA_KDR (*(__IO uint32_t*)0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */ + #define REG_PIOA_KIER (*(__O uint32_t*)0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */ + #define REG_PIOA_KIDR (*(__O uint32_t*)0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */ + #define REG_PIOA_KIMR (*(__I uint32_t*)0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */ + #define REG_PIOA_KSR (*(__I uint32_t*)0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */ + #define REG_PIOA_KKPR (*(__I uint32_t*)0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */ + #define REG_PIOA_KKRR (*(__I uint32_t*)0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */ + #define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ + #define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ + #define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ + #define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ + #define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ + #define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PIOA_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piob.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piob.h new file mode 100644 index 00000000..20f6e283 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piob.h @@ -0,0 +1,171 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIOB_INSTANCE_ +#define _SAME70_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ + #define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ + #define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ + #define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */ + #define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ + #define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ + #define REG_PIOB_VERSION (0x400E10FCU) /**< \brief (PIOB) Version Register */ + #define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ + #define REG_PIOB_DRIVER (0x400E1118U) /**< \brief (PIOB) PIO I/O Drive Register */ + #define REG_PIOB_KER (0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */ + #define REG_PIOB_KRCR (0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */ + #define REG_PIOB_KDR (0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */ + #define REG_PIOB_KIER (0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */ + #define REG_PIOB_KIDR (0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */ + #define REG_PIOB_KIMR (0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */ + #define REG_PIOB_KSR (0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */ + #define REG_PIOB_KKPR (0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */ + #define REG_PIOB_KKRR (0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */ + #define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ + #define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ + #define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ + #define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ + #define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ + #define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ + #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ + #define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ + #define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) /**< \brief (PIOB) Lock Status */ + #define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ + #define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ + #define REG_PIOB_VERSION (*(__I uint32_t*)0x400E10FCU) /**< \brief (PIOB) Version Register */ + #define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ + #define REG_PIOB_DRIVER (*(__IO uint32_t*)0x400E1118U) /**< \brief (PIOB) PIO I/O Drive Register */ + #define REG_PIOB_KER (*(__IO uint32_t*)0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */ + #define REG_PIOB_KRCR (*(__IO uint32_t*)0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */ + #define REG_PIOB_KDR (*(__IO uint32_t*)0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */ + #define REG_PIOB_KIER (*(__O uint32_t*)0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */ + #define REG_PIOB_KIDR (*(__O uint32_t*)0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */ + #define REG_PIOB_KIMR (*(__I uint32_t*)0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */ + #define REG_PIOB_KSR (*(__I uint32_t*)0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */ + #define REG_PIOB_KKPR (*(__I uint32_t*)0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */ + #define REG_PIOB_KKRR (*(__I uint32_t*)0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */ + #define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ + #define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ + #define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ + #define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ + #define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ + #define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PIOB_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioc.h new file mode 100644 index 00000000..802bd831 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioc.h @@ -0,0 +1,171 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIOC_INSTANCE_ +#define _SAME70_PIOC_INSTANCE_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */ + #define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */ + #define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */ + #define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */ + #define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */ + #define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */ + #define REG_PIOC_VERSION (0x400E12FCU) /**< \brief (PIOC) Version Register */ + #define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ + #define REG_PIOC_DRIVER (0x400E1318U) /**< \brief (PIOC) PIO I/O Drive Register */ + #define REG_PIOC_KER (0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */ + #define REG_PIOC_KRCR (0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */ + #define REG_PIOC_KDR (0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */ + #define REG_PIOC_KIER (0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */ + #define REG_PIOC_KIDR (0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */ + #define REG_PIOC_KIMR (0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */ + #define REG_PIOC_KSR (0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */ + #define REG_PIOC_KKPR (0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */ + #define REG_PIOC_KKRR (0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */ + #define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ + #define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ + #define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ + #define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ + #define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ + #define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */ + #define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */ + #define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */ + #define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_LOCKSR (*(__I uint32_t*)0x400E12E0U) /**< \brief (PIOC) Lock Status */ + #define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */ + #define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */ + #define REG_PIOC_VERSION (*(__I uint32_t*)0x400E12FCU) /**< \brief (PIOC) Version Register */ + #define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ + #define REG_PIOC_DRIVER (*(__IO uint32_t*)0x400E1318U) /**< \brief (PIOC) PIO I/O Drive Register */ + #define REG_PIOC_KER (*(__IO uint32_t*)0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */ + #define REG_PIOC_KRCR (*(__IO uint32_t*)0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */ + #define REG_PIOC_KDR (*(__IO uint32_t*)0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */ + #define REG_PIOC_KIER (*(__O uint32_t*)0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */ + #define REG_PIOC_KIDR (*(__O uint32_t*)0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */ + #define REG_PIOC_KIMR (*(__I uint32_t*)0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */ + #define REG_PIOC_KSR (*(__I uint32_t*)0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */ + #define REG_PIOC_KKPR (*(__I uint32_t*)0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */ + #define REG_PIOC_KKRR (*(__I uint32_t*)0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */ + #define REG_PIOC_PCMR (*(__IO uint32_t*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ + #define REG_PIOC_PCIER (*(__O uint32_t*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ + #define REG_PIOC_PCIDR (*(__O uint32_t*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ + #define REG_PIOC_PCIMR (*(__I uint32_t*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ + #define REG_PIOC_PCISR (*(__I uint32_t*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ + #define REG_PIOC_PCRHR (*(__I uint32_t*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PIOC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piod.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piod.h new file mode 100644 index 00000000..850bcf04 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piod.h @@ -0,0 +1,171 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIOD_INSTANCE_ +#define _SAME70_PIOD_INSTANCE_ + +/* ========== Register definition for PIOD peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ + #define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ + #define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */ + #define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */ + #define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */ + #define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */ + #define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ + #define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ + #define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ + #define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ + #define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ + #define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ + #define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ + #define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ + #define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ + #define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ + #define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ + #define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ + #define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ + #define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ + #define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ + #define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ + #define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ + #define REG_PIOD_ABCDSR (0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */ + #define REG_PIOD_IFSCDR (0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ + #define REG_PIOD_IFSCER (0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ + #define REG_PIOD_IFSCSR (0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ + #define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ + #define REG_PIOD_PPDDR (0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */ + #define REG_PIOD_PPDER (0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */ + #define REG_PIOD_PPDSR (0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */ + #define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ + #define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ + #define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ + #define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ + #define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */ + #define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ + #define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ + #define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */ + #define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ + #define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */ + #define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */ + #define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ + #define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */ + #define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */ + #define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */ + #define REG_PIOD_VERSION (0x400E14FCU) /**< \brief (PIOD) Version Register */ + #define REG_PIOD_SCHMITT (0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */ + #define REG_PIOD_DRIVER (0x400E1518U) /**< \brief (PIOD) PIO I/O Drive Register */ + #define REG_PIOD_KER (0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */ + #define REG_PIOD_KRCR (0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */ + #define REG_PIOD_KDR (0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */ + #define REG_PIOD_KIER (0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */ + #define REG_PIOD_KIDR (0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */ + #define REG_PIOD_KIMR (0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */ + #define REG_PIOD_KSR (0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */ + #define REG_PIOD_KKPR (0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */ + #define REG_PIOD_KKRR (0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */ + #define REG_PIOD_PCMR (0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */ + #define REG_PIOD_PCIER (0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */ + #define REG_PIOD_PCIDR (0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */ + #define REG_PIOD_PCIMR (0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */ + #define REG_PIOD_PCISR (0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */ + #define REG_PIOD_PCRHR (0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOD_PER (*(__O uint32_t*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ + #define REG_PIOD_PDR (*(__O uint32_t*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ + #define REG_PIOD_PSR (*(__I uint32_t*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */ + #define REG_PIOD_OER (*(__O uint32_t*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */ + #define REG_PIOD_ODR (*(__O uint32_t*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */ + #define REG_PIOD_OSR (*(__I uint32_t*)0x400E1418U) /**< \brief (PIOD) Output Status Register */ + #define REG_PIOD_IFER (*(__O uint32_t*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ + #define REG_PIOD_IFDR (*(__O uint32_t*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ + #define REG_PIOD_IFSR (*(__I uint32_t*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ + #define REG_PIOD_SODR (*(__O uint32_t*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ + #define REG_PIOD_CODR (*(__O uint32_t*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ + #define REG_PIOD_ODSR (*(__IO uint32_t*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ + #define REG_PIOD_PDSR (*(__I uint32_t*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ + #define REG_PIOD_IER (*(__O uint32_t*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ + #define REG_PIOD_IDR (*(__O uint32_t*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ + #define REG_PIOD_IMR (*(__I uint32_t*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ + #define REG_PIOD_ISR (*(__I uint32_t*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ + #define REG_PIOD_MDER (*(__O uint32_t*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ + #define REG_PIOD_MDDR (*(__O uint32_t*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ + #define REG_PIOD_MDSR (*(__I uint32_t*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ + #define REG_PIOD_PUDR (*(__O uint32_t*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ + #define REG_PIOD_PUER (*(__O uint32_t*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ + #define REG_PIOD_PUSR (*(__I uint32_t*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ + #define REG_PIOD_ABCDSR (*(__IO uint32_t*)0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */ + #define REG_PIOD_IFSCDR (*(__O uint32_t*)0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ + #define REG_PIOD_IFSCER (*(__O uint32_t*)0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ + #define REG_PIOD_IFSCSR (*(__I uint32_t*)0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ + #define REG_PIOD_SCDR (*(__IO uint32_t*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ + #define REG_PIOD_PPDDR (*(__O uint32_t*)0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */ + #define REG_PIOD_PPDER (*(__O uint32_t*)0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */ + #define REG_PIOD_PPDSR (*(__I uint32_t*)0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */ + #define REG_PIOD_OWER (*(__O uint32_t*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ + #define REG_PIOD_OWDR (*(__O uint32_t*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ + #define REG_PIOD_OWSR (*(__I uint32_t*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ + #define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ + #define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */ + #define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ + #define REG_PIOD_ESR (*(__O uint32_t*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ + #define REG_PIOD_LSR (*(__O uint32_t*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */ + #define REG_PIOD_ELSR (*(__I uint32_t*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ + #define REG_PIOD_FELLSR (*(__O uint32_t*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */ + #define REG_PIOD_REHLSR (*(__O uint32_t*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */ + #define REG_PIOD_FRLHSR (*(__I uint32_t*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ + #define REG_PIOD_LOCKSR (*(__I uint32_t*)0x400E14E0U) /**< \brief (PIOD) Lock Status */ + #define REG_PIOD_WPMR (*(__IO uint32_t*)0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */ + #define REG_PIOD_WPSR (*(__I uint32_t*)0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */ + #define REG_PIOD_VERSION (*(__I uint32_t*)0x400E14FCU) /**< \brief (PIOD) Version Register */ + #define REG_PIOD_SCHMITT (*(__IO uint32_t*)0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */ + #define REG_PIOD_DRIVER (*(__IO uint32_t*)0x400E1518U) /**< \brief (PIOD) PIO I/O Drive Register */ + #define REG_PIOD_KER (*(__IO uint32_t*)0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */ + #define REG_PIOD_KRCR (*(__IO uint32_t*)0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */ + #define REG_PIOD_KDR (*(__IO uint32_t*)0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */ + #define REG_PIOD_KIER (*(__O uint32_t*)0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */ + #define REG_PIOD_KIDR (*(__O uint32_t*)0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */ + #define REG_PIOD_KIMR (*(__I uint32_t*)0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */ + #define REG_PIOD_KSR (*(__I uint32_t*)0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */ + #define REG_PIOD_KKPR (*(__I uint32_t*)0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */ + #define REG_PIOD_KKRR (*(__I uint32_t*)0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */ + #define REG_PIOD_PCMR (*(__IO uint32_t*)0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */ + #define REG_PIOD_PCIER (*(__O uint32_t*)0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */ + #define REG_PIOD_PCIDR (*(__O uint32_t*)0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */ + #define REG_PIOD_PCIMR (*(__I uint32_t*)0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */ + #define REG_PIOD_PCISR (*(__I uint32_t*)0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */ + #define REG_PIOD_PCRHR (*(__I uint32_t*)0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PIOD_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioe.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioe.h new file mode 100644 index 00000000..5291dac7 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioe.h @@ -0,0 +1,171 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIOE_INSTANCE_ +#define _SAME70_PIOE_INSTANCE_ + +/* ========== Register definition for PIOE peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ + #define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ + #define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */ + #define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */ + #define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */ + #define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */ + #define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ + #define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ + #define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ + #define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ + #define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ + #define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ + #define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ + #define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ + #define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ + #define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ + #define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ + #define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ + #define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ + #define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ + #define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ + #define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ + #define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ + #define REG_PIOE_ABCDSR (0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */ + #define REG_PIOE_IFSCDR (0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ + #define REG_PIOE_IFSCER (0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ + #define REG_PIOE_IFSCSR (0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ + #define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ + #define REG_PIOE_PPDDR (0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */ + #define REG_PIOE_PPDER (0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */ + #define REG_PIOE_PPDSR (0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */ + #define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ + #define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ + #define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ + #define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ + #define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */ + #define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ + #define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ + #define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */ + #define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ + #define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */ + #define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */ + #define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ + #define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */ + #define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */ + #define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */ + #define REG_PIOE_VERSION (0x400E16FCU) /**< \brief (PIOE) Version Register */ + #define REG_PIOE_SCHMITT (0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */ + #define REG_PIOE_DRIVER (0x400E1718U) /**< \brief (PIOE) PIO I/O Drive Register */ + #define REG_PIOE_KER (0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */ + #define REG_PIOE_KRCR (0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */ + #define REG_PIOE_KDR (0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */ + #define REG_PIOE_KIER (0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */ + #define REG_PIOE_KIDR (0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */ + #define REG_PIOE_KIMR (0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */ + #define REG_PIOE_KSR (0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */ + #define REG_PIOE_KKPR (0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */ + #define REG_PIOE_KKRR (0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */ + #define REG_PIOE_PCMR (0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */ + #define REG_PIOE_PCIER (0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */ + #define REG_PIOE_PCIDR (0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */ + #define REG_PIOE_PCIMR (0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */ + #define REG_PIOE_PCISR (0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */ + #define REG_PIOE_PCRHR (0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ + #define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ + #define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */ + #define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */ + #define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */ + #define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< \brief (PIOE) Output Status Register */ + #define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ + #define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ + #define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ + #define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ + #define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ + #define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ + #define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ + #define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ + #define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ + #define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ + #define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ + #define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ + #define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ + #define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ + #define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ + #define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ + #define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ + #define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */ + #define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ + #define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ + #define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ + #define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ + #define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */ + #define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */ + #define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */ + #define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ + #define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ + #define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ + #define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ + #define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */ + #define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ + #define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ + #define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */ + #define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ + #define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */ + #define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */ + #define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ + #define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) /**< \brief (PIOE) Lock Status */ + #define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */ + #define REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */ + #define REG_PIOE_VERSION (*(__I uint32_t*)0x400E16FCU) /**< \brief (PIOE) Version Register */ + #define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */ + #define REG_PIOE_DRIVER (*(__IO uint32_t*)0x400E1718U) /**< \brief (PIOE) PIO I/O Drive Register */ + #define REG_PIOE_KER (*(__IO uint32_t*)0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */ + #define REG_PIOE_KRCR (*(__IO uint32_t*)0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */ + #define REG_PIOE_KDR (*(__IO uint32_t*)0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */ + #define REG_PIOE_KIER (*(__O uint32_t*)0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */ + #define REG_PIOE_KIDR (*(__O uint32_t*)0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */ + #define REG_PIOE_KIMR (*(__I uint32_t*)0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */ + #define REG_PIOE_KSR (*(__I uint32_t*)0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */ + #define REG_PIOE_KKPR (*(__I uint32_t*)0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */ + #define REG_PIOE_KKRR (*(__I uint32_t*)0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */ + #define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */ + #define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */ + #define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */ + #define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */ + #define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */ + #define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PIOE_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pmc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pmc.h new file mode 100644 index 00000000..54094217 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pmc.h @@ -0,0 +1,123 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PMC_INSTANCE_ +#define _SAME70_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ + #define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */ + #define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ + #define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ + #define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */ + #define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */ + #define REG_PMC_VERSION (0x400E06FCU) /**< \brief (PMC) Version Register */ + #define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ + #define REG_PMC_OCR (0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ + #define REG_PMC_SLPWK_ER0 (0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */ + #define REG_PMC_SLPWK_DR0 (0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */ + #define REG_PMC_SLPWK_SR0 (0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */ + #define REG_PMC_SLPWK_ASR0 (0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ + #define REG_PMC_PMMR (0x400E0730U) /**< \brief (PMC) PLL Maximum Multiplier Value Register */ + #define REG_PMC_SLPWK_ER1 (0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */ + #define REG_PMC_SLPWK_DR1 (0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */ + #define REG_PMC_SLPWK_SR1 (0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */ + #define REG_PMC_SLPWK_ASR1 (0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */ + #define REG_PMC_SLPWK_AIPR (0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */ + #define REG_PMC_APLLACR (0x400E0758U) /**< \brief (PMC) Audio PLL Analog Configuration Register */ + #define REG_PMC_WMST (0x400E075CU) /**< \brief (PMC) Wait Mode Startup Time Register */ +#else + #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ + #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< \brief (PMC) PLLA Register */ + #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ + #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ + #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */ + #define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */ + #define REG_PMC_VERSION (*(__I uint32_t*)0x400E06FCU) /**< \brief (PMC) Version Register */ + #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ + #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ + #define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */ + #define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */ + #define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */ + #define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ + #define REG_PMC_PMMR (*(__IO uint32_t*)0x400E0730U) /**< \brief (PMC) PLL Maximum Multiplier Value Register */ + #define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */ + #define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */ + #define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */ + #define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */ + #define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */ + #define REG_PMC_APLLACR (*(__IO uint32_t*)0x400E0758U) /**< \brief (PMC) Audio PLL Analog Configuration Register */ + #define REG_PMC_WMST (*(__IO uint32_t*)0x400E075CU) /**< \brief (PMC) Wait Mode Startup Time Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PMC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h new file mode 100644 index 00000000..27c1b906 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h @@ -0,0 +1,259 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PWM0_INSTANCE_ +#define _SAME70_PWM0_INSTANCE_ + +/* ========== Register definition for PWM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PWM0_CLK (0x40020000U) /**< \brief (PWM0) PWM Clock Register */ + #define REG_PWM0_ENA (0x40020004U) /**< \brief (PWM0) PWM Enable Register */ + #define REG_PWM0_DIS (0x40020008U) /**< \brief (PWM0) PWM Disable Register */ + #define REG_PWM0_SR (0x4002000CU) /**< \brief (PWM0) PWM Status Register */ + #define REG_PWM0_IER1 (0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */ + #define REG_PWM0_IDR1 (0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */ + #define REG_PWM0_IMR1 (0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */ + #define REG_PWM0_ISR1 (0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */ + #define REG_PWM0_SCM (0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */ + #define REG_PWM0_DMAR (0x40020024U) /**< \brief (PWM0) PWM DMA Register */ + #define REG_PWM0_SCUC (0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */ + #define REG_PWM0_SCUP (0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */ + #define REG_PWM0_SCUPUPD (0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */ + #define REG_PWM0_IER2 (0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */ + #define REG_PWM0_IDR2 (0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */ + #define REG_PWM0_IMR2 (0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */ + #define REG_PWM0_ISR2 (0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */ + #define REG_PWM0_OOV (0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */ + #define REG_PWM0_OS (0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */ + #define REG_PWM0_OSS (0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */ + #define REG_PWM0_OSC (0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */ + #define REG_PWM0_OSSUPD (0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */ + #define REG_PWM0_OSCUPD (0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */ + #define REG_PWM0_FMR (0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */ + #define REG_PWM0_FSR (0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */ + #define REG_PWM0_FCR (0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */ + #define REG_PWM0_FPV1 (0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */ + #define REG_PWM0_FPE (0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */ + #define REG_PWM0_ELMR (0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */ + #define REG_PWM0_SSPR (0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */ + #define REG_PWM0_SSPUP (0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */ + #define REG_PWM0_SMMR (0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */ + #define REG_PWM0_FPV2 (0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */ + #define REG_PWM0_WPCR (0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */ + #define REG_PWM0_WPSR (0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */ + #define REG_PWM0_VERSION (0x400200FCU) /**< \brief (PWM0) Version Register */ + #define REG_PWM0_CMPV0 (0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */ + #define REG_PWM0_CMPVUPD0 (0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */ + #define REG_PWM0_CMPM0 (0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */ + #define REG_PWM0_CMPMUPD0 (0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */ + #define REG_PWM0_CMPV1 (0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */ + #define REG_PWM0_CMPVUPD1 (0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */ + #define REG_PWM0_CMPM1 (0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */ + #define REG_PWM0_CMPMUPD1 (0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */ + #define REG_PWM0_CMPV2 (0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */ + #define REG_PWM0_CMPVUPD2 (0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */ + #define REG_PWM0_CMPM2 (0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */ + #define REG_PWM0_CMPMUPD2 (0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */ + #define REG_PWM0_CMPV3 (0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */ + #define REG_PWM0_CMPVUPD3 (0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */ + #define REG_PWM0_CMPM3 (0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */ + #define REG_PWM0_CMPMUPD3 (0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */ + #define REG_PWM0_CMPV4 (0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */ + #define REG_PWM0_CMPVUPD4 (0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */ + #define REG_PWM0_CMPM4 (0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */ + #define REG_PWM0_CMPMUPD4 (0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */ + #define REG_PWM0_CMPV5 (0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */ + #define REG_PWM0_CMPVUPD5 (0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */ + #define REG_PWM0_CMPM5 (0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */ + #define REG_PWM0_CMPMUPD5 (0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */ + #define REG_PWM0_CMPV6 (0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */ + #define REG_PWM0_CMPVUPD6 (0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */ + #define REG_PWM0_CMPM6 (0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */ + #define REG_PWM0_CMPMUPD6 (0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */ + #define REG_PWM0_CMPV7 (0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */ + #define REG_PWM0_CMPVUPD7 (0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */ + #define REG_PWM0_CMPM7 (0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */ + #define REG_PWM0_CMPMUPD7 (0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */ + #define REG_PWM0_CMR0 (0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM0_CDTY0 (0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM0_CDTYUPD0 (0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM0_CPRD0 (0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM0_CPRDUPD0 (0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM0_CCNT0 (0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM0_DT0 (0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM0_DTUPD0 (0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM0_CMR1 (0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM0_CDTY1 (0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM0_CDTYUPD1 (0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM0_CPRD1 (0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM0_CPRDUPD1 (0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM0_CCNT1 (0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM0_DT1 (0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM0_DTUPD1 (0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM0_CMR2 (0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM0_CDTY2 (0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM0_CDTYUPD2 (0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM0_CPRD2 (0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM0_CPRDUPD2 (0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM0_CCNT2 (0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM0_DT2 (0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM0_DTUPD2 (0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM0_CMR3 (0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM0_CDTY3 (0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM0_CDTYUPD3 (0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM0_CPRD3 (0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM0_CPRDUPD3 (0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM0_CCNT3 (0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM0_DT3 (0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM0_DTUPD3 (0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM0_CMUPD0 (0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM0_CMUPD1 (0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM0_ETRG1 (0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM0_LEBR1 (0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM0_CMUPD2 (0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM0_ETRG2 (0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM0_LEBR2 (0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM0_CMUPD3 (0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ +#else + #define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM0) PWM Clock Register */ + #define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< \brief (PWM0) PWM Enable Register */ + #define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< \brief (PWM0) PWM Disable Register */ + #define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< \brief (PWM0) PWM Status Register */ + #define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */ + #define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */ + #define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */ + #define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */ + #define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */ + #define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< \brief (PWM0) PWM DMA Register */ + #define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */ + #define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */ + #define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */ + #define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */ + #define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */ + #define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */ + #define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */ + #define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */ + #define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */ + #define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */ + #define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */ + #define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */ + #define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */ + #define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */ + #define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */ + #define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */ + #define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */ + #define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */ + #define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */ + #define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */ + #define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */ + #define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */ + #define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */ + #define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */ + #define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */ + #define REG_PWM0_VERSION (*(__I uint32_t*)0x400200FCU) /**< \brief (PWM0) Version Register */ + #define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */ + #define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */ + #define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */ + #define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */ + #define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */ + #define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */ + #define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */ + #define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */ + #define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */ + #define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */ + #define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */ + #define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */ + #define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */ + #define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */ + #define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */ + #define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */ + #define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */ + #define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */ + #define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */ + #define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */ + #define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */ + #define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */ + #define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */ + #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */ + #define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */ + #define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */ + #define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */ + #define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */ + #define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */ + #define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */ + #define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */ + #define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */ + #define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PWM0_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h new file mode 100644 index 00000000..0e308d78 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h @@ -0,0 +1,259 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PWM1_INSTANCE_ +#define _SAME70_PWM1_INSTANCE_ + +/* ========== Register definition for PWM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PWM1_CLK (0x4005C000U) /**< \brief (PWM1) PWM Clock Register */ + #define REG_PWM1_ENA (0x4005C004U) /**< \brief (PWM1) PWM Enable Register */ + #define REG_PWM1_DIS (0x4005C008U) /**< \brief (PWM1) PWM Disable Register */ + #define REG_PWM1_SR (0x4005C00CU) /**< \brief (PWM1) PWM Status Register */ + #define REG_PWM1_IER1 (0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */ + #define REG_PWM1_IDR1 (0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */ + #define REG_PWM1_IMR1 (0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */ + #define REG_PWM1_ISR1 (0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */ + #define REG_PWM1_SCM (0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */ + #define REG_PWM1_DMAR (0x4005C024U) /**< \brief (PWM1) PWM DMA Register */ + #define REG_PWM1_SCUC (0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */ + #define REG_PWM1_SCUP (0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */ + #define REG_PWM1_SCUPUPD (0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */ + #define REG_PWM1_IER2 (0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */ + #define REG_PWM1_IDR2 (0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */ + #define REG_PWM1_IMR2 (0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */ + #define REG_PWM1_ISR2 (0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */ + #define REG_PWM1_OOV (0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */ + #define REG_PWM1_OS (0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */ + #define REG_PWM1_OSS (0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */ + #define REG_PWM1_OSC (0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */ + #define REG_PWM1_OSSUPD (0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */ + #define REG_PWM1_OSCUPD (0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */ + #define REG_PWM1_FMR (0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */ + #define REG_PWM1_FSR (0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */ + #define REG_PWM1_FCR (0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */ + #define REG_PWM1_FPV1 (0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */ + #define REG_PWM1_FPE (0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */ + #define REG_PWM1_ELMR (0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */ + #define REG_PWM1_SSPR (0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */ + #define REG_PWM1_SSPUP (0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */ + #define REG_PWM1_SMMR (0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */ + #define REG_PWM1_FPV2 (0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */ + #define REG_PWM1_WPCR (0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */ + #define REG_PWM1_WPSR (0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */ + #define REG_PWM1_VERSION (0x4005C0FCU) /**< \brief (PWM1) Version Register */ + #define REG_PWM1_CMPV0 (0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */ + #define REG_PWM1_CMPVUPD0 (0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */ + #define REG_PWM1_CMPM0 (0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */ + #define REG_PWM1_CMPMUPD0 (0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */ + #define REG_PWM1_CMPV1 (0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */ + #define REG_PWM1_CMPVUPD1 (0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */ + #define REG_PWM1_CMPM1 (0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */ + #define REG_PWM1_CMPMUPD1 (0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */ + #define REG_PWM1_CMPV2 (0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */ + #define REG_PWM1_CMPVUPD2 (0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */ + #define REG_PWM1_CMPM2 (0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */ + #define REG_PWM1_CMPMUPD2 (0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */ + #define REG_PWM1_CMPV3 (0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */ + #define REG_PWM1_CMPVUPD3 (0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */ + #define REG_PWM1_CMPM3 (0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */ + #define REG_PWM1_CMPMUPD3 (0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */ + #define REG_PWM1_CMPV4 (0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */ + #define REG_PWM1_CMPVUPD4 (0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */ + #define REG_PWM1_CMPM4 (0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */ + #define REG_PWM1_CMPMUPD4 (0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */ + #define REG_PWM1_CMPV5 (0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */ + #define REG_PWM1_CMPVUPD5 (0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */ + #define REG_PWM1_CMPM5 (0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */ + #define REG_PWM1_CMPMUPD5 (0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */ + #define REG_PWM1_CMPV6 (0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */ + #define REG_PWM1_CMPVUPD6 (0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */ + #define REG_PWM1_CMPM6 (0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */ + #define REG_PWM1_CMPMUPD6 (0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */ + #define REG_PWM1_CMPV7 (0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */ + #define REG_PWM1_CMPVUPD7 (0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */ + #define REG_PWM1_CMPM7 (0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */ + #define REG_PWM1_CMPMUPD7 (0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */ + #define REG_PWM1_CMR0 (0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM1_CDTY0 (0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM1_CDTYUPD0 (0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM1_CPRD0 (0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM1_CPRDUPD0 (0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM1_CCNT0 (0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM1_DT0 (0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM1_DTUPD0 (0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM1_CMR1 (0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM1_CDTY1 (0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM1_CDTYUPD1 (0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM1_CPRD1 (0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM1_CPRDUPD1 (0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM1_CCNT1 (0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM1_DT1 (0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM1_DTUPD1 (0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM1_CMR2 (0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM1_CDTY2 (0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM1_CDTYUPD2 (0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM1_CPRD2 (0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM1_CPRDUPD2 (0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM1_CCNT2 (0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM1_DT2 (0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM1_DTUPD2 (0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM1_CMR3 (0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM1_CDTY3 (0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM1_CDTYUPD3 (0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM1_CPRD3 (0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM1_CPRDUPD3 (0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM1_CCNT3 (0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM1_DT3 (0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM1_DTUPD3 (0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM1_CMUPD0 (0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM1_CMUPD1 (0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM1_ETRG1 (0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM1_LEBR1 (0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM1_CMUPD2 (0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM1_ETRG2 (0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM1_LEBR2 (0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM1_CMUPD3 (0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */ +#else + #define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U) /**< \brief (PWM1) PWM Clock Register */ + #define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) /**< \brief (PWM1) PWM Enable Register */ + #define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) /**< \brief (PWM1) PWM Disable Register */ + #define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU) /**< \brief (PWM1) PWM Status Register */ + #define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */ + #define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */ + #define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */ + #define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */ + #define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */ + #define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) /**< \brief (PWM1) PWM DMA Register */ + #define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */ + #define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */ + #define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */ + #define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */ + #define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */ + #define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */ + #define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */ + #define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */ + #define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */ + #define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */ + #define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */ + #define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */ + #define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */ + #define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */ + #define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */ + #define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */ + #define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */ + #define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */ + #define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */ + #define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */ + #define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */ + #define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */ + #define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */ + #define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */ + #define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */ + #define REG_PWM1_VERSION (*(__I uint32_t*)0x4005C0FCU) /**< \brief (PWM1) Version Register */ + #define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */ + #define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */ + #define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */ + #define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */ + #define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */ + #define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */ + #define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */ + #define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */ + #define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */ + #define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */ + #define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */ + #define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */ + #define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */ + #define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */ + #define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */ + #define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */ + #define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */ + #define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */ + #define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */ + #define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */ + #define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */ + #define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */ + #define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */ + #define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */ + #define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */ + #define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */ + #define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */ + #define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */ + #define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */ + #define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */ + #define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */ + #define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */ + #define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PWM1_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h new file mode 100644 index 00000000..0705e815 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h @@ -0,0 +1,77 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_QSPI_INSTANCE_ +#define _SAME70_QSPI_INSTANCE_ + +/* ========== Register definition for QSPI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_QSPI_CR (0x4007C000U) /**< \brief (QSPI) Control Register */ + #define REG_QSPI_MR (0x4007C004U) /**< \brief (QSPI) Mode Register */ + #define REG_QSPI_RDR (0x4007C008U) /**< \brief (QSPI) Receive Data Register */ + #define REG_QSPI_TDR (0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */ + #define REG_QSPI_SR (0x4007C010U) /**< \brief (QSPI) Status Register */ + #define REG_QSPI_IER (0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */ + #define REG_QSPI_IDR (0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */ + #define REG_QSPI_IMR (0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */ + #define REG_QSPI_SCR (0x4007C020U) /**< \brief (QSPI) Serial Clock Register */ + #define REG_QSPI_IAR (0x4007C030U) /**< \brief (QSPI) Instruction Address Register */ + #define REG_QSPI_ICR (0x4007C034U) /**< \brief (QSPI) Instruction Code Register */ + #define REG_QSPI_IFR (0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */ + #define REG_QSPI_SMR (0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */ + #define REG_QSPI_SKR (0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */ + #define REG_QSPI_WPMR (0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */ + #define REG_QSPI_WPSR (0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */ + #define REG_QSPI_VERSION (0x4007C0FCU) /**< \brief (QSPI) Version Register */ +#else + #define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< \brief (QSPI) Control Register */ + #define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< \brief (QSPI) Mode Register */ + #define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< \brief (QSPI) Receive Data Register */ + #define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */ + #define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< \brief (QSPI) Status Register */ + #define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */ + #define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */ + #define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */ + #define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< \brief (QSPI) Serial Clock Register */ + #define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< \brief (QSPI) Instruction Address Register */ + #define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< \brief (QSPI) Instruction Code Register */ + #define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */ + #define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */ + #define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */ + #define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */ + #define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */ + #define REG_QSPI_VERSION (*(__I uint32_t*)0x4007C0FCU) /**< \brief (QSPI) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_QSPI_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h new file mode 100644 index 00000000..d9a2e52b --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h @@ -0,0 +1,49 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RSTC_INSTANCE_ +#define _SAME70_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RSTC_CR (0x400E1800U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (0x400E1804U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (0x400E1808U) /**< \brief (RSTC) Mode Register */ +#else + #define REG_RSTC_CR (*(__O uint32_t*)0x400E1800U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (*(__I uint32_t*)0x400E1804U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (*(__IO uint32_t*)0x400E1808U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_RSTC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h new file mode 100644 index 00000000..572d024d --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h @@ -0,0 +1,48 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70_RSWDT_INSTANCE_ +#define _SAME70_RSWDT_INSTANCE_ + +/* ========== Register definition for RSWDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RSWDT_CR (0x400E1900U) /**< \brief (RSWDT) Control Register */ + #define REG_RSWDT_MR (0x400E1904U) /**< \brief (RSWDT) Mode Register */ + #define REG_RSWDT_SR (0x400E1908U) /**< \brief (RSWDT) Status Register */ +#else + #define REG_RSWDT_CR (*(__O uint32_t*)0x400E1900U) /**< \brief (RSWDT) Control Register */ + #define REG_RSWDT_MR (*(__IO uint32_t*)0x400E1904U) /**< \brief (RSWDT) Mode Register */ + #define REG_RSWDT_SR (*(__I uint32_t*)0x400E1908U) /**< \brief (RSWDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_RSWDT_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtc.h new file mode 100644 index 00000000..cdbd2bee --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtc.h @@ -0,0 +1,71 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RTC_INSTANCE_ +#define _SAME70_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTC_CR (0x400E1860U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (0x400E1864U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (0x400E1868U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (0x400E186CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (0x400E1870U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (0x400E1878U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (0x400E188CU) /**< \brief (RTC) Valid Entry Register */ + #define REG_RTC_WPMR (0x400E1944U) /**< \brief (RTC) Write Protection Mode Register */ + #define REG_RTC_VERSION (0x400E195CU) /**< \brief (RTC) Version Register */ +#else + #define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */ + #define REG_RTC_WPMR (*(__IO uint32_t*)0x400E1944U) /**< \brief (RTC) Write Protection Mode Register */ + #define REG_RTC_VERSION (*(__I uint32_t*)0x400E195CU) /**< \brief (RTC) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_RTC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtt.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtt.h new file mode 100644 index 00000000..d156c84f --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtt.h @@ -0,0 +1,51 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RTT_INSTANCE_ +#define _SAME70_RTT_INSTANCE_ + +/* ========== Register definition for RTT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTT_MR (0x400E1830U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (0x400E1834U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (0x400E1838U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (0x400E183CU) /**< \brief (RTT) Status Register */ +#else + #define REG_RTT_MR (*(__IO uint32_t*)0x400E1830U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (*(__IO uint32_t*)0x400E1834U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (*(__I uint32_t*)0x400E1838U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (*(__I uint32_t*)0x400E183CU) /**< \brief (RTT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_RTT_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/sdramc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/sdramc.h new file mode 100644 index 00000000..ee229408 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/sdramc.h @@ -0,0 +1,71 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SDRAMC_INSTANCE_ +#define _SAME70_SDRAMC_INSTANCE_ + +/* ========== Register definition for SDRAMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SDRAMC_MR (0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */ + #define REG_SDRAMC_TR (0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ + #define REG_SDRAMC_CR (0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ + #define REG_SDRAMC_LPR (0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ + #define REG_SDRAMC_IER (0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ + #define REG_SDRAMC_IDR (0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ + #define REG_SDRAMC_IMR (0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ + #define REG_SDRAMC_ISR (0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ + #define REG_SDRAMC_MDR (0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ + #define REG_SDRAMC_CFR1 (0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ + #define REG_SDRAMC_OCMS (0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */ + #define REG_SDRAMC_OCMS_KEY1 (0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */ + #define REG_SDRAMC_OCMS_KEY2 (0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */ + #define REG_SDRAMC_VERSION (0x400840FCU) /**< \brief (SDRAMC) SDRAMC Version Register */ +#else + #define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */ + #define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ + #define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ + #define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ + #define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ + #define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ + #define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ + #define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ + #define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ + #define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ + #define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */ + #define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */ + #define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */ + #define REG_SDRAMC_VERSION (*(__I uint32_t*)0x400840FCU) /**< \brief (SDRAMC) SDRAMC Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SDRAMC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/smc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/smc.h new file mode 100644 index 00000000..9a5c8776 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/smc.h @@ -0,0 +1,87 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SMC_INSTANCE_ +#define _SAME70_SMC_INSTANCE_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SMC_SETUP0 (0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (0x4008000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (0x4008001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (0x4008002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (0x4008003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ + #define REG_SMC_OCMS (0x40080080U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling Register */ + #define REG_SMC_KEY1 (0x40080084U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling KEY1 Register */ + #define REG_SMC_KEY2 (0x40080088U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling KEY2 Register */ + #define REG_SMC_WPMR (0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */ + #define REG_SMC_WPSR (0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */ + #define REG_SMC_VERSION (0x400800FCU) /**< \brief (SMC) SMC Version Register */ +#else + #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ + #define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling Register */ + #define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling KEY1 Register */ + #define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling KEY2 Register */ + #define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */ + #define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */ + #define REG_SMC_VERSION (*(__I uint32_t*)0x400800FCU) /**< \brief (SMC) SMC Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SMC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h new file mode 100644 index 00000000..52c70284 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SPI0_INSTANCE_ +#define _SAME70_SPI0_INSTANCE_ + +/* ========== Register definition for SPI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SPI0_CR (0x40008000U) /**< \brief (SPI0) Control Register */ + #define REG_SPI0_MR (0x40008004U) /**< \brief (SPI0) Mode Register */ + #define REG_SPI0_RDR (0x40008008U) /**< \brief (SPI0) Receive Data Register */ + #define REG_SPI0_TDR (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ + #define REG_SPI0_SR (0x40008010U) /**< \brief (SPI0) Status Register */ + #define REG_SPI0_IER (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ + #define REG_SPI0_IDR (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ + #define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ + #define REG_SPI0_CSR (0x40008030U) /**< \brief (SPI0) Chip Select Register (CS_number = 0) */ + #define REG_SPI0_WPMR (0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */ + #define REG_SPI0_WPSR (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ + #define REG_SPI0_VERSION (0x400080FCU) /**< \brief (SPI0) Version Register */ +#else + #define REG_SPI0_CR (*(__O uint32_t*)0x40008000U) /**< \brief (SPI0) Control Register */ + #define REG_SPI0_MR (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI0) Mode Register */ + #define REG_SPI0_RDR (*(__I uint32_t*)0x40008008U) /**< \brief (SPI0) Receive Data Register */ + #define REG_SPI0_TDR (*(__O uint32_t*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ + #define REG_SPI0_SR (*(__I uint32_t*)0x40008010U) /**< \brief (SPI0) Status Register */ + #define REG_SPI0_IER (*(__O uint32_t*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ + #define REG_SPI0_IDR (*(__O uint32_t*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ + #define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ + #define REG_SPI0_CSR (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI0) Chip Select Register (CS_number = 0) */ + #define REG_SPI0_WPMR (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */ + #define REG_SPI0_WPSR (*(__I uint32_t*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ + #define REG_SPI0_VERSION (*(__I uint32_t*)0x400080FCU) /**< \brief (SPI0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SPI0_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h new file mode 100644 index 00000000..d7db3d07 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SPI1_INSTANCE_ +#define _SAME70_SPI1_INSTANCE_ + +/* ========== Register definition for SPI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SPI1_CR (0x40058000U) /**< \brief (SPI1) Control Register */ + #define REG_SPI1_MR (0x40058004U) /**< \brief (SPI1) Mode Register */ + #define REG_SPI1_RDR (0x40058008U) /**< \brief (SPI1) Receive Data Register */ + #define REG_SPI1_TDR (0x4005800CU) /**< \brief (SPI1) Transmit Data Register */ + #define REG_SPI1_SR (0x40058010U) /**< \brief (SPI1) Status Register */ + #define REG_SPI1_IER (0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */ + #define REG_SPI1_IDR (0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */ + #define REG_SPI1_IMR (0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */ + #define REG_SPI1_CSR (0x40058030U) /**< \brief (SPI1) Chip Select Register (CS_number = 0) */ + #define REG_SPI1_WPMR (0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */ + #define REG_SPI1_WPSR (0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */ + #define REG_SPI1_VERSION (0x400580FCU) /**< \brief (SPI1) Version Register */ +#else + #define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< \brief (SPI1) Control Register */ + #define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< \brief (SPI1) Mode Register */ + #define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< \brief (SPI1) Receive Data Register */ + #define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< \brief (SPI1) Transmit Data Register */ + #define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< \brief (SPI1) Status Register */ + #define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */ + #define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */ + #define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */ + #define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< \brief (SPI1) Chip Select Register (CS_number = 0) */ + #define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */ + #define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */ + #define REG_SPI1_VERSION (*(__I uint32_t*)0x400580FCU) /**< \brief (SPI1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SPI1_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/ssc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/ssc.h new file mode 100644 index 00000000..706f13dd --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/ssc.h @@ -0,0 +1,81 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SSC_INSTANCE_ +#define _SAME70_SSC_INSTANCE_ + +/* ========== Register definition for SSC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */ + #define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protection Status Register */ + #define REG_SSC_VERSION (0x400040FCU) /**< \brief (SSC) Version Register */ +#else + #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */ + #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protection Status Register */ + #define REG_SSC_VERSION (*(__I uint32_t*)0x400040FCU) /**< \brief (SSC) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SSC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/supc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/supc.h new file mode 100644 index 00000000..dee9e81b --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/supc.h @@ -0,0 +1,57 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SUPC_INSTANCE_ +#define _SAME70_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SUPC_CR (0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ + #define REG_SUPC_WUIR (0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ + #define REG_SUPC_SR (0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */ + #define REG_SYSC_VERSION (0x400E190CU) /**< \brief (SUPC) Version Register */ +#else + #define REG_SUPC_CR (*(__O uint32_t*)0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (*(__IO uint32_t*)0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ + #define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ + #define REG_SUPC_SR (*(__I uint32_t*)0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */ + #define REG_SYSC_VERSION (*(__I uint32_t*)0x400E190CU) /**< \brief (SUPC) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SUPC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc0.h new file mode 100644 index 00000000..e2cc2461 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc0.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TC0_INSTANCE_ +#define _SAME70_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC0_CCR0 (0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_RAB0 (0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */ + #define REG_TC0_CV0 (0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_EMR0 (0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */ + #define REG_TC0_CCR1 (0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_RAB1 (0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */ + #define REG_TC0_CV1 (0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_EMR1 (0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */ + #define REG_TC0_CCR2 (0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_RAB2 (0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */ + #define REG_TC0_CV2 (0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_EMR2 (0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */ + #define REG_TC0_BCR (0x4000C0C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (0x4000C0C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */ + #define REG_TC0_VER (0x4000C0FCU) /**< \brief (TC0) Version Register */ +#else + #define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */ + #define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */ + #define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */ + #define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */ + #define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */ + #define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */ + #define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */ + #define REG_TC0_VER (*(__I uint32_t*)0x4000C0FCU) /**< \brief (TC0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TC0_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc1.h new file mode 100644 index 00000000..d8f78fcd --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc1.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TC1_INSTANCE_ +#define _SAME70_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC1_CCR0 (0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_RAB0 (0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */ + #define REG_TC1_CV0 (0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (0x40010014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (0x40010018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_EMR0 (0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ + #define REG_TC1_CCR1 (0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_RAB1 (0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */ + #define REG_TC1_CV1 (0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (0x40010054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (0x40010058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_EMR1 (0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ + #define REG_TC1_CCR2 (0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_RAB2 (0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */ + #define REG_TC1_CV2 (0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (0x40010094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (0x40010098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_EMR2 (0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ + #define REG_TC1_BCR (0x400100C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (0x400100C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (0x400100D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */ + #define REG_TC1_VER (0x400100FCU) /**< \brief (TC1) Version Register */ +#else + #define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */ + #define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ + #define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */ + #define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ + #define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */ + #define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ + #define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */ + #define REG_TC1_VER (*(__I uint32_t*)0x400100FCU) /**< \brief (TC1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TC1_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc2.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc2.h new file mode 100644 index 00000000..8d4a950c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc2.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TC2_INSTANCE_ +#define _SAME70_TC2_INSTANCE_ + +/* ========== Register definition for TC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC2_CCR0 (0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ + #define REG_TC2_CMR0 (0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ + #define REG_TC2_SMMR0 (0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC2_RAB0 (0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */ + #define REG_TC2_CV0 (0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */ + #define REG_TC2_RA0 (0x40014014U) /**< \brief (TC2) Register A (channel = 0) */ + #define REG_TC2_RB0 (0x40014018U) /**< \brief (TC2) Register B (channel = 0) */ + #define REG_TC2_RC0 (0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */ + #define REG_TC2_SR0 (0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */ + #define REG_TC2_IER0 (0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ + #define REG_TC2_IDR0 (0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ + #define REG_TC2_IMR0 (0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ + #define REG_TC2_EMR0 (0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */ + #define REG_TC2_CCR1 (0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ + #define REG_TC2_CMR1 (0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ + #define REG_TC2_SMMR1 (0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC2_RAB1 (0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */ + #define REG_TC2_CV1 (0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */ + #define REG_TC2_RA1 (0x40014054U) /**< \brief (TC2) Register A (channel = 1) */ + #define REG_TC2_RB1 (0x40014058U) /**< \brief (TC2) Register B (channel = 1) */ + #define REG_TC2_RC1 (0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */ + #define REG_TC2_SR1 (0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */ + #define REG_TC2_IER1 (0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ + #define REG_TC2_IDR1 (0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ + #define REG_TC2_IMR1 (0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ + #define REG_TC2_EMR1 (0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */ + #define REG_TC2_CCR2 (0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ + #define REG_TC2_CMR2 (0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ + #define REG_TC2_SMMR2 (0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC2_RAB2 (0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */ + #define REG_TC2_CV2 (0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */ + #define REG_TC2_RA2 (0x40014094U) /**< \brief (TC2) Register A (channel = 2) */ + #define REG_TC2_RB2 (0x40014098U) /**< \brief (TC2) Register B (channel = 2) */ + #define REG_TC2_RC2 (0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */ + #define REG_TC2_SR2 (0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */ + #define REG_TC2_IER2 (0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ + #define REG_TC2_IDR2 (0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ + #define REG_TC2_IMR2 (0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ + #define REG_TC2_EMR2 (0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */ + #define REG_TC2_BCR (0x400140C0U) /**< \brief (TC2) Block Control Register */ + #define REG_TC2_BMR (0x400140C4U) /**< \brief (TC2) Block Mode Register */ + #define REG_TC2_QIER (0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ + #define REG_TC2_QIDR (0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ + #define REG_TC2_QIMR (0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ + #define REG_TC2_QISR (0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ + #define REG_TC2_FMR (0x400140D8U) /**< \brief (TC2) Fault Mode Register */ + #define REG_TC2_WPMR (0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */ + #define REG_TC2_VER (0x400140FCU) /**< \brief (TC2) Version Register */ +#else + #define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ + #define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ + #define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */ + #define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */ + #define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U) /**< \brief (TC2) Register A (channel = 0) */ + #define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC2) Register B (channel = 0) */ + #define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */ + #define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */ + #define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ + #define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ + #define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ + #define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */ + #define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ + #define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ + #define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */ + #define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */ + #define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U) /**< \brief (TC2) Register A (channel = 1) */ + #define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U) /**< \brief (TC2) Register B (channel = 1) */ + #define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */ + #define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */ + #define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ + #define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ + #define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ + #define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */ + #define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ + #define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ + #define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */ + #define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */ + #define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC2) Register A (channel = 2) */ + #define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U) /**< \brief (TC2) Register B (channel = 2) */ + #define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */ + #define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */ + #define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ + #define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ + #define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ + #define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */ + #define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< \brief (TC2) Block Control Register */ + #define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U) /**< \brief (TC2) Block Mode Register */ + #define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ + #define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ + #define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ + #define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ + #define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U) /**< \brief (TC2) Fault Mode Register */ + #define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */ + #define REG_TC2_VER (*(__I uint32_t*)0x400140FCU) /**< \brief (TC2) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TC2_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc3.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc3.h new file mode 100644 index 00000000..29351ce4 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc3.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TC3_INSTANCE_ +#define _SAME70_TC3_INSTANCE_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC3_CCR0 (0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */ + #define REG_TC3_CMR0 (0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */ + #define REG_TC3_SMMR0 (0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC3_RAB0 (0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */ + #define REG_TC3_CV0 (0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */ + #define REG_TC3_RA0 (0x40054014U) /**< \brief (TC3) Register A (channel = 0) */ + #define REG_TC3_RB0 (0x40054018U) /**< \brief (TC3) Register B (channel = 0) */ + #define REG_TC3_RC0 (0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */ + #define REG_TC3_SR0 (0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */ + #define REG_TC3_IER0 (0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */ + #define REG_TC3_IDR0 (0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */ + #define REG_TC3_IMR0 (0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */ + #define REG_TC3_EMR0 (0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */ + #define REG_TC3_CCR1 (0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */ + #define REG_TC3_CMR1 (0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */ + #define REG_TC3_SMMR1 (0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC3_RAB1 (0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */ + #define REG_TC3_CV1 (0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */ + #define REG_TC3_RA1 (0x40054054U) /**< \brief (TC3) Register A (channel = 1) */ + #define REG_TC3_RB1 (0x40054058U) /**< \brief (TC3) Register B (channel = 1) */ + #define REG_TC3_RC1 (0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */ + #define REG_TC3_SR1 (0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */ + #define REG_TC3_IER1 (0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */ + #define REG_TC3_IDR1 (0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */ + #define REG_TC3_IMR1 (0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */ + #define REG_TC3_EMR1 (0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */ + #define REG_TC3_CCR2 (0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */ + #define REG_TC3_CMR2 (0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */ + #define REG_TC3_SMMR2 (0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC3_RAB2 (0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */ + #define REG_TC3_CV2 (0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */ + #define REG_TC3_RA2 (0x40054094U) /**< \brief (TC3) Register A (channel = 2) */ + #define REG_TC3_RB2 (0x40054098U) /**< \brief (TC3) Register B (channel = 2) */ + #define REG_TC3_RC2 (0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */ + #define REG_TC3_SR2 (0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */ + #define REG_TC3_IER2 (0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */ + #define REG_TC3_IDR2 (0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */ + #define REG_TC3_IMR2 (0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */ + #define REG_TC3_EMR2 (0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */ + #define REG_TC3_BCR (0x400540C0U) /**< \brief (TC3) Block Control Register */ + #define REG_TC3_BMR (0x400540C4U) /**< \brief (TC3) Block Mode Register */ + #define REG_TC3_QIER (0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */ + #define REG_TC3_QIDR (0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */ + #define REG_TC3_QIMR (0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */ + #define REG_TC3_QISR (0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */ + #define REG_TC3_FMR (0x400540D8U) /**< \brief (TC3) Fault Mode Register */ + #define REG_TC3_WPMR (0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */ + #define REG_TC3_VER (0x400540FCU) /**< \brief (TC3) Version Register */ +#else + #define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */ + #define REG_TC3_CMR0 (*(__IO uint32_t*)0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */ + #define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */ + #define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */ + #define REG_TC3_RA0 (*(__IO uint32_t*)0x40054014U) /**< \brief (TC3) Register A (channel = 0) */ + #define REG_TC3_RB0 (*(__IO uint32_t*)0x40054018U) /**< \brief (TC3) Register B (channel = 0) */ + #define REG_TC3_RC0 (*(__IO uint32_t*)0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */ + #define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */ + #define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */ + #define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */ + #define REG_TC3_IMR0 (*(__I uint32_t*)0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */ + #define REG_TC3_EMR0 (*(__IO uint32_t*)0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */ + #define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */ + #define REG_TC3_CMR1 (*(__IO uint32_t*)0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */ + #define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */ + #define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */ + #define REG_TC3_RA1 (*(__IO uint32_t*)0x40054054U) /**< \brief (TC3) Register A (channel = 1) */ + #define REG_TC3_RB1 (*(__IO uint32_t*)0x40054058U) /**< \brief (TC3) Register B (channel = 1) */ + #define REG_TC3_RC1 (*(__IO uint32_t*)0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */ + #define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */ + #define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */ + #define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */ + #define REG_TC3_IMR1 (*(__I uint32_t*)0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */ + #define REG_TC3_EMR1 (*(__IO uint32_t*)0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */ + #define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */ + #define REG_TC3_CMR2 (*(__IO uint32_t*)0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */ + #define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */ + #define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */ + #define REG_TC3_RA2 (*(__IO uint32_t*)0x40054094U) /**< \brief (TC3) Register A (channel = 2) */ + #define REG_TC3_RB2 (*(__IO uint32_t*)0x40054098U) /**< \brief (TC3) Register B (channel = 2) */ + #define REG_TC3_RC2 (*(__IO uint32_t*)0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */ + #define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */ + #define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */ + #define REG_TC3_IDR2 (*(__O uint32_t*)0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */ + #define REG_TC3_IMR2 (*(__I uint32_t*)0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */ + #define REG_TC3_EMR2 (*(__IO uint32_t*)0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */ + #define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) /**< \brief (TC3) Block Control Register */ + #define REG_TC3_BMR (*(__IO uint32_t*)0x400540C4U) /**< \brief (TC3) Block Mode Register */ + #define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */ + #define REG_TC3_QIDR (*(__O uint32_t*)0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */ + #define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */ + #define REG_TC3_QISR (*(__I uint32_t*)0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */ + #define REG_TC3_FMR (*(__IO uint32_t*)0x400540D8U) /**< \brief (TC3) Fault Mode Register */ + #define REG_TC3_WPMR (*(__IO uint32_t*)0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */ + #define REG_TC3_VER (*(__I uint32_t*)0x400540FCU) /**< \brief (TC3) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TC3_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/trng.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/trng.h new file mode 100644 index 00000000..e0f1b062 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/trng.h @@ -0,0 +1,57 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TRNG_INSTANCE_ +#define _SAME70_TRNG_INSTANCE_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TRNG_CR (0x40070000U) /**< \brief (TRNG) Control Register */ + #define REG_TRNG_IER (0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */ + #define REG_TRNG_IDR (0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */ + #define REG_TRNG_IMR (0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */ + #define REG_TRNG_ISR (0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */ + #define REG_TRNG_ODATA (0x40070050U) /**< \brief (TRNG) Output Data Register */ + #define REG_TRNG_VERSION (0x400700FCU) /**< \brief (TRNG) Version Register */ +#else + #define REG_TRNG_CR (*(__O uint32_t*)0x40070000U) /**< \brief (TRNG) Control Register */ + #define REG_TRNG_IER (*(__O uint32_t*)0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */ + #define REG_TRNG_IDR (*(__O uint32_t*)0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */ + #define REG_TRNG_IMR (*(__I uint32_t*)0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */ + #define REG_TRNG_ISR (*(__I uint32_t*)0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */ + #define REG_TRNG_ODATA (*(__I uint32_t*)0x40070050U) /**< \brief (TRNG) Output Data Register */ + #define REG_TRNG_VERSION (*(__I uint32_t*)0x400700FCU) /**< \brief (TRNG) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TRNG_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h new file mode 100644 index 00000000..35504a31 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h @@ -0,0 +1,79 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TWIHS0_INSTANCE_ +#define _SAME70_TWIHS0_INSTANCE_ + +/* ========== Register definition for TWIHS0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS0_CR (0x40018000U) /**< \brief (TWIHS0) Control Register */ + #define REG_TWIHS0_MMR (0x40018004U) /**< \brief (TWIHS0) Master Mode Register */ + #define REG_TWIHS0_SMR (0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */ + #define REG_TWIHS0_IADR (0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */ + #define REG_TWIHS0_CWGR (0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */ + #define REG_TWIHS0_SR (0x40018020U) /**< \brief (TWIHS0) Status Register */ + #define REG_TWIHS0_IER (0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */ + #define REG_TWIHS0_IDR (0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */ + #define REG_TWIHS0_IMR (0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */ + #define REG_TWIHS0_RHR (0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */ + #define REG_TWIHS0_THR (0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */ + #define REG_TWIHS0_SMBTR (0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */ + #define REG_TWIHS0_FILTR (0x40018044U) /**< \brief (TWIHS0) Filter Register */ + #define REG_TWIHS0_SWMR (0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */ + #define REG_TWIHS0_DR (0x400180D0U) /**< \brief (TWIHS0) Debug Register */ + #define REG_TWIHS0_WPMR (0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */ + #define REG_TWIHS0_WPSR (0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */ + #define REG_TWIHS0_VER (0x400180FCU) /**< \brief (TWIHS0) Version Register */ +#else + #define REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) /**< \brief (TWIHS0) Control Register */ + #define REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) /**< \brief (TWIHS0) Master Mode Register */ + #define REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */ + #define REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */ + #define REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */ + #define REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) /**< \brief (TWIHS0) Status Register */ + #define REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */ + #define REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */ + #define REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */ + #define REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */ + #define REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */ + #define REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */ + #define REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) /**< \brief (TWIHS0) Filter Register */ + #define REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */ + #define REG_TWIHS0_DR (*(__I uint32_t*)0x400180D0U) /**< \brief (TWIHS0) Debug Register */ + #define REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */ + #define REG_TWIHS0_WPSR (*(__I uint32_t*)0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */ + #define REG_TWIHS0_VER (*(__I uint32_t*)0x400180FCU) /**< \brief (TWIHS0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TWIHS0_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h new file mode 100644 index 00000000..f76e761a --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h @@ -0,0 +1,79 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TWIHS1_INSTANCE_ +#define _SAME70_TWIHS1_INSTANCE_ + +/* ========== Register definition for TWIHS1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS1_CR (0x4001C000U) /**< \brief (TWIHS1) Control Register */ + #define REG_TWIHS1_MMR (0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */ + #define REG_TWIHS1_SMR (0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */ + #define REG_TWIHS1_IADR (0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */ + #define REG_TWIHS1_CWGR (0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */ + #define REG_TWIHS1_SR (0x4001C020U) /**< \brief (TWIHS1) Status Register */ + #define REG_TWIHS1_IER (0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */ + #define REG_TWIHS1_IDR (0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */ + #define REG_TWIHS1_IMR (0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */ + #define REG_TWIHS1_RHR (0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */ + #define REG_TWIHS1_THR (0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */ + #define REG_TWIHS1_SMBTR (0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */ + #define REG_TWIHS1_FILTR (0x4001C044U) /**< \brief (TWIHS1) Filter Register */ + #define REG_TWIHS1_SWMR (0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */ + #define REG_TWIHS1_DR (0x4001C0D0U) /**< \brief (TWIHS1) Debug Register */ + #define REG_TWIHS1_WPMR (0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */ + #define REG_TWIHS1_WPSR (0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */ + #define REG_TWIHS1_VER (0x4001C0FCU) /**< \brief (TWIHS1) Version Register */ +#else + #define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< \brief (TWIHS1) Control Register */ + #define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */ + #define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */ + #define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */ + #define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */ + #define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< \brief (TWIHS1) Status Register */ + #define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */ + #define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */ + #define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */ + #define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */ + #define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */ + #define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */ + #define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< \brief (TWIHS1) Filter Register */ + #define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */ + #define REG_TWIHS1_DR (*(__I uint32_t*)0x4001C0D0U) /**< \brief (TWIHS1) Debug Register */ + #define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */ + #define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */ + #define REG_TWIHS1_VER (*(__I uint32_t*)0x4001C0FCU) /**< \brief (TWIHS1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TWIHS1_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h new file mode 100644 index 00000000..bedb4b91 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h @@ -0,0 +1,79 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TWIHS2_INSTANCE_ +#define _SAME70_TWIHS2_INSTANCE_ + +/* ========== Register definition for TWIHS2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS2_CR (0x40060000U) /**< \brief (TWIHS2) Control Register */ + #define REG_TWIHS2_MMR (0x40060004U) /**< \brief (TWIHS2) Master Mode Register */ + #define REG_TWIHS2_SMR (0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */ + #define REG_TWIHS2_IADR (0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */ + #define REG_TWIHS2_CWGR (0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */ + #define REG_TWIHS2_SR (0x40060020U) /**< \brief (TWIHS2) Status Register */ + #define REG_TWIHS2_IER (0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */ + #define REG_TWIHS2_IDR (0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */ + #define REG_TWIHS2_IMR (0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */ + #define REG_TWIHS2_RHR (0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */ + #define REG_TWIHS2_THR (0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */ + #define REG_TWIHS2_SMBTR (0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */ + #define REG_TWIHS2_FILTR (0x40060044U) /**< \brief (TWIHS2) Filter Register */ + #define REG_TWIHS2_SWMR (0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */ + #define REG_TWIHS2_DR (0x400600D0U) /**< \brief (TWIHS2) Debug Register */ + #define REG_TWIHS2_WPMR (0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */ + #define REG_TWIHS2_WPSR (0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */ + #define REG_TWIHS2_VER (0x400600FCU) /**< \brief (TWIHS2) Version Register */ +#else + #define REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) /**< \brief (TWIHS2) Control Register */ + #define REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) /**< \brief (TWIHS2) Master Mode Register */ + #define REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */ + #define REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */ + #define REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */ + #define REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) /**< \brief (TWIHS2) Status Register */ + #define REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */ + #define REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */ + #define REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */ + #define REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */ + #define REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */ + #define REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */ + #define REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) /**< \brief (TWIHS2) Filter Register */ + #define REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */ + #define REG_TWIHS2_DR (*(__I uint32_t*)0x400600D0U) /**< \brief (TWIHS2) Debug Register */ + #define REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */ + #define REG_TWIHS2_WPSR (*(__I uint32_t*)0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */ + #define REG_TWIHS2_VER (*(__I uint32_t*)0x400600FCU) /**< \brief (TWIHS2) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TWIHS2_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart0.h new file mode 100644 index 00000000..e3f2d2ad --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart0.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UART0_INSTANCE_ +#define _SAME70_UART0_INSTANCE_ + +/* ========== Register definition for UART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART0_CR (0x400E0800U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (0x400E0804U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (0x400E0814U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (0x400E0818U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (0x400E081CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_CMPR (0x400E0824U) /**< \brief (UART0) Comparison Register */ + #define REG_UART0_WPMR (0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */ + #define REG_UART0_VERSION (0x400E08FCU) /**< \brief (UART0) Version Register */ +#else + #define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< \brief (UART0) Comparison Register */ + #define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */ + #define REG_UART0_VERSION (*(__I uint32_t*)0x400E08FCU) /**< \brief (UART0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UART0_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart1.h new file mode 100644 index 00000000..b1c2be7c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart1.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UART1_INSTANCE_ +#define _SAME70_UART1_INSTANCE_ + +/* ========== Register definition for UART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART1_CR (0x400E0A00U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (0x400E0A04U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (0x400E0A14U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (0x400E0A18U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_CMPR (0x400E0A24U) /**< \brief (UART1) Comparison Register */ + #define REG_UART1_WPMR (0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */ + #define REG_UART1_VERSION (0x400E0AFCU) /**< \brief (UART1) Version Register */ +#else + #define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< \brief (UART1) Comparison Register */ + #define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */ + #define REG_UART1_VERSION (*(__I uint32_t*)0x400E0AFCU) /**< \brief (UART1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UART1_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart2.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart2.h new file mode 100644 index 00000000..70fefd05 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart2.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UART2_INSTANCE_ +#define _SAME70_UART2_INSTANCE_ + +/* ========== Register definition for UART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART2_CR (0x400E1A00U) /**< \brief (UART2) Control Register */ + #define REG_UART2_MR (0x400E1A04U) /**< \brief (UART2) Mode Register */ + #define REG_UART2_IER (0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */ + #define REG_UART2_IDR (0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */ + #define REG_UART2_IMR (0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */ + #define REG_UART2_SR (0x400E1A14U) /**< \brief (UART2) Status Register */ + #define REG_UART2_RHR (0x400E1A18U) /**< \brief (UART2) Receive Holding Register */ + #define REG_UART2_THR (0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */ + #define REG_UART2_BRGR (0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */ + #define REG_UART2_CMPR (0x400E1A24U) /**< \brief (UART2) Comparison Register */ + #define REG_UART2_WPMR (0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */ + #define REG_UART2_VERSION (0x400E1AFCU) /**< \brief (UART2) Version Register */ +#else + #define REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) /**< \brief (UART2) Control Register */ + #define REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) /**< \brief (UART2) Mode Register */ + #define REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */ + #define REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */ + #define REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */ + #define REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) /**< \brief (UART2) Status Register */ + #define REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) /**< \brief (UART2) Receive Holding Register */ + #define REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */ + #define REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */ + #define REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) /**< \brief (UART2) Comparison Register */ + #define REG_UART2_WPMR (*(__IO uint32_t*)0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */ + #define REG_UART2_VERSION (*(__I uint32_t*)0x400E1AFCU) /**< \brief (UART2) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UART2_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart3.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart3.h new file mode 100644 index 00000000..1f932b14 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart3.h @@ -0,0 +1,66 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70_UART3_INSTANCE_ +#define _SAME70_UART3_INSTANCE_ + +/* ========== Register definition for UART3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART3_CR (0x400E1C00U) /**< \brief (UART3) Control Register */ + #define REG_UART3_MR (0x400E1C04U) /**< \brief (UART3) Mode Register */ + #define REG_UART3_IER (0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */ + #define REG_UART3_IDR (0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */ + #define REG_UART3_IMR (0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */ + #define REG_UART3_SR (0x400E1C14U) /**< \brief (UART3) Status Register */ + #define REG_UART3_RHR (0x400E1C18U) /**< \brief (UART3) Receive Holding Register */ + #define REG_UART3_THR (0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */ + #define REG_UART3_BRGR (0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */ + #define REG_UART3_CMPR (0x400E1C24U) /**< \brief (UART3) Comparison Register */ + #define REG_UART3_WPMR (0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */ + #define REG_UART3_VERSION (0x400E1CFCU) /**< \brief (UART3) Version Register */ +#else + #define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) /**< \brief (UART3) Control Register */ + #define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) /**< \brief (UART3) Mode Register */ + #define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */ + #define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */ + #define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */ + #define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) /**< \brief (UART3) Status Register */ + #define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) /**< \brief (UART3) Receive Holding Register */ + #define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */ + #define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */ + #define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) /**< \brief (UART3) Comparison Register */ + #define REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */ + #define REG_UART3_VERSION (*(__I uint32_t*)0x400E1CFCU) /**< \brief (UART3) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UART3_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart4.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart4.h new file mode 100644 index 00000000..ba51c947 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart4.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UART4_INSTANCE_ +#define _SAME70_UART4_INSTANCE_ + +/* ========== Register definition for UART4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART4_CR (0x400E1E00U) /**< \brief (UART4) Control Register */ + #define REG_UART4_MR (0x400E1E04U) /**< \brief (UART4) Mode Register */ + #define REG_UART4_IER (0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */ + #define REG_UART4_IDR (0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */ + #define REG_UART4_IMR (0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */ + #define REG_UART4_SR (0x400E1E14U) /**< \brief (UART4) Status Register */ + #define REG_UART4_RHR (0x400E1E18U) /**< \brief (UART4) Receive Holding Register */ + #define REG_UART4_THR (0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */ + #define REG_UART4_BRGR (0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */ + #define REG_UART4_CMPR (0x400E1E24U) /**< \brief (UART4) Comparison Register */ + #define REG_UART4_WPMR (0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */ + #define REG_UART4_VERSION (0x400E1EFCU) /**< \brief (UART4) Version Register */ +#else + #define REG_UART4_CR (*(__O uint32_t*)0x400E1E00U) /**< \brief (UART4) Control Register */ + #define REG_UART4_MR (*(__IO uint32_t*)0x400E1E04U) /**< \brief (UART4) Mode Register */ + #define REG_UART4_IER (*(__O uint32_t*)0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */ + #define REG_UART4_IDR (*(__O uint32_t*)0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */ + #define REG_UART4_IMR (*(__I uint32_t*)0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */ + #define REG_UART4_SR (*(__I uint32_t*)0x400E1E14U) /**< \brief (UART4) Status Register */ + #define REG_UART4_RHR (*(__I uint32_t*)0x400E1E18U) /**< \brief (UART4) Receive Holding Register */ + #define REG_UART4_THR (*(__O uint32_t*)0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */ + #define REG_UART4_BRGR (*(__IO uint32_t*)0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */ + #define REG_UART4_CMPR (*(__IO uint32_t*)0x400E1E24U) /**< \brief (UART4) Comparison Register */ + #define REG_UART4_WPMR (*(__IO uint32_t*)0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */ + #define REG_UART4_VERSION (*(__I uint32_t*)0x400E1EFCU) /**< \brief (UART4) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UART4_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart0.h new file mode 100644 index 00000000..3f523ae0 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart0.h @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USART0_INSTANCE_ +#define _SAME70_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receive Holding Register */ + #define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ + #define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_FIDI (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ + #define REG_USART0_NER (0x40024044U) /**< \brief (USART0) Number of Errors Register */ + #define REG_USART0_IF (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ + #define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ + #define REG_USART0_LINMR (0x40024054U) /**< \brief (USART0) LIN Mode Register */ + #define REG_USART0_LINIR (0x40024058U) /**< \brief (USART0) LIN Identifier Register */ + #define REG_USART0_LINBRR (0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */ + #define REG_USART0_LONMR (0x40024060U) /**< \brief (USART0) LON Mode Register */ + #define REG_USART0_LONPR (0x40024064U) /**< \brief (USART0) LON Preamble Register */ + #define REG_USART0_LONDL (0x40024068U) /**< \brief (USART0) LON Data Length Register */ + #define REG_USART0_LONL2HDR (0x4002406CU) /**< \brief (USART0) LON L2HDR Register */ + #define REG_USART0_LONBL (0x40024070U) /**< \brief (USART0) LON Backlog Register */ + #define REG_USART0_LONB1TX (0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */ + #define REG_USART0_LONB1RX (0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */ + #define REG_USART0_LONPRIO (0x4002407CU) /**< \brief (USART0) LON Priority Register */ + #define REG_USART0_IDTTX (0x40024080U) /**< \brief (USART0) LON IDT Tx Register */ + #define REG_USART0_IDTRX (0x40024084U) /**< \brief (USART0) LON IDT Rx Register */ + #define REG_USART0_ICDIFF (0x40024088U) /**< \brief (USART0) IC DIFF Register */ + #define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ + #define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ + #define REG_USART0_VERSION (0x400240FCU) /**< \brief (USART0) Version Register */ +#else + #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receive Holding Register */ + #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ + #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_FIDI (*(__IO uint32_t*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ + #define REG_USART0_NER (*(__I uint32_t*)0x40024044U) /**< \brief (USART0) Number of Errors Register */ + #define REG_USART0_IF (*(__IO uint32_t*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ + #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ + #define REG_USART0_LINMR (*(__IO uint32_t*)0x40024054U) /**< \brief (USART0) LIN Mode Register */ + #define REG_USART0_LINIR (*(__IO uint32_t*)0x40024058U) /**< \brief (USART0) LIN Identifier Register */ + #define REG_USART0_LINBRR (*(__I uint32_t*)0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */ + #define REG_USART0_LONMR (*(__IO uint32_t*)0x40024060U) /**< \brief (USART0) LON Mode Register */ + #define REG_USART0_LONPR (*(__IO uint32_t*)0x40024064U) /**< \brief (USART0) LON Preamble Register */ + #define REG_USART0_LONDL (*(__IO uint32_t*)0x40024068U) /**< \brief (USART0) LON Data Length Register */ + #define REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< \brief (USART0) LON L2HDR Register */ + #define REG_USART0_LONBL (*(__I uint32_t*)0x40024070U) /**< \brief (USART0) LON Backlog Register */ + #define REG_USART0_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */ + #define REG_USART0_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */ + #define REG_USART0_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< \brief (USART0) LON Priority Register */ + #define REG_USART0_IDTTX (*(__IO uint32_t*)0x40024080U) /**< \brief (USART0) LON IDT Tx Register */ + #define REG_USART0_IDTRX (*(__IO uint32_t*)0x40024084U) /**< \brief (USART0) LON IDT Rx Register */ + #define REG_USART0_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< \brief (USART0) IC DIFF Register */ + #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ + #define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ + #define REG_USART0_VERSION (*(__I uint32_t*)0x400240FCU) /**< \brief (USART0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_USART0_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart1.h new file mode 100644 index 00000000..5b0fe493 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart1.h @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USART1_INSTANCE_ +#define _SAME70_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receive Holding Register */ + #define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmit Holding Register */ + #define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_FIDI (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ + #define REG_USART1_NER (0x40028044U) /**< \brief (USART1) Number of Errors Register */ + #define REG_USART1_IF (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ + #define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Configuration Register */ + #define REG_USART1_LINMR (0x40028054U) /**< \brief (USART1) LIN Mode Register */ + #define REG_USART1_LINIR (0x40028058U) /**< \brief (USART1) LIN Identifier Register */ + #define REG_USART1_LINBRR (0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */ + #define REG_USART1_LONMR (0x40028060U) /**< \brief (USART1) LON Mode Register */ + #define REG_USART1_LONPR (0x40028064U) /**< \brief (USART1) LON Preamble Register */ + #define REG_USART1_LONDL (0x40028068U) /**< \brief (USART1) LON Data Length Register */ + #define REG_USART1_LONL2HDR (0x4002806CU) /**< \brief (USART1) LON L2HDR Register */ + #define REG_USART1_LONBL (0x40028070U) /**< \brief (USART1) LON Backlog Register */ + #define REG_USART1_LONB1TX (0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */ + #define REG_USART1_LONB1RX (0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */ + #define REG_USART1_LONPRIO (0x4002807CU) /**< \brief (USART1) LON Priority Register */ + #define REG_USART1_IDTTX (0x40028080U) /**< \brief (USART1) LON IDT Tx Register */ + #define REG_USART1_IDTRX (0x40028084U) /**< \brief (USART1) LON IDT Rx Register */ + #define REG_USART1_ICDIFF (0x40028088U) /**< \brief (USART1) IC DIFF Register */ + #define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */ + #define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protection Status Register */ + #define REG_USART1_VERSION (0x400280FCU) /**< \brief (USART1) Version Register */ +#else + #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) /**< \brief (USART1) Receive Holding Register */ + #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) /**< \brief (USART1) Transmit Holding Register */ + #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_FIDI (*(__IO uint32_t*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ + #define REG_USART1_NER (*(__I uint32_t*)0x40028044U) /**< \brief (USART1) Number of Errors Register */ + #define REG_USART1_IF (*(__IO uint32_t*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ + #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Configuration Register */ + #define REG_USART1_LINMR (*(__IO uint32_t*)0x40028054U) /**< \brief (USART1) LIN Mode Register */ + #define REG_USART1_LINIR (*(__IO uint32_t*)0x40028058U) /**< \brief (USART1) LIN Identifier Register */ + #define REG_USART1_LINBRR (*(__I uint32_t*)0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */ + #define REG_USART1_LONMR (*(__IO uint32_t*)0x40028060U) /**< \brief (USART1) LON Mode Register */ + #define REG_USART1_LONPR (*(__IO uint32_t*)0x40028064U) /**< \brief (USART1) LON Preamble Register */ + #define REG_USART1_LONDL (*(__IO uint32_t*)0x40028068U) /**< \brief (USART1) LON Data Length Register */ + #define REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< \brief (USART1) LON L2HDR Register */ + #define REG_USART1_LONBL (*(__I uint32_t*)0x40028070U) /**< \brief (USART1) LON Backlog Register */ + #define REG_USART1_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */ + #define REG_USART1_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */ + #define REG_USART1_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< \brief (USART1) LON Priority Register */ + #define REG_USART1_IDTTX (*(__IO uint32_t*)0x40028080U) /**< \brief (USART1) LON IDT Tx Register */ + #define REG_USART1_IDTRX (*(__IO uint32_t*)0x40028084U) /**< \brief (USART1) LON IDT Rx Register */ + #define REG_USART1_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< \brief (USART1) IC DIFF Register */ + #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */ + #define REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protection Status Register */ + #define REG_USART1_VERSION (*(__I uint32_t*)0x400280FCU) /**< \brief (USART1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_USART1_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart2.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart2.h new file mode 100644 index 00000000..575c10c8 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart2.h @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USART2_INSTANCE_ +#define _SAME70_USART2_INSTANCE_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART2_CR (0x4002C000U) /**< \brief (USART2) Control Register */ + #define REG_USART2_MR (0x4002C004U) /**< \brief (USART2) Mode Register */ + #define REG_USART2_IER (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */ + #define REG_USART2_IDR (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */ + #define REG_USART2_IMR (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */ + #define REG_USART2_CSR (0x4002C014U) /**< \brief (USART2) Channel Status Register */ + #define REG_USART2_RHR (0x4002C018U) /**< \brief (USART2) Receive Holding Register */ + #define REG_USART2_THR (0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */ + #define REG_USART2_BRGR (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */ + #define REG_USART2_RTOR (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */ + #define REG_USART2_TTGR (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */ + #define REG_USART2_FIDI (0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */ + #define REG_USART2_NER (0x4002C044U) /**< \brief (USART2) Number of Errors Register */ + #define REG_USART2_IF (0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */ + #define REG_USART2_MAN (0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */ + #define REG_USART2_LINMR (0x4002C054U) /**< \brief (USART2) LIN Mode Register */ + #define REG_USART2_LINIR (0x4002C058U) /**< \brief (USART2) LIN Identifier Register */ + #define REG_USART2_LINBRR (0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */ + #define REG_USART2_LONMR (0x4002C060U) /**< \brief (USART2) LON Mode Register */ + #define REG_USART2_LONPR (0x4002C064U) /**< \brief (USART2) LON Preamble Register */ + #define REG_USART2_LONDL (0x4002C068U) /**< \brief (USART2) LON Data Length Register */ + #define REG_USART2_LONL2HDR (0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */ + #define REG_USART2_LONBL (0x4002C070U) /**< \brief (USART2) LON Backlog Register */ + #define REG_USART2_LONB1TX (0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */ + #define REG_USART2_LONB1RX (0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */ + #define REG_USART2_LONPRIO (0x4002C07CU) /**< \brief (USART2) LON Priority Register */ + #define REG_USART2_IDTTX (0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */ + #define REG_USART2_IDTRX (0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */ + #define REG_USART2_ICDIFF (0x4002C088U) /**< \brief (USART2) IC DIFF Register */ + #define REG_USART2_WPMR (0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */ + #define REG_USART2_WPSR (0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */ + #define REG_USART2_VERSION (0x4002C0FCU) /**< \brief (USART2) Version Register */ +#else + #define REG_USART2_CR (*(__O uint32_t*)0x4002C000U) /**< \brief (USART2) Control Register */ + #define REG_USART2_MR (*(__IO uint32_t*)0x4002C004U) /**< \brief (USART2) Mode Register */ + #define REG_USART2_IER (*(__O uint32_t*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */ + #define REG_USART2_IDR (*(__O uint32_t*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */ + #define REG_USART2_IMR (*(__I uint32_t*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */ + #define REG_USART2_CSR (*(__I uint32_t*)0x4002C014U) /**< \brief (USART2) Channel Status Register */ + #define REG_USART2_RHR (*(__I uint32_t*)0x4002C018U) /**< \brief (USART2) Receive Holding Register */ + #define REG_USART2_THR (*(__O uint32_t*)0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */ + #define REG_USART2_BRGR (*(__IO uint32_t*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */ + #define REG_USART2_RTOR (*(__IO uint32_t*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */ + #define REG_USART2_TTGR (*(__IO uint32_t*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */ + #define REG_USART2_FIDI (*(__IO uint32_t*)0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */ + #define REG_USART2_NER (*(__I uint32_t*)0x4002C044U) /**< \brief (USART2) Number of Errors Register */ + #define REG_USART2_IF (*(__IO uint32_t*)0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */ + #define REG_USART2_MAN (*(__IO uint32_t*)0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */ + #define REG_USART2_LINMR (*(__IO uint32_t*)0x4002C054U) /**< \brief (USART2) LIN Mode Register */ + #define REG_USART2_LINIR (*(__IO uint32_t*)0x4002C058U) /**< \brief (USART2) LIN Identifier Register */ + #define REG_USART2_LINBRR (*(__I uint32_t*)0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */ + #define REG_USART2_LONMR (*(__IO uint32_t*)0x4002C060U) /**< \brief (USART2) LON Mode Register */ + #define REG_USART2_LONPR (*(__IO uint32_t*)0x4002C064U) /**< \brief (USART2) LON Preamble Register */ + #define REG_USART2_LONDL (*(__IO uint32_t*)0x4002C068U) /**< \brief (USART2) LON Data Length Register */ + #define REG_USART2_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */ + #define REG_USART2_LONBL (*(__I uint32_t*)0x4002C070U) /**< \brief (USART2) LON Backlog Register */ + #define REG_USART2_LONB1TX (*(__IO uint32_t*)0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */ + #define REG_USART2_LONB1RX (*(__IO uint32_t*)0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */ + #define REG_USART2_LONPRIO (*(__IO uint32_t*)0x4002C07CU) /**< \brief (USART2) LON Priority Register */ + #define REG_USART2_IDTTX (*(__IO uint32_t*)0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */ + #define REG_USART2_IDTRX (*(__IO uint32_t*)0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */ + #define REG_USART2_ICDIFF (*(__IO uint32_t*)0x4002C088U) /**< \brief (USART2) IC DIFF Register */ + #define REG_USART2_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */ + #define REG_USART2_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */ + #define REG_USART2_VERSION (*(__I uint32_t*)0x4002C0FCU) /**< \brief (USART2) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_USART2_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h new file mode 100644 index 00000000..3ae80f03 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h @@ -0,0 +1,245 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USBHS_INSTANCE_ +#define _SAME70_USBHS_INSTANCE_ + +/* ========== Register definition for USBHS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USBHS_DEVCTRL (0x40038000U) /**< \brief (USBHS) Device General Control Register */ + #define REG_USBHS_DEVISR (0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */ + #define REG_USBHS_DEVICR (0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */ + #define REG_USBHS_DEVIFR (0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */ + #define REG_USBHS_DEVIMR (0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */ + #define REG_USBHS_DEVIDR (0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */ + #define REG_USBHS_DEVIER (0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */ + #define REG_USBHS_DEVEPT (0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */ + #define REG_USBHS_DEVFNUM (0x40038020U) /**< \brief (USBHS) Device Frame Number Register */ + #define REG_USBHS_DEVEPTCFG (0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */ + #define REG_USBHS_DEVEPTISR (0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */ + #define REG_USBHS_DEVEPTICR (0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */ + #define REG_USBHS_DEVEPTIFR (0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */ + #define REG_USBHS_DEVEPTIMR (0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */ + #define REG_USBHS_DEVEPTIER (0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */ + #define REG_USBHS_DEVEPTIDR (0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */ + #define REG_USBHS_DEVDMANXTDSC1 (0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_DEVDMAADDRESS1 (0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */ + #define REG_USBHS_DEVDMACONTROL1 (0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */ + #define REG_USBHS_DEVDMASTATUS1 (0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */ + #define REG_USBHS_DEVDMANXTDSC2 (0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_DEVDMAADDRESS2 (0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */ + #define REG_USBHS_DEVDMACONTROL2 (0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */ + #define REG_USBHS_DEVDMASTATUS2 (0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */ + #define REG_USBHS_DEVDMANXTDSC3 (0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_DEVDMAADDRESS3 (0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */ + #define REG_USBHS_DEVDMACONTROL3 (0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */ + #define REG_USBHS_DEVDMASTATUS3 (0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */ + #define REG_USBHS_DEVDMANXTDSC4 (0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_DEVDMAADDRESS4 (0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */ + #define REG_USBHS_DEVDMACONTROL4 (0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */ + #define REG_USBHS_DEVDMASTATUS4 (0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */ + #define REG_USBHS_DEVDMANXTDSC5 (0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_DEVDMAADDRESS5 (0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */ + #define REG_USBHS_DEVDMACONTROL5 (0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */ + #define REG_USBHS_DEVDMASTATUS5 (0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */ + #define REG_USBHS_DEVDMANXTDSC6 (0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_DEVDMAADDRESS6 (0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */ + #define REG_USBHS_DEVDMACONTROL6 (0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */ + #define REG_USBHS_DEVDMASTATUS6 (0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */ + #define REG_USBHS_DEVDMANXTDSC7 (0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_DEVDMAADDRESS7 (0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */ + #define REG_USBHS_DEVDMACONTROL7 (0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */ + #define REG_USBHS_DEVDMASTATUS7 (0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */ + #define REG_USBHS_HSTCTRL (0x40038400U) /**< \brief (USBHS) Host General Control Register */ + #define REG_USBHS_HSTISR (0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */ + #define REG_USBHS_HSTICR (0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */ + #define REG_USBHS_HSTIFR (0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */ + #define REG_USBHS_HSTIMR (0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */ + #define REG_USBHS_HSTIDR (0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */ + #define REG_USBHS_HSTIER (0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */ + #define REG_USBHS_HSTPIP (0x4003841CU) /**< \brief (USBHS) Host Pipe Register */ + #define REG_USBHS_HSTFNUM (0x40038420U) /**< \brief (USBHS) Host Frame Number Register */ + #define REG_USBHS_HSTADDR1 (0x40038424U) /**< \brief (USBHS) Host Address 1 Register */ + #define REG_USBHS_HSTADDR2 (0x40038428U) /**< \brief (USBHS) Host Address 2 Register */ + #define REG_USBHS_HSTADDR3 (0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */ + #define REG_USBHS_HSTPIPCFG (0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */ + #define REG_USBHS_HSTPIPISR (0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */ + #define REG_USBHS_HSTPIPICR (0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */ + #define REG_USBHS_HSTPIPIFR (0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */ + #define REG_USBHS_HSTPIPIMR (0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */ + #define REG_USBHS_HSTPIPIER (0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */ + #define REG_USBHS_HSTPIPIDR (0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */ + #define REG_USBHS_HSTPIPINRQ (0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */ + #define REG_USBHS_HSTPIPERR (0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */ + #define REG_USBHS_HSTDMANXTDSC1 (0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_HSTDMAADDRESS1 (0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */ + #define REG_USBHS_HSTDMACONTROL1 (0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */ + #define REG_USBHS_HSTDMASTATUS1 (0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */ + #define REG_USBHS_HSTDMANXTDSC2 (0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_HSTDMAADDRESS2 (0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */ + #define REG_USBHS_HSTDMACONTROL2 (0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */ + #define REG_USBHS_HSTDMASTATUS2 (0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */ + #define REG_USBHS_HSTDMANXTDSC3 (0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_HSTDMAADDRESS3 (0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */ + #define REG_USBHS_HSTDMACONTROL3 (0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */ + #define REG_USBHS_HSTDMASTATUS3 (0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */ + #define REG_USBHS_HSTDMANXTDSC4 (0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_HSTDMAADDRESS4 (0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */ + #define REG_USBHS_HSTDMACONTROL4 (0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */ + #define REG_USBHS_HSTDMASTATUS4 (0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */ + #define REG_USBHS_HSTDMANXTDSC5 (0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_HSTDMAADDRESS5 (0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */ + #define REG_USBHS_HSTDMACONTROL5 (0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */ + #define REG_USBHS_HSTDMASTATUS5 (0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */ + #define REG_USBHS_HSTDMANXTDSC6 (0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_HSTDMAADDRESS6 (0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */ + #define REG_USBHS_HSTDMACONTROL6 (0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */ + #define REG_USBHS_HSTDMASTATUS6 (0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */ + #define REG_USBHS_HSTDMANXTDSC7 (0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_HSTDMAADDRESS7 (0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */ + #define REG_USBHS_HSTDMACONTROL7 (0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */ + #define REG_USBHS_HSTDMASTATUS7 (0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */ + #define REG_USBHS_CTRL (0x40038800U) /**< \brief (USBHS) General Control Register */ + #define REG_USBHS_SR (0x40038804U) /**< \brief (USBHS) General Status Register */ + #define REG_USBHS_SCR (0x40038808U) /**< \brief (USBHS) General Status Clear Register */ + #define REG_USBHS_SFR (0x4003880CU) /**< \brief (USBHS) General Status Set Register */ + #define REG_USBHS_TSTA1 (0x40038810U) /**< \brief (USBHS) General Test A1 Register */ + #define REG_USBHS_TSTA2 (0x40038814U) /**< \brief (USBHS) General Test A2 Register */ + #define REG_USBHS_VERSION (0x40038818U) /**< \brief (USBHS) General Version Register */ + #define REG_USBHS_FSM (0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */ +#else + #define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< \brief (USBHS) Device General Control Register */ + #define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */ + #define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */ + #define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */ + #define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */ + #define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */ + #define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */ + #define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */ + #define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< \brief (USBHS) Device Frame Number Register */ + #define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */ + #define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */ + #define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */ + #define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */ + #define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */ + #define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */ + #define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */ + #define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */ + #define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */ + #define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */ + #define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */ + #define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */ + #define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */ + #define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */ + #define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */ + #define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */ + #define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */ + #define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */ + #define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */ + #define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */ + #define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */ + #define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */ + #define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */ + #define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */ + #define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */ + #define REG_USBHS_DEVDMANXTDSC7 (*(__IO uint32_t*)0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */ + #define REG_USBHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */ + #define REG_USBHS_DEVDMASTATUS7 (*(__IO uint32_t*)0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */ + #define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< \brief (USBHS) Host General Control Register */ + #define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */ + #define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */ + #define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */ + #define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */ + #define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */ + #define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */ + #define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< \brief (USBHS) Host Pipe Register */ + #define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< \brief (USBHS) Host Frame Number Register */ + #define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< \brief (USBHS) Host Address 1 Register */ + #define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< \brief (USBHS) Host Address 2 Register */ + #define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */ + #define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */ + #define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */ + #define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */ + #define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */ + #define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */ + #define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */ + #define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */ + #define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */ + #define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */ + #define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */ + #define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */ + #define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */ + #define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */ + #define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */ + #define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */ + #define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */ + #define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */ + #define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */ + #define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */ + #define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */ + #define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */ + #define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */ + #define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */ + #define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */ + #define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */ + #define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */ + #define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */ + #define REG_USBHS_HSTDMANXTDSC7 (*(__IO uint32_t*)0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */ + #define REG_USBHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */ + #define REG_USBHS_HSTDMASTATUS7 (*(__IO uint32_t*)0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */ + #define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< \brief (USBHS) General Control Register */ + #define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< \brief (USBHS) General Status Register */ + #define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< \brief (USBHS) General Status Clear Register */ + #define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< \brief (USBHS) General Status Set Register */ + #define REG_USBHS_TSTA1 (*(__IO uint32_t*)0x40038810U) /**< \brief (USBHS) General Test A1 Register */ + #define REG_USBHS_TSTA2 (*(__IO uint32_t*)0x40038814U) /**< \brief (USBHS) General Test A2 Register */ + #define REG_USBHS_VERSION (*(__I uint32_t*)0x40038818U) /**< \brief (USBHS) General Version Register */ + #define REG_USBHS_FSM (*(__I uint32_t*)0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_USBHS_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/utmi.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/utmi.h new file mode 100644 index 00000000..0b4a61ee --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/utmi.h @@ -0,0 +1,47 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UTMI_INSTANCE_ +#define _SAME70_UTMI_INSTANCE_ + +/* ========== Register definition for UTMI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UTMI_OHCIICR (0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */ + #define REG_UTMI_CKTRIM (0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */ +#else + #define REG_UTMI_OHCIICR (*(__IO uint32_t*)0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */ + #define REG_UTMI_CKTRIM (*(__IO uint32_t*)0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UTMI_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/wdt.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/wdt.h new file mode 100644 index 00000000..d92669ca --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/wdt.h @@ -0,0 +1,49 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_WDT_INSTANCE_ +#define _SAME70_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_WDT_CR (0x400E1850U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (0x400E1854U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (0x400E1858U) /**< \brief (WDT) Status Register */ +#else + #define REG_WDT_CR (*(__O uint32_t*)0x400E1850U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (*(__IO uint32_t*)0x400E1854U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (*(__I uint32_t*)0x400E1858U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_WDT_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/xdmac.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/xdmac.h new file mode 100644 index 00000000..535e6bc3 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/xdmac.h @@ -0,0 +1,751 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_XDMAC_INSTANCE_ +#define _SAME70_XDMAC_INSTANCE_ + +/* ========== Register definition for XDMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_XDMAC_GTYPE (0x40078000U) /**< \brief (XDMAC) Global Type Register */ + #define REG_XDMAC_GCFG (0x40078004U) /**< \brief (XDMAC) Global Configuration Register */ + #define REG_XDMAC_GWAC (0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */ + #define REG_XDMAC_GIE (0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */ + #define REG_XDMAC_GID (0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */ + #define REG_XDMAC_GIM (0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */ + #define REG_XDMAC_GIS (0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */ + #define REG_XDMAC_GE (0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */ + #define REG_XDMAC_GD (0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */ + #define REG_XDMAC_GS (0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */ + #define REG_XDMAC_GRS (0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */ + #define REG_XDMAC_GWS (0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */ + #define REG_XDMAC_GRWS (0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */ + #define REG_XDMAC_GRWR (0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */ + #define REG_XDMAC_GSWR (0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */ + #define REG_XDMAC_GSWS (0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */ + #define REG_XDMAC_GSWF (0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */ + #define REG_XDMAC_CIE0 (0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */ + #define REG_XDMAC_CID0 (0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */ + #define REG_XDMAC_CIM0 (0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */ + #define REG_XDMAC_CIS0 (0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */ + #define REG_XDMAC_CSA0 (0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */ + #define REG_XDMAC_CDA0 (0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */ + #define REG_XDMAC_CNDA0 (0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */ + #define REG_XDMAC_CNDC0 (0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */ + #define REG_XDMAC_CUBC0 (0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */ + #define REG_XDMAC_CBC0 (0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */ + #define REG_XDMAC_CC0 (0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */ + #define REG_XDMAC_CDS_MSP0 (0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */ + #define REG_XDMAC_CSUS0 (0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */ + #define REG_XDMAC_CDUS0 (0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */ + #define REG_XDMAC_CIE1 (0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */ + #define REG_XDMAC_CID1 (0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */ + #define REG_XDMAC_CIM1 (0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */ + #define REG_XDMAC_CIS1 (0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */ + #define REG_XDMAC_CSA1 (0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */ + #define REG_XDMAC_CDA1 (0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */ + #define REG_XDMAC_CNDA1 (0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */ + #define REG_XDMAC_CNDC1 (0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */ + #define REG_XDMAC_CUBC1 (0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */ + #define REG_XDMAC_CBC1 (0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */ + #define REG_XDMAC_CC1 (0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */ + #define REG_XDMAC_CDS_MSP1 (0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */ + #define REG_XDMAC_CSUS1 (0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */ + #define REG_XDMAC_CDUS1 (0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */ + #define REG_XDMAC_CIE2 (0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */ + #define REG_XDMAC_CID2 (0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */ + #define REG_XDMAC_CIM2 (0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */ + #define REG_XDMAC_CIS2 (0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */ + #define REG_XDMAC_CSA2 (0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */ + #define REG_XDMAC_CDA2 (0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */ + #define REG_XDMAC_CNDA2 (0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */ + #define REG_XDMAC_CNDC2 (0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */ + #define REG_XDMAC_CUBC2 (0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */ + #define REG_XDMAC_CBC2 (0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */ + #define REG_XDMAC_CC2 (0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */ + #define REG_XDMAC_CDS_MSP2 (0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */ + #define REG_XDMAC_CSUS2 (0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */ + #define REG_XDMAC_CDUS2 (0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */ + #define REG_XDMAC_CIE3 (0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */ + #define REG_XDMAC_CID3 (0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */ + #define REG_XDMAC_CIM3 (0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */ + #define REG_XDMAC_CIS3 (0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */ + #define REG_XDMAC_CSA3 (0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */ + #define REG_XDMAC_CDA3 (0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */ + #define REG_XDMAC_CNDA3 (0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */ + #define REG_XDMAC_CNDC3 (0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */ + #define REG_XDMAC_CUBC3 (0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */ + #define REG_XDMAC_CBC3 (0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */ + #define REG_XDMAC_CC3 (0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */ + #define REG_XDMAC_CDS_MSP3 (0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */ + #define REG_XDMAC_CSUS3 (0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */ + #define REG_XDMAC_CDUS3 (0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */ + #define REG_XDMAC_CIE4 (0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */ + #define REG_XDMAC_CID4 (0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */ + #define REG_XDMAC_CIM4 (0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */ + #define REG_XDMAC_CIS4 (0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */ + #define REG_XDMAC_CSA4 (0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */ + #define REG_XDMAC_CDA4 (0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */ + #define REG_XDMAC_CNDA4 (0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */ + #define REG_XDMAC_CNDC4 (0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */ + #define REG_XDMAC_CUBC4 (0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */ + #define REG_XDMAC_CBC4 (0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */ + #define REG_XDMAC_CC4 (0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */ + #define REG_XDMAC_CDS_MSP4 (0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */ + #define REG_XDMAC_CSUS4 (0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */ + #define REG_XDMAC_CDUS4 (0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */ + #define REG_XDMAC_CIE5 (0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */ + #define REG_XDMAC_CID5 (0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */ + #define REG_XDMAC_CIM5 (0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */ + #define REG_XDMAC_CIS5 (0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */ + #define REG_XDMAC_CSA5 (0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */ + #define REG_XDMAC_CDA5 (0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */ + #define REG_XDMAC_CNDA5 (0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */ + #define REG_XDMAC_CNDC5 (0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */ + #define REG_XDMAC_CUBC5 (0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */ + #define REG_XDMAC_CBC5 (0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */ + #define REG_XDMAC_CC5 (0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */ + #define REG_XDMAC_CDS_MSP5 (0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */ + #define REG_XDMAC_CSUS5 (0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */ + #define REG_XDMAC_CDUS5 (0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */ + #define REG_XDMAC_CIE6 (0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */ + #define REG_XDMAC_CID6 (0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */ + #define REG_XDMAC_CIM6 (0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */ + #define REG_XDMAC_CIS6 (0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */ + #define REG_XDMAC_CSA6 (0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */ + #define REG_XDMAC_CDA6 (0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */ + #define REG_XDMAC_CNDA6 (0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */ + #define REG_XDMAC_CNDC6 (0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */ + #define REG_XDMAC_CUBC6 (0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */ + #define REG_XDMAC_CBC6 (0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */ + #define REG_XDMAC_CC6 (0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */ + #define REG_XDMAC_CDS_MSP6 (0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */ + #define REG_XDMAC_CSUS6 (0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */ + #define REG_XDMAC_CDUS6 (0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */ + #define REG_XDMAC_CIE7 (0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */ + #define REG_XDMAC_CID7 (0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */ + #define REG_XDMAC_CIM7 (0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */ + #define REG_XDMAC_CIS7 (0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */ + #define REG_XDMAC_CSA7 (0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */ + #define REG_XDMAC_CDA7 (0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */ + #define REG_XDMAC_CNDA7 (0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */ + #define REG_XDMAC_CNDC7 (0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */ + #define REG_XDMAC_CUBC7 (0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */ + #define REG_XDMAC_CBC7 (0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */ + #define REG_XDMAC_CC7 (0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */ + #define REG_XDMAC_CDS_MSP7 (0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */ + #define REG_XDMAC_CSUS7 (0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */ + #define REG_XDMAC_CDUS7 (0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */ + #define REG_XDMAC_CIE8 (0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */ + #define REG_XDMAC_CID8 (0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */ + #define REG_XDMAC_CIM8 (0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */ + #define REG_XDMAC_CIS8 (0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */ + #define REG_XDMAC_CSA8 (0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */ + #define REG_XDMAC_CDA8 (0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */ + #define REG_XDMAC_CNDA8 (0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */ + #define REG_XDMAC_CNDC8 (0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */ + #define REG_XDMAC_CUBC8 (0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */ + #define REG_XDMAC_CBC8 (0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */ + #define REG_XDMAC_CC8 (0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */ + #define REG_XDMAC_CDS_MSP8 (0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */ + #define REG_XDMAC_CSUS8 (0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */ + #define REG_XDMAC_CDUS8 (0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */ + #define REG_XDMAC_CIE9 (0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */ + #define REG_XDMAC_CID9 (0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */ + #define REG_XDMAC_CIM9 (0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */ + #define REG_XDMAC_CIS9 (0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */ + #define REG_XDMAC_CSA9 (0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */ + #define REG_XDMAC_CDA9 (0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */ + #define REG_XDMAC_CNDA9 (0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */ + #define REG_XDMAC_CNDC9 (0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */ + #define REG_XDMAC_CUBC9 (0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */ + #define REG_XDMAC_CBC9 (0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */ + #define REG_XDMAC_CC9 (0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */ + #define REG_XDMAC_CDS_MSP9 (0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */ + #define REG_XDMAC_CSUS9 (0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */ + #define REG_XDMAC_CDUS9 (0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */ + #define REG_XDMAC_CIE10 (0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */ + #define REG_XDMAC_CID10 (0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */ + #define REG_XDMAC_CIM10 (0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */ + #define REG_XDMAC_CIS10 (0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */ + #define REG_XDMAC_CSA10 (0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */ + #define REG_XDMAC_CDA10 (0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */ + #define REG_XDMAC_CNDA10 (0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */ + #define REG_XDMAC_CNDC10 (0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */ + #define REG_XDMAC_CUBC10 (0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */ + #define REG_XDMAC_CBC10 (0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */ + #define REG_XDMAC_CC10 (0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */ + #define REG_XDMAC_CDS_MSP10 (0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */ + #define REG_XDMAC_CSUS10 (0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */ + #define REG_XDMAC_CDUS10 (0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */ + #define REG_XDMAC_CIE11 (0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */ + #define REG_XDMAC_CID11 (0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */ + #define REG_XDMAC_CIM11 (0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */ + #define REG_XDMAC_CIS11 (0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */ + #define REG_XDMAC_CSA11 (0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */ + #define REG_XDMAC_CDA11 (0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */ + #define REG_XDMAC_CNDA11 (0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */ + #define REG_XDMAC_CNDC11 (0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */ + #define REG_XDMAC_CUBC11 (0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */ + #define REG_XDMAC_CBC11 (0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */ + #define REG_XDMAC_CC11 (0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */ + #define REG_XDMAC_CDS_MSP11 (0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */ + #define REG_XDMAC_CSUS11 (0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */ + #define REG_XDMAC_CDUS11 (0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */ + #define REG_XDMAC_CIE12 (0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */ + #define REG_XDMAC_CID12 (0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */ + #define REG_XDMAC_CIM12 (0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */ + #define REG_XDMAC_CIS12 (0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */ + #define REG_XDMAC_CSA12 (0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */ + #define REG_XDMAC_CDA12 (0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */ + #define REG_XDMAC_CNDA12 (0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */ + #define REG_XDMAC_CNDC12 (0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */ + #define REG_XDMAC_CUBC12 (0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */ + #define REG_XDMAC_CBC12 (0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */ + #define REG_XDMAC_CC12 (0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */ + #define REG_XDMAC_CDS_MSP12 (0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */ + #define REG_XDMAC_CSUS12 (0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */ + #define REG_XDMAC_CDUS12 (0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */ + #define REG_XDMAC_CIE13 (0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */ + #define REG_XDMAC_CID13 (0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */ + #define REG_XDMAC_CIM13 (0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */ + #define REG_XDMAC_CIS13 (0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */ + #define REG_XDMAC_CSA13 (0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */ + #define REG_XDMAC_CDA13 (0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */ + #define REG_XDMAC_CNDA13 (0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */ + #define REG_XDMAC_CNDC13 (0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */ + #define REG_XDMAC_CUBC13 (0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */ + #define REG_XDMAC_CBC13 (0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */ + #define REG_XDMAC_CC13 (0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */ + #define REG_XDMAC_CDS_MSP13 (0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */ + #define REG_XDMAC_CSUS13 (0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */ + #define REG_XDMAC_CDUS13 (0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */ + #define REG_XDMAC_CIE14 (0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */ + #define REG_XDMAC_CID14 (0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */ + #define REG_XDMAC_CIM14 (0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */ + #define REG_XDMAC_CIS14 (0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */ + #define REG_XDMAC_CSA14 (0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */ + #define REG_XDMAC_CDA14 (0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */ + #define REG_XDMAC_CNDA14 (0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */ + #define REG_XDMAC_CNDC14 (0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */ + #define REG_XDMAC_CUBC14 (0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */ + #define REG_XDMAC_CBC14 (0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */ + #define REG_XDMAC_CC14 (0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */ + #define REG_XDMAC_CDS_MSP14 (0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */ + #define REG_XDMAC_CSUS14 (0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */ + #define REG_XDMAC_CDUS14 (0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */ + #define REG_XDMAC_CIE15 (0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */ + #define REG_XDMAC_CID15 (0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */ + #define REG_XDMAC_CIM15 (0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */ + #define REG_XDMAC_CIS15 (0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */ + #define REG_XDMAC_CSA15 (0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */ + #define REG_XDMAC_CDA15 (0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */ + #define REG_XDMAC_CNDA15 (0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */ + #define REG_XDMAC_CNDC15 (0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */ + #define REG_XDMAC_CUBC15 (0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */ + #define REG_XDMAC_CBC15 (0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */ + #define REG_XDMAC_CC15 (0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */ + #define REG_XDMAC_CDS_MSP15 (0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */ + #define REG_XDMAC_CSUS15 (0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */ + #define REG_XDMAC_CDUS15 (0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */ + #define REG_XDMAC_CIE16 (0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */ + #define REG_XDMAC_CID16 (0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */ + #define REG_XDMAC_CIM16 (0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */ + #define REG_XDMAC_CIS16 (0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */ + #define REG_XDMAC_CSA16 (0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */ + #define REG_XDMAC_CDA16 (0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */ + #define REG_XDMAC_CNDA16 (0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */ + #define REG_XDMAC_CNDC16 (0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */ + #define REG_XDMAC_CUBC16 (0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */ + #define REG_XDMAC_CBC16 (0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */ + #define REG_XDMAC_CC16 (0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */ + #define REG_XDMAC_CDS_MSP16 (0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */ + #define REG_XDMAC_CSUS16 (0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */ + #define REG_XDMAC_CDUS16 (0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */ + #define REG_XDMAC_CIE17 (0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */ + #define REG_XDMAC_CID17 (0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */ + #define REG_XDMAC_CIM17 (0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */ + #define REG_XDMAC_CIS17 (0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */ + #define REG_XDMAC_CSA17 (0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */ + #define REG_XDMAC_CDA17 (0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */ + #define REG_XDMAC_CNDA17 (0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */ + #define REG_XDMAC_CNDC17 (0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */ + #define REG_XDMAC_CUBC17 (0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */ + #define REG_XDMAC_CBC17 (0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */ + #define REG_XDMAC_CC17 (0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */ + #define REG_XDMAC_CDS_MSP17 (0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */ + #define REG_XDMAC_CSUS17 (0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */ + #define REG_XDMAC_CDUS17 (0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */ + #define REG_XDMAC_CIE18 (0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */ + #define REG_XDMAC_CID18 (0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */ + #define REG_XDMAC_CIM18 (0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */ + #define REG_XDMAC_CIS18 (0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */ + #define REG_XDMAC_CSA18 (0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */ + #define REG_XDMAC_CDA18 (0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */ + #define REG_XDMAC_CNDA18 (0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */ + #define REG_XDMAC_CNDC18 (0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */ + #define REG_XDMAC_CUBC18 (0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */ + #define REG_XDMAC_CBC18 (0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */ + #define REG_XDMAC_CC18 (0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */ + #define REG_XDMAC_CDS_MSP18 (0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */ + #define REG_XDMAC_CSUS18 (0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */ + #define REG_XDMAC_CDUS18 (0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */ + #define REG_XDMAC_CIE19 (0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */ + #define REG_XDMAC_CID19 (0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */ + #define REG_XDMAC_CIM19 (0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */ + #define REG_XDMAC_CIS19 (0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */ + #define REG_XDMAC_CSA19 (0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */ + #define REG_XDMAC_CDA19 (0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */ + #define REG_XDMAC_CNDA19 (0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */ + #define REG_XDMAC_CNDC19 (0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */ + #define REG_XDMAC_CUBC19 (0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */ + #define REG_XDMAC_CBC19 (0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */ + #define REG_XDMAC_CC19 (0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */ + #define REG_XDMAC_CDS_MSP19 (0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */ + #define REG_XDMAC_CSUS19 (0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */ + #define REG_XDMAC_CDUS19 (0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */ + #define REG_XDMAC_CIE20 (0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */ + #define REG_XDMAC_CID20 (0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */ + #define REG_XDMAC_CIM20 (0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */ + #define REG_XDMAC_CIS20 (0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */ + #define REG_XDMAC_CSA20 (0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */ + #define REG_XDMAC_CDA20 (0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */ + #define REG_XDMAC_CNDA20 (0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */ + #define REG_XDMAC_CNDC20 (0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */ + #define REG_XDMAC_CUBC20 (0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */ + #define REG_XDMAC_CBC20 (0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */ + #define REG_XDMAC_CC20 (0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */ + #define REG_XDMAC_CDS_MSP20 (0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */ + #define REG_XDMAC_CSUS20 (0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */ + #define REG_XDMAC_CDUS20 (0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */ + #define REG_XDMAC_CIE21 (0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */ + #define REG_XDMAC_CID21 (0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */ + #define REG_XDMAC_CIM21 (0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */ + #define REG_XDMAC_CIS21 (0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */ + #define REG_XDMAC_CSA21 (0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */ + #define REG_XDMAC_CDA21 (0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */ + #define REG_XDMAC_CNDA21 (0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */ + #define REG_XDMAC_CNDC21 (0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */ + #define REG_XDMAC_CUBC21 (0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */ + #define REG_XDMAC_CBC21 (0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */ + #define REG_XDMAC_CC21 (0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */ + #define REG_XDMAC_CDS_MSP21 (0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */ + #define REG_XDMAC_CSUS21 (0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */ + #define REG_XDMAC_CDUS21 (0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */ + #define REG_XDMAC_CIE22 (0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */ + #define REG_XDMAC_CID22 (0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */ + #define REG_XDMAC_CIM22 (0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */ + #define REG_XDMAC_CIS22 (0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */ + #define REG_XDMAC_CSA22 (0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */ + #define REG_XDMAC_CDA22 (0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */ + #define REG_XDMAC_CNDA22 (0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */ + #define REG_XDMAC_CNDC22 (0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */ + #define REG_XDMAC_CUBC22 (0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */ + #define REG_XDMAC_CBC22 (0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */ + #define REG_XDMAC_CC22 (0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */ + #define REG_XDMAC_CDS_MSP22 (0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */ + #define REG_XDMAC_CSUS22 (0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */ + #define REG_XDMAC_CDUS22 (0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */ + #define REG_XDMAC_CIE23 (0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */ + #define REG_XDMAC_CID23 (0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */ + #define REG_XDMAC_CIM23 (0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */ + #define REG_XDMAC_CIS23 (0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */ + #define REG_XDMAC_CSA23 (0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */ + #define REG_XDMAC_CDA23 (0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */ + #define REG_XDMAC_CNDA23 (0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */ + #define REG_XDMAC_CNDC23 (0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */ + #define REG_XDMAC_CUBC23 (0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */ + #define REG_XDMAC_CBC23 (0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */ + #define REG_XDMAC_CC23 (0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */ + #define REG_XDMAC_CDS_MSP23 (0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */ + #define REG_XDMAC_CSUS23 (0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */ + #define REG_XDMAC_CDUS23 (0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */ + #define REG_XDMAC_VERSION (0x40078FFCU) /**< \brief (XDMAC) XDMAC Version Register */ +#else + #define REG_XDMAC_GTYPE (*(__I uint32_t*)0x40078000U) /**< \brief (XDMAC) Global Type Register */ + #define REG_XDMAC_GCFG (*(__IO uint32_t*)0x40078004U) /**< \brief (XDMAC) Global Configuration Register */ + #define REG_XDMAC_GWAC (*(__I uint32_t*)0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */ + #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */ + #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */ + #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */ + #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */ + #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */ + #define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */ + #define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */ + #define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */ + #define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */ + #define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */ + #define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */ + #define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */ + #define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */ + #define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */ + #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */ + #define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */ + #define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */ + #define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */ + #define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */ + #define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */ + #define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */ + #define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */ + #define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */ + #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */ + #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */ + #define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */ + #define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */ + #define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */ + #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */ + #define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */ + #define REG_XDMAC_CIM1 (*(__I uint32_t*)0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */ + #define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */ + #define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */ + #define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */ + #define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */ + #define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */ + #define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */ + #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */ + #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */ + #define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */ + #define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */ + #define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */ + #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */ + #define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */ + #define REG_XDMAC_CIM2 (*(__I uint32_t*)0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */ + #define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */ + #define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */ + #define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */ + #define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */ + #define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */ + #define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */ + #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */ + #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */ + #define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */ + #define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */ + #define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */ + #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */ + #define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */ + #define REG_XDMAC_CIM3 (*(__I uint32_t*)0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */ + #define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */ + #define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */ + #define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */ + #define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */ + #define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */ + #define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */ + #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */ + #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */ + #define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */ + #define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */ + #define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */ + #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */ + #define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */ + #define REG_XDMAC_CIM4 (*(__I uint32_t*)0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */ + #define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */ + #define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */ + #define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */ + #define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */ + #define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */ + #define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */ + #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */ + #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */ + #define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */ + #define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */ + #define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */ + #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */ + #define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */ + #define REG_XDMAC_CIM5 (*(__I uint32_t*)0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */ + #define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */ + #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */ + #define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */ + #define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */ + #define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */ + #define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */ + #define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */ + #define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */ + #define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */ + #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */ + #define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */ + #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */ + #define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */ + #define REG_XDMAC_CIM6 (*(__I uint32_t*)0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */ + #define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */ + #define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */ + #define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */ + #define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */ + #define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */ + #define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */ + #define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */ + #define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */ + #define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */ + #define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */ + #define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */ + #define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */ + #define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */ + #define REG_XDMAC_CIM7 (*(__I uint32_t*)0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */ + #define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */ + #define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */ + #define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */ + #define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */ + #define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */ + #define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */ + #define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */ + #define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */ + #define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */ + #define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */ + #define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */ + #define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */ + #define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */ + #define REG_XDMAC_CIM8 (*(__I uint32_t*)0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */ + #define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */ + #define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */ + #define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */ + #define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */ + #define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */ + #define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */ + #define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */ + #define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */ + #define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */ + #define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */ + #define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */ + #define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */ + #define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */ + #define REG_XDMAC_CIM9 (*(__I uint32_t*)0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */ + #define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */ + #define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */ + #define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */ + #define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */ + #define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */ + #define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */ + #define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */ + #define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */ + #define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */ + #define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */ + #define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */ + #define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */ + #define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */ + #define REG_XDMAC_CIM10 (*(__I uint32_t*)0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */ + #define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */ + #define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */ + #define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */ + #define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */ + #define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */ + #define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */ + #define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */ + #define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */ + #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */ + #define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */ + #define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */ + #define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */ + #define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */ + #define REG_XDMAC_CIM11 (*(__I uint32_t*)0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */ + #define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */ + #define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */ + #define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */ + #define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */ + #define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */ + #define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */ + #define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */ + #define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */ + #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */ + #define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */ + #define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */ + #define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */ + #define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */ + #define REG_XDMAC_CIM12 (*(__I uint32_t*)0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */ + #define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */ + #define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */ + #define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */ + #define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */ + #define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */ + #define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */ + #define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */ + #define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */ + #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */ + #define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */ + #define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */ + #define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */ + #define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */ + #define REG_XDMAC_CIM13 (*(__I uint32_t*)0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */ + #define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */ + #define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */ + #define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */ + #define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */ + #define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */ + #define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */ + #define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */ + #define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */ + #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */ + #define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */ + #define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */ + #define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */ + #define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */ + #define REG_XDMAC_CIM14 (*(__I uint32_t*)0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */ + #define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */ + #define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */ + #define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */ + #define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */ + #define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */ + #define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */ + #define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */ + #define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */ + #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */ + #define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */ + #define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */ + #define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */ + #define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */ + #define REG_XDMAC_CIM15 (*(__I uint32_t*)0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */ + #define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */ + #define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */ + #define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */ + #define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */ + #define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */ + #define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */ + #define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */ + #define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */ + #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */ + #define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */ + #define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */ + #define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */ + #define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */ + #define REG_XDMAC_CIM16 (*(__I uint32_t*)0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */ + #define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */ + #define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */ + #define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */ + #define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */ + #define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */ + #define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */ + #define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */ + #define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */ + #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */ + #define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */ + #define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */ + #define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */ + #define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */ + #define REG_XDMAC_CIM17 (*(__I uint32_t*)0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */ + #define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */ + #define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */ + #define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */ + #define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */ + #define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */ + #define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */ + #define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */ + #define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */ + #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */ + #define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */ + #define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */ + #define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */ + #define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */ + #define REG_XDMAC_CIM18 (*(__I uint32_t*)0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */ + #define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */ + #define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */ + #define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */ + #define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */ + #define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */ + #define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */ + #define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */ + #define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */ + #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */ + #define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */ + #define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */ + #define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */ + #define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */ + #define REG_XDMAC_CIM19 (*(__I uint32_t*)0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */ + #define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */ + #define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */ + #define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */ + #define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */ + #define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */ + #define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */ + #define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */ + #define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */ + #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */ + #define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */ + #define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */ + #define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */ + #define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */ + #define REG_XDMAC_CIM20 (*(__I uint32_t*)0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */ + #define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */ + #define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */ + #define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */ + #define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */ + #define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */ + #define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */ + #define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */ + #define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */ + #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */ + #define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */ + #define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */ + #define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */ + #define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */ + #define REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */ + #define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */ + #define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */ + #define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */ + #define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */ + #define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */ + #define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */ + #define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */ + #define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */ + #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */ + #define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */ + #define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */ + #define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */ + #define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */ + #define REG_XDMAC_CIM22 (*(__I uint32_t*)0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */ + #define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */ + #define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */ + #define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */ + #define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */ + #define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */ + #define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */ + #define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */ + #define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */ + #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */ + #define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */ + #define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */ + #define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */ + #define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */ + #define REG_XDMAC_CIM23 (*(__I uint32_t*)0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */ + #define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */ + #define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */ + #define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */ + #define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */ + #define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */ + #define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */ + #define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */ + #define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */ + #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */ + #define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */ + #define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */ + #define REG_XDMAC_VERSION (*(__IO uint32_t*)0x40078FFCU) /**< \brief (XDMAC) XDMAC Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_XDMAC_INSTANCE_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j19.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j19.h new file mode 100644 index 00000000..4710fa85 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j19.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J19_PIO_ +#define _SAME70J19_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J19_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j19b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j19b.h new file mode 100644 index 00000000..5d40d1dd --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j19b.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J19B_PIO_ +#define _SAME70J19B_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J19B_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j20.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j20.h new file mode 100644 index 00000000..e15510c5 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j20.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J20_PIO_ +#define _SAME70J20_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J20_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j20b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j20b.h new file mode 100644 index 00000000..c3860b61 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j20b.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J20B_PIO_ +#define _SAME70J20B_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J20B_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j21.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j21.h new file mode 100644 index 00000000..ec9104a8 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j21.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J21_PIO_ +#define _SAME70J21_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J21_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j21b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j21b.h new file mode 100644 index 00000000..dfcead66 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70j21b.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J21B_PIO_ +#define _SAME70J21B_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J21B_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n19.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n19.h new file mode 100644 index 00000000..fe3589a1 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n19.h @@ -0,0 +1,489 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N19_PIO_ +#define _SAME70N19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N19_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n19b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n19b.h new file mode 100644 index 00000000..3fec5394 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n19b.h @@ -0,0 +1,495 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N19B_PIO_ +#define _SAME70N19B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N19B_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n20.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n20.h new file mode 100644 index 00000000..8ec046f4 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n20.h @@ -0,0 +1,489 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N20_PIO_ +#define _SAME70N20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N20_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n20b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n20b.h new file mode 100644 index 00000000..a488317d --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n20b.h @@ -0,0 +1,495 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N20B_PIO_ +#define _SAME70N20B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N20B_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n21.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n21.h new file mode 100644 index 00000000..1743056c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n21.h @@ -0,0 +1,489 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N21_PIO_ +#define _SAME70N21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N21_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n21b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n21b.h new file mode 100644 index 00000000..9c230da7 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70n21b.h @@ -0,0 +1,495 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N21B_PIO_ +#define _SAME70N21B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N21B_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q19.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q19.h new file mode 100644 index 00000000..6988dbe8 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q19.h @@ -0,0 +1,685 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q19_PIO_ +#define _SAME70Q19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q19_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q19b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q19b.h new file mode 100644 index 00000000..76320693 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q19b.h @@ -0,0 +1,697 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q19B_PIO_ +#define _SAME70Q19B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for I2SC1 peripheral ========== */ +#define PIO_PA20D_I2SC1_CK (1u << 20) /**< \brief I2sc1 signal: I2SC1_CK */ +#define PIO_PE2C_I2SC1_DI0 (1u << 2) /**< \brief I2sc1 signal: I2SC1_DI0 */ +#define PIO_PE1C_I2SC1_DO0 (1u << 1) /**< \brief I2sc1 signal: I2SC1_DO0 */ +#define PIO_PA19D_I2SC1_MCK (1u << 19) /**< \brief I2sc1 signal: I2SC1_MCK */ +#define PIO_PE0C_I2SC1_WS (1u << 0) /**< \brief I2sc1 signal: I2SC1_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q19B_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q20.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q20.h new file mode 100644 index 00000000..d4c304ea --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q20.h @@ -0,0 +1,685 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q20_PIO_ +#define _SAME70Q20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q20_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q20b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q20b.h new file mode 100644 index 00000000..8d86b238 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q20b.h @@ -0,0 +1,697 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q20B_PIO_ +#define _SAME70Q20B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for I2SC1 peripheral ========== */ +#define PIO_PA20D_I2SC1_CK (1u << 20) /**< \brief I2sc1 signal: I2SC1_CK */ +#define PIO_PE2C_I2SC1_DI0 (1u << 2) /**< \brief I2sc1 signal: I2SC1_DI0 */ +#define PIO_PE1C_I2SC1_DO0 (1u << 1) /**< \brief I2sc1 signal: I2SC1_DO0 */ +#define PIO_PA19D_I2SC1_MCK (1u << 19) /**< \brief I2sc1 signal: I2SC1_MCK */ +#define PIO_PE0C_I2SC1_WS (1u << 0) /**< \brief I2sc1 signal: I2SC1_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q20B_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q21.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q21.h new file mode 100644 index 00000000..9dec3f29 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q21.h @@ -0,0 +1,685 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q21_PIO_ +#define _SAME70Q21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q21_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q21b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q21b.h new file mode 100644 index 00000000..9512051f --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/pio/same70q21b.h @@ -0,0 +1,697 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q21B_PIO_ +#define _SAME70Q21B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for I2SC1 peripheral ========== */ +#define PIO_PA20D_I2SC1_CK (1u << 20) /**< \brief I2sc1 signal: I2SC1_CK */ +#define PIO_PE2C_I2SC1_DI0 (1u << 2) /**< \brief I2sc1 signal: I2SC1_DI0 */ +#define PIO_PE1C_I2SC1_DO0 (1u << 1) /**< \brief I2sc1 signal: I2SC1_DO0 */ +#define PIO_PA19D_I2SC1_MCK (1u << 19) /**< \brief I2sc1 signal: I2SC1_MCK */ +#define PIO_PE0C_I2SC1_WS (1u << 0) /**< \brief I2sc1 signal: I2SC1_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q21B_PIO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70.h new file mode 100644 index 00000000..de427fdf --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70.h @@ -0,0 +1,77 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70_ +#define _SAME70_ + +#if defined (__SAME70J19__) +#include "same70j19.h" +#elif defined (__SAME70J20__) +#include "same70j20.h" +#elif defined (__SAME70J21__) +#include "same70j21.h" +#elif defined (__SAME70N19__) +#include "same70n19.h" +#elif defined (__SAME70N20__) +#include "same70n20.h" +#elif defined (__SAME70N21__) +#include "same70n21.h" +#elif defined (__SAME70Q19__) +#include "same70q19.h" +#elif defined (__SAME70Q20__) +#include "same70q20.h" +#elif defined (__SAME70Q21__) +#include "same70q21.h" +#elif defined (__SAME70J19B__) +#include "same70j19b.h" +#elif defined (__SAME70J20B__) +#include "same70j20b.h" +#elif defined (__SAME70J21B__) +#include "same70j21b.h" +#elif defined (__SAME70N19B__) +#include "same70n19b.h" +#elif defined (__SAME70N20B__) +#include "same70n20b.h" +#elif defined (__SAME70N21B__) +#include "same70n21b.h" +#elif defined (__SAME70Q19B__) +#include "same70q19b.h" +#elif defined (__SAME70Q20B__) +#include "same70q20b.h" +#elif defined (__SAME70Q21B__) +#include "same70q21b.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAME70_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j19.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j19.h new file mode 100644 index 00000000..d1a2c2ed --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j19.h @@ -0,0 +1,611 @@ +/** + * \file + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J19_ +#define _SAME70J19_ + +/** \addtogroup SAME70J19_definitions SAME70J19 definitions + This file defines all structures and symbols for SAME70J19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J19 USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J19 Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J19 Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J19 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J19 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J19 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J19 Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J19 UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J19 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J19 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J19 Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J19 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J19 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J19 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J19 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J19 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70J19 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J19_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j19b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j19b.h new file mode 100644 index 00000000..72ea61aa --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j19b.h @@ -0,0 +1,617 @@ +/** + * \file + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J19B_ +#define _SAME70J19B_ + +/** \addtogroup SAME70J19B_definitions SAME70J19B definitions + This file defines all structures and symbols for SAME70J19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J19B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J19B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J19B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J19B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J19B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J19B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J19B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J19B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J19B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J19B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J19B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J19B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J19B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J19B USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J19B Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J19B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J19B Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J19B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J19B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J19B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J19B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J19B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J19B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J19B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J19B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J19B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J19B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J19B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J19B Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J19B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J19B Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J19B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J19B UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J19B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J19B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J19B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J19B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J19B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J19B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J19B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J19B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J19B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J19B Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J19B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J19B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J19B Floating Point Unit Registers (FPU) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J19B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J19B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J19B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J19B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J19B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J19B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J19B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J19B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J19B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70J19 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j19b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A01UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J19B_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j20.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j20.h new file mode 100644 index 00000000..17407173 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j20.h @@ -0,0 +1,613 @@ +/** + * \file + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J20_ +#define _SAME70J20_ + +/** \addtogroup SAME70J20_definitions SAME70J20 definitions + This file defines all structures and symbols for SAME70J20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J20 USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J20 Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J20 Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J20 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J20 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J20 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J20 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J20 Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J20 UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J20 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J20 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J20 Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J20 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J20 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J20 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J20 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J20 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70J20 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/acc.h" +#include "instance/dacc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J20_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j20b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j20b.h new file mode 100644 index 00000000..0578f4ca --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j20b.h @@ -0,0 +1,618 @@ +/** + * \file + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J20B_ +#define _SAME70J20B_ + +/** \addtogroup SAME70J20B_definitions SAME70J20B definitions + This file defines all structures and symbols for SAME70J20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J20B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J20B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J20B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J20B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J20B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J20B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J20B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J20B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J20B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J20B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J20B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J20B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J20B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J20B USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J20B Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J20B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J20B Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J20B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J20B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J20B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J20B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J20B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J20B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J20B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J20B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J20B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J20B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J20B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J20B Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J20B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J20B Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J20B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J20B UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J20B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J20B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J20B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J20B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J20B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J20B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J20B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J20B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J20B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J20B Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J20B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J20B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J20B Floating Point Unit Registers (FPU) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J20B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J20B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J20B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J20B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J20B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J20B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J20B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J20B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J20B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70J20 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/acc.h" +#include "instance/dacc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j20b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C01UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J20B_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j21.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j21.h new file mode 100644 index 00000000..9e727004 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j21.h @@ -0,0 +1,618 @@ +/** + * \file + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J21_ +#define _SAME70J21_ + +/** \addtogroup SAME70J21_definitions SAME70J21 definitions + This file defines all structures and symbols for SAME70J21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J20B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J20B USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J21 Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J21 Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J21 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J21 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J21 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J21 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J21 Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J21 UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J21 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J21 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J21 Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J21 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J21 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J21 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J21 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J21 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70J21 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/dacc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J21_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j21b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j21b.h new file mode 100644 index 00000000..4ea83a6d --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70j21b.h @@ -0,0 +1,625 @@ +/** + * \file + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J21B_ +#define _SAME70J21B_ + +/** \addtogroup SAME70J21B_definitions SAME70J21B definitions + This file defines all structures and symbols for SAME70J21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J21B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J21B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J21B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J21B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J21B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J21B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J21B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J21B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J21B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J21B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J21B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J21B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J20B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J20B USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J21B Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J21B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J21B Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J21B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J21B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J21B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J21B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J21B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J21B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J21B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J21B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J21B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J21B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J21B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J21B Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J21B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J21B Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J21B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J21B UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J21B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J21B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J21B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J21B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J21B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J21B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J21B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J21B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J21B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J21B Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J21B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J21B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J21B Floating Point Unit Registers (FPU) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J21B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J21B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J21B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J21B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J21B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J21B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J21B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J21B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J21B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70J21 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/dacc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j21b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E01UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J21B_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n19.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n19.h new file mode 100644 index 00000000..b0d613f8 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n19.h @@ -0,0 +1,657 @@ +/** + * \file + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70N19_ +#define _SAME70N19_ + +/** \addtogroup SAME70N19_definitions SAME70N19 definitions + This file defines all structures and symbols for SAME70N19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N19 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N19 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N19 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N19 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N19 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N19 Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N19 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N19 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N19 Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N19 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N19 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N19 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N19 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N19 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70N19 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N19_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n19b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n19b.h new file mode 100644 index 00000000..06eb1b51 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n19b.h @@ -0,0 +1,670 @@ +/** + * \file + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70N19B_ +#define _SAME70N19B_ + +/** \addtogroup SAME70N19B_definitions SAME70N19B definitions + This file defines all structures and symbols for SAME70N19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N19B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N19B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N19B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N19B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N19B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N19B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N19B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N19B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N19B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N19B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N19B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N19B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N19B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N19B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N19B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N19B Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N19B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N19B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N19B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N19B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N19B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N19B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N19B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N19B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N19B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N19B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N19B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N19B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N19B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N19B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N19B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N19B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N19B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N19B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N19B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N19B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N19B Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N19B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N19B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N19B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N19B UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N19B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N19B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N19B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N19B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N19B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N19B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N19B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N19B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N19B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N19B Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N19B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N19B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N19B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70N19B Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 71 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N19B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N19B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N19B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N19B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N19B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N19B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N19B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N19B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N19B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70N19 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n19b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A01UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N19B_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n20.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n20.h new file mode 100644 index 00000000..4d3e1b1c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n20.h @@ -0,0 +1,659 @@ +/** + * \file + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N20_ +#define _SAME70N20_ + +/** \addtogroup SAME70N20_definitions SAME70N20 definitions + This file defines all structures and symbols for SAME70N20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N20 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N20 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N20 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N20 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N20 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N20 Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N20 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N20 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N20 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N20 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N20 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N20 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N20 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N20 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70N20 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N20_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n20b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n20b.h new file mode 100644 index 00000000..e07d4d96 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n20b.h @@ -0,0 +1,672 @@ +/** + * \file + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N20B_ +#define _SAME70N20B_ + +/** \addtogroup SAME70N20B_definitions SAME70N20B definitions + This file defines all structures and symbols for SAME70N20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N20B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N20B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N20B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N20B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N20B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N20B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N20B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N20B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N20B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N20B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N20B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N20B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N20B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N20B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N20B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N20B Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N20B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N20B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N20B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N20B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N20B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N20B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N20B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N20B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N20B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N20B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N20B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N20B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N20B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N20B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N20B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N20B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N20B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N20B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N20B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N20B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N20B Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N20B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N20B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N20B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N20B UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N20B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N20B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N20B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N20B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N20B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N20B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N20B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N20B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N20B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N20B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N20B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N20B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N20B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70N20B Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N20B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N20B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N20B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N20B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N20B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N20B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N20B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N20B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N20B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70N20 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n20b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C01UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N20B_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n21.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n21.h new file mode 100644 index 00000000..f8fd282b --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n21.h @@ -0,0 +1,657 @@ +/** + * \file + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N21_ +#define _SAME70N21_ + +/** \addtogroup SAME70N21_definitions SAME70N21 definitions + This file defines all structures and symbols for SAME70N21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N21 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N21 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N21 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N21 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N21 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N21 Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N21 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N21 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N21 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N21 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N21 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N21 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N21 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N21 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70N21 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N21_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n21b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n21b.h new file mode 100644 index 00000000..bfc398b2 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70n21b.h @@ -0,0 +1,670 @@ +/** + * \file + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N21B_ +#define _SAME70N21B_ + +/** \addtogroup SAME70N21B_definitions SAME70N21B definitions + This file defines all structures and symbols for SAME70N21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N21B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N21B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N21B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N21B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N21B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N21B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N21B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N21B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N21B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N21B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N21B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N21B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N21B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N21B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N21B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N21B Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N21B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N21B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N21B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N21B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N21B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N21B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N21B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N21B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N21B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N21B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N21B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N21B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N21B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N21B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N21B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N21B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N21B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N21B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N21B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N21B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N21B Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N21B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N21B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N21B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N21B UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N21B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N21B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N21B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N21B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N21B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N21B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N21B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N21B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N21B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N21B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N21B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N21B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N21B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70N21B Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N21B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N21B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N21B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N21B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N21B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N21B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N21B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N21B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N21B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70N21 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n21b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E01UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N21B_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q19.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q19.h new file mode 100644 index 00000000..82aac3b2 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q19.h @@ -0,0 +1,715 @@ +/** + * \file + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70Q19_ +#define _SAME70Q19_ + +/** \addtogroup SAME70Q19_definitions SAME70Q19 definitions + This file defines all structures and symbols for SAME70Q19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q19 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q19 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q19 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q19 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q19 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q19 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q19 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q19 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q19 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q19 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q19 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q19 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q19 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q19 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q19 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q19 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q19 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q19 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q19 Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q19 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q19 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q19 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q19 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q19 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q19 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q19 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70Q19 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q19_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q19b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q19b.h new file mode 100644 index 00000000..b7bb92ae --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q19b.h @@ -0,0 +1,734 @@ +/** + * \file + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70Q19B_ +#define _SAME70Q19B_ + +/** \addtogroup SAME70Q19B_definitions SAME70Q19B definitions + This file defines all structures and symbols for SAME70Q19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q19B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q19B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q19B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q19B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q19B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q19B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q19B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q19B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q19B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q19B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q19B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q19B Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q19B Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q19B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q19B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q19B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q19B Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q19B Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q19B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q19B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q19B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q19B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q19B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q19B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q19B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q19B Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q19B Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q19B Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q19B Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q19B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q19B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q19B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q19B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q19B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q19B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q19B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q19B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q19B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q19B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q19B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q19B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q19B Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q19B Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q19B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q19B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q19B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q19B UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q19B Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q19B Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q19B Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q19B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q19B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q19B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q19B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q19B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q19B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q19B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q19B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q19B Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q19B SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q19B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q19B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q19B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q19B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70Q19B Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70, /**< 70 SAME70Q19B Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q19B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q19B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q19B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q19B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q19B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q19B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q19B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q19B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q19B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70Q19 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/i2sc1.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ +#define ID_I2SC1 (70) /**< \brief Inter-IC Sound controller (I2SC1) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 (0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 ((I2sc *)0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q19b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A01UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q19B_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q20.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q20.h new file mode 100644 index 00000000..cc1742b7 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q20.h @@ -0,0 +1,716 @@ +/** + * \file + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q20_ +#define _SAME70Q20_ + +/** \addtogroup SAME70Q20_definitions SAME70Q20 definitions + This file defines all structures and symbols for SAME70Q20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q20 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q20 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q20 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q20 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q20 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q20 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q20 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q20 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q20 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q20 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q20 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q20 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q20 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q20 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q20 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q20 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q20 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q20 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q20 Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q20 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q20 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q20 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q20 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q20 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q20 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q20 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70Q20 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C01UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q20_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q20b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q20b.h new file mode 100644 index 00000000..59e0e9e7 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q20b.h @@ -0,0 +1,735 @@ +/** + * \file + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q20B_ +#define _SAME70Q20B_ + +/** \addtogroup SAME70Q20B_definitions SAME70Q20B definitions + This file defines all structures and symbols for SAME70Q20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q20B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q20B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q20B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q20B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q20B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q20B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q20B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q20B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q20B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q20B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q20B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q20B Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q20B Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q20B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q20B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q20B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q20B Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q20B Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q20B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q20B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q20B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q20B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q20B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q20B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q20B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q20B Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q20B Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q20B Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q20B Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q20B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q20B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q20B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q20B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q20B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q20B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q20B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q20B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q20B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q20B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q20B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q20B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q20B Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q20B Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q20B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q20B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q20B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q20B UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q20B Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q20B Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q20B Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q20B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q20B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q20B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q20B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q20B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q20B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q20B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q20B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q20B Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q20B SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q20B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q20B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q20B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q20B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70Q20B Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70, /**< 70 SAME70Q20B Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q20B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q20B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q20B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q20B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q20B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q20B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q20B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q20B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q20B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70Q20 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/i2sc1.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ +#define ID_I2SC1 (70) /**< \brief Inter-IC Sound controller (I2SC1) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 (0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 ((I2sc *)0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q20b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C01UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q20B_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q21.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q21.h new file mode 100644 index 00000000..f9459965 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q21.h @@ -0,0 +1,716 @@ +/** + * \file + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q21_ +#define _SAME70Q21_ + +/** \addtogroup SAME70Q21_definitions SAME70Q21 definitions + This file defines all structures and symbols for SAME70Q21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q21 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q21 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q21 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q21 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q21 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q21 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q21 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q21 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q21 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q21 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q21 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q21 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q21 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q21 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q21 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q21 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q21 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q21 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q21 Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q21 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q21 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q21 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q21 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q21 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q21 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q21 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70Q21 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q21_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q21b.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q21b.h new file mode 100644 index 00000000..aee8699e --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/same70q21b.h @@ -0,0 +1,735 @@ +/** + * \file + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q21B_ +#define _SAME70Q21B_ + +/** \addtogroup SAME70Q21B_definitions SAME70Q21B definitions + This file defines all structures and symbols for SAME70Q21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q21B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q21B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q21B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q21B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q21B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q21B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q21B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q21B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q21B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q21B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q21B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q21B Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q21B Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q21B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q21B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q21B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q21B Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q21B Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q21B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q21B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q21B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q21B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q21B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q21B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q21B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q21B Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q21B Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q21B Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q21B Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q21B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q21B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q21B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q21B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q21B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q21B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q21B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q21B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q21B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q21B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q21B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q21B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q21B Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q21B Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q21B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q21B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q21B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q21B UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q21B Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q21B Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q21B Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q21B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q21B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q21B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q21B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q21B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q21B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q21B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q21B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q21B Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q21B SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q21B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q21B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q21B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q21B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70Q21B Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70, /**< 70 SAME70Q21B Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q21B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q21B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q21B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q21B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q21B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q21B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q21B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q21B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q21B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70Q21 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/i2sc1.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ +#define ID_I2SC1 (70) /**< \brief Inter-IC Sound controller (I2SC1) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 (0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 ((I2sc *)0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q21b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E01UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q21B_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/source/templates/gcc/startup_same70.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/source/templates/gcc/startup_same70.c new file mode 100644 index 00000000..e8b360cb --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/source/templates/gcc/startup_same70.c @@ -0,0 +1,432 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "same70.h" + +#if __FPU_USED /* CMSIS defined value to indicate usage of FPU */ +#include "fpu.h" +#endif + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_PIOC_INSTANCE_ +void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_PIOC_INSTANCE_ */ +#ifdef _SAME70_USART0_INSTANCE_ +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_USART0_INSTANCE_ */ +#ifdef _SAME70_USART1_INSTANCE_ +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_USART1_INSTANCE_ */ +#ifdef _SAME70_USART2_INSTANCE_ +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_USART2_INSTANCE_ */ +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_PIOE_INSTANCE_ +void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_PIOE_INSTANCE_ */ +#ifdef _SAME70_HSMCI_INSTANCE_ +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_HSMCI_INSTANCE_ */ +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_SPI0_INSTANCE_ +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_SPI0_INSTANCE_ */ +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_TC1_INSTANCE_ +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC1_INSTANCE_ */ +#ifdef _SAME70_TC1_INSTANCE_ +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC1_INSTANCE_ */ +#ifdef _SAME70_TC1_INSTANCE_ +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC1_INSTANCE_ */ +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_DACC_INSTANCE_ +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_DACC_INSTANCE_ */ +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_MCAN1_INSTANCE_ +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_MCAN1_INSTANCE_ */ +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_TWIHS2_INSTANCE_ +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TWIHS2_INSTANCE_ */ +#ifdef _SAME70_SPI1_INSTANCE_ +void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_SPI1_INSTANCE_ */ +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_UART3_INSTANCE_ +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_UART3_INSTANCE_ */ +#ifdef _SAME70_UART4_INSTANCE_ +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_UART4_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC2_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC2_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC2_INSTANCE_ */ +void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_SDRAMC_INSTANCE_ +void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_SDRAMC_INSTANCE_ */ +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCW_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_I2SC0_INSTANCE_ +void I2SC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_I2SC0_INSTANCE_ */ +#ifdef _SAME70_I2SC1_INSTANCE_ +void I2SC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_I2SC1_INSTANCE_ */ +#if (__SAM_M7_REVB == 1) +void GMAC_Q3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNMI_Handler = (void*) NMI_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemManage_Handler = (void*) MemManage_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pfnReserved1_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved2_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved3_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved4_Handler = (void*) (0UL), /* Reserved */ + .pfnSVC_Handler = (void*) SVC_Handler, + .pfnDebugMon_Handler = (void*) DebugMon_Handler, + .pfnReserved5_Handler = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real Time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real Time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Enhanced Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 UART 0 */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 UART 1 */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel I/O Controller A */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel I/O Controller B */ +#ifdef _SAME70_PIOC_INSTANCE_ + .pfnPIOC_Handler = (void*) PIOC_Handler, /* 12 Parallel I/O Controller C */ +#else + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ +#endif /* _SAME70_PIOC_INSTANCE_ */ +#ifdef _SAME70_USART0_INSTANCE_ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 USART 0 */ +#else + .pvReserved13 = (void*) (0UL), /* 13 Reserved */ +#endif /* _SAME70_USART0_INSTANCE_ */ +#ifdef _SAME70_USART1_INSTANCE_ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 USART 1 */ +#else + .pvReserved14 = (void*) (0UL), /* 14 Reserved */ +#endif /* _SAME70_USART1_INSTANCE_ */ +#ifdef _SAME70_USART2_INSTANCE_ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 USART 2 */ +#else + .pvReserved15 = (void*) (0UL), /* 15 Reserved */ +#endif /* _SAME70_USART2_INSTANCE_ */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel I/O Controller D */ +#ifdef _SAME70_PIOE_INSTANCE_ + .pfnPIOE_Handler = (void*) PIOE_Handler, /* 17 Parallel I/O Controller E */ +#else + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ +#endif /* _SAME70_PIOE_INSTANCE_ */ +#ifdef _SAME70_HSMCI_INSTANCE_ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 Multimedia Card Interface */ +#else + .pvReserved18 = (void*) (0UL), /* 18 Reserved */ +#endif /* _SAME70_HSMCI_INSTANCE_ */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two Wire Interface 0 HS */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two Wire Interface 1 HS */ +#ifdef _SAME70_SPI0_INSTANCE_ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface 0 */ +#else + .pvReserved21 = (void*) (0UL), /* 21 Reserved */ +#endif /* _SAME70_SPI0_INSTANCE_ */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer/Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer/Counter 1 */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer/Counter 2 */ +#ifdef _SAME70_TC1_INSTANCE_ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer/Counter 3 */ +#else + .pvReserved26 = (void*) (0UL), /* 26 Reserved */ +#endif /* _SAME70_TC1_INSTANCE_ */ +#ifdef _SAME70_TC1_INSTANCE_ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer/Counter 4 */ +#else + .pvReserved27 = (void*) (0UL), /* 27 Reserved */ +#endif /* _SAME70_TC1_INSTANCE_ */ +#ifdef _SAME70_TC1_INSTANCE_ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer/Counter 5 */ +#else + .pvReserved28 = (void*) (0UL), /* 28 Reserved */ +#endif /* _SAME70_TC1_INSTANCE_ */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front End 0 */ +#ifdef _SAME70_DACC_INSTANCE_ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital To Analog Converter */ +#else + .pvReserved30 = (void*) (0UL), /* 30 Reserved */ +#endif /* _SAME70_DACC_INSTANCE_ */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation 0 */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB Host / Device Controller */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ +#ifdef _SAME70_MCAN1_INSTANCE_ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ +#else + .pvReserved37 = (void*) (0UL), /* 37 Reserved */ + .pvReserved38 = (void*) (0UL), /* 38 Reserved */ +#endif /* _SAME70_MCAN1_INSTANCE_ */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front End 1 */ +#ifdef _SAME70_TWIHS2_INSTANCE_ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two Wire Interface 2 HS */ +#else + .pvReserved41 = (void*) (0UL), /* 41 Reserved */ +#endif /* _SAME70_TWIHS2_INSTANCE_ */ +#ifdef _SAME70_SPI1_INSTANCE_ + .pfnSPI1_Handler = (void*) SPI1_Handler, /* 42 Serial Peripheral Interface 1 */ +#else + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ +#endif /* _SAME70_SPI1_INSTANCE_ */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad I/O Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 UART 2 */ +#ifdef _SAME70_UART3_INSTANCE_ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 UART 3 */ +#else + .pvReserved45 = (void*) (0UL), /* 45 Reserved */ +#endif /* _SAME70_UART3_INSTANCE_ */ +#ifdef _SAME70_UART4_INSTANCE_ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 UART 4 */ +#else + .pvReserved46 = (void*) (0UL), /* 46 Reserved */ +#endif /* _SAME70_UART4_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer/Counter 6 */ +#else + .pvReserved47 = (void*) (0UL), /* 47 Reserved */ +#endif /* _SAME70_TC2_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer/Counter 7 */ +#else + .pvReserved48 = (void*) (0UL), /* 48 Reserved */ +#endif /* _SAME70_TC2_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer/Counter 8 */ +#else + .pvReserved49 = (void*) (0UL), /* 49 Reserved */ +#endif /* _SAME70_TC2_INSTANCE_ */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer/Counter 9 */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer/Counter 10 */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer/Counter 11 */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 AES */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 DMA */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Camera Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation 1 */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit Registers */ +#ifdef _SAME70_SDRAMC_INSTANCE_ + .pfnSDRAMC_Handler = (void*) SDRAMC_Handler, /* 62 SDRAM Controller */ +#else + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ +#endif /* _SAME70_SDRAMC_INSTANCE_ */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Secure Watchdog Timer */ + .pfnCCW_Handler = (void*) CCW_Handler, /* 64 System Control Registers */ + .pfnCCF_Handler = (void*) CCF_Handler, /* 65 System Control Registers */ + .pfnGMAC_Q1_Handler= (void*) GMAC_Q1_Handler,/* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler= (void*) GMAC_Q2_Handler,/* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler, /* 68 Floating Point Unit Registers */ +#ifdef _SAME70_I2SC0_INSTANCE_ + .pfnI2SC0_Handler = (void*) I2SC0_Handler, /* 69 Inter-IC Sound controller */ +#else + .pvReserved69 = (void*) (0UL), /* 69 Reserved */ +#endif /* _SAME70_I2SC0_INSTANCE_ */ +#ifdef _SAME70_I2SC1_INSTANCE_ + .pfnI2SC1_Handler = (void*) I2SC1_Handler, /* 70 Inter-IC Sound controller */ +#else + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ +#endif /* _SAME70_I2SC1_INSTANCE_ */ +#if (__SAM_M7_REVB == 1) + .pfnGMAC_Q3_Handler= (void*) GMAC_Q3_Handler,/* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler= (void*) GMAC_Q4_Handler,/* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler= (void*) GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +#else + .pvReserved71 = (void*) (0UL), /* 71 Reserved */ + .pvReserved72 = (void*) (0UL), /* 72 Reserved */ + .pvReserved73 = (void*) (0UL) /* 73 Reserved */ +#endif +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + +#if __FPU_USED + fpu_enable(); +#endif + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/source/templates/system_same70.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/source/templates/system_same70.c new file mode 100644 index 00000000..ef0e9961 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/source/templates/system_same70.c @@ -0,0 +1,255 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "same70.h" + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +/* %ATMEL_SYSTEM% */ +/* Clock Settings (600MHz PLL VDDIO 3.3V and VDDCORE 1.2V) */ +/* Clock Settings (300MHz HCLK, 150MHz MCK)=> PRESC = 2, MDIV = 2 */ +#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U)) +#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x31U) | \ + CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)) +#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK | (1<<8)) + +uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + +/** + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ + void SystemInit( void ) +{ + /* Set FWS according to SYS_BOARD_MCKR configuration */ + EFC->EEFC_FMR = EEFC_FMR_FWS(5); + + /* Initialize main oscillator */ + if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) + { + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + + while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) ) + { + } + } + + /* Switch to 3-20MHz Xtal oscillator */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; + + while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) ) + { + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + /* Initialize PLLA */ + PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; + while ( !(PMC->PMC_SR & PMC_SR_LOCKA) ) + { + } + + /* Switch to main clock */ + PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + /* Switch to PLLA */ + PMC->PMC_MCKR = SYS_BOARD_MCKR; + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + SystemCoreClock = CHIP_FREQ_CPU_MAX; +} + +void SystemCoreClockUpdate( void ) +{ + /* Determine clock frequency according to clock register values */ + switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) + { + case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */ + if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_32K; + } + else + { + SystemCoreClock = CHIP_FREQ_SLCK_RC; + } + break; + + case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */ + if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_12M; + } + else + { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) + { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + + default: + break; + } + } + break; + + case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ + if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_12M ; + } + else + { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) + { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + + default: + break; + } + } + + if ( (uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK ) + { + SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos) + 1U); + SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos)); + } + break; + + default: + break; + } + + if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 ) + { + SystemCoreClock /= 3U; + } + else + { + SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos); + } +} +/** + * Initialize flash. + */ +void system_init_flash( uint32_t ul_clk ) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if ( ul_clk < CHIP_FREQ_FWS_0 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE; + } + else + { + if (ul_clk < CHIP_FREQ_FWS_1) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE; + } + else + { + if (ul_clk < CHIP_FREQ_FWS_2) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE; + } + else + { + if ( ul_clk < CHIP_FREQ_FWS_3 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE; + } + else + { + if ( ul_clk < CHIP_FREQ_FWS_4 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE; + } + else + { + if ( ul_clk < CHIP_FREQ_FWS_5 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE; + } + else + { + EFC->EEFC_FMR = EEFC_FMR_FWS(6)|EEFC_FMR_CLOE; + } + } + } + } + } + } +} +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/source/templates/system_same70.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/source/templates/system_same70.h new file mode 100644 index 00000000..f605ccca --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/source/templates/system_same70.h @@ -0,0 +1,75 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef SYSTEM_SAME70_H_INCLUDED +#define SYSTEM_SAME70_H_INCLUDED + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAME70_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/compiler.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/compiler.h new file mode 100644 index 00000000..67cd4ebb --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/compiler.h @@ -0,0 +1,1189 @@ +/** + * \file + * + * \brief Commonly used includes, types and macros. + * + * Copyright (c) 2010-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef UTILS_COMPILER_H +#define UTILS_COMPILER_H + +/** + * \defgroup group_sam_utils Compiler abstraction layer and code utilities + * + * Compiler abstraction layer and code utilities for AT91SAM. + * This module provides various abstraction layers and utilities to make code compatible between different compilers. + * + * \{ + */ +#include + +#if (defined __ICCARM__) +# include +#endif + +#include +#include "preprocessor.h" + +#include + +//_____ D E C L A R A T I O N S ____________________________________________ + +#ifndef __ASSEMBLY__ // Not defined for assembling. + +#include +#include +#include +#include + +#ifdef __ICCARM__ +/*! \name Compiler Keywords + * + * Port of some keywords from GCC to IAR Embedded Workbench. + */ +//! @{ +#define __asm__ asm +#define __inline__ inline +#define __volatile__ +//! @} + +#endif + +#define FUNC_PTR void * +/** + * \def UNUSED + * \brief Marking \a v as a unused parameter or value. + */ +#define UNUSED(v) (void)(v) + +/** + * \def unused + * \brief Marking \a v as a unused parameter or value. + */ +#define unused(v) do { (void)(v); } while(0) + +/** + * \def barrier + * \brief Memory barrier + */ +#define barrier() __DMB() + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union + * definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union + * definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + + +/** + * \brief Set aligned boundary. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif (defined __ICCARM__) +# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#endif + +/** + * \brief Set word-aligned boundary. + */ +#if (defined __GNUC__) || defined(__CC_ARM) +#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#elif (defined __ICCARM__) +#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) +#endif + +/** + * \def __always_inline + * \brief The function should always be inlined. + * + * This annotation instructs the compiler to ignore its inlining + * heuristics and inline the function no matter how big it thinks it + * becomes. + */ +#if defined(__CC_ARM) +# define __always_inline __forceinline +#elif (defined __GNUC__) +#ifdef __always_inline +# undef __always_inline +#endif +# define __always_inline inline __attribute__((__always_inline__)) +#elif (defined __ICCARM__) +# define __always_inline _Pragma("inline=forced") +#endif + +/** + * \def __no_inline + * \brief The function should not be inlined. + * + * This annotation instructs the compiler to ignore its inlining + * heuristics and not inline the function. + */ +#if defined(__CC_ARM) +# define __no_inline __attribute__((noinline)) +#elif (defined __GNUC__) +# define __no_inline __attribute__((__noinline__)) +#elif (defined __ICCARM__) +# define __no_inline _Pragma("inline=never") +#endif + +/*! \brief This macro is used to test fatal errors. + * + * The macro tests if the expression is false. If it is, a fatal error is + * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO + * is defined, a unit test version of the macro is used, to allow execution + * of further tests after a false expression. + * + * \param expr Expression to evaluate and supposed to be nonzero. + */ +#if defined(_ASSERT_ENABLE_) +# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO) + // Assert() is defined in unit_test/suite.h +# include "unit_test/suite.h" +# else +#undef TEST_SUITE_DEFINE_ASSERT_MACRO +# define Assert(expr) \ + {\ + if (!(expr)) while (true);\ + } +# endif +#else +# define Assert(expr) ((void) 0) +#endif + +/* Define WEAK attribute */ +#if defined ( __CC_ARM ) /* Keil µVision 4 */ +# define WEAK __attribute__ ((weak)) +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +# define WEAK __weak +#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ +# define WEAK __attribute__ ((weak)) +#endif + +/* Define NO_INIT attribute */ +#if defined ( __CC_ARM ) +# define NO_INIT __attribute__((zero_init)) +#elif defined ( __ICCARM__ ) +# define NO_INIT __no_init +#elif defined ( __GNUC__ ) +# define NO_INIT __attribute__((section(".no_init"))) +#endif + +/* Define RAMFUNC attribute */ +#if defined ( __CC_ARM ) /* Keil µVision 4 */ +# define RAMFUNC __attribute__ ((section(".ramfunc"))) +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +# define RAMFUNC __ramfunc +#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ +# define RAMFUNC __attribute__ ((section(".ramfunc"))) +#endif + +/* Define OPTIMIZE_HIGH attribute */ +#if defined ( __CC_ARM ) /* Keil µVision 4 */ +# define OPTIMIZE_HIGH _Pragma("O3") +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +# define OPTIMIZE_HIGH _Pragma("optimize=high") +#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ +# define OPTIMIZE_HIGH __attribute__((optimize("s"))) +#endif + +#include "interrupt.h" + +/*! \name Usual Types + */ +//! @{ +typedef unsigned char Bool; //!< Boolean. +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +typedef unsigned char bool; //!< Boolean. +#endif +#endif +typedef int8_t S8 ; //!< 8-bit signed integer. +typedef uint8_t U8 ; //!< 8-bit unsigned integer. +typedef int16_t S16; //!< 16-bit signed integer. +typedef uint16_t U16; //!< 16-bit unsigned integer. +typedef uint16_t le16_t; +typedef uint16_t be16_t; +typedef int32_t S32; //!< 32-bit signed integer. +typedef uint32_t U32; //!< 32-bit unsigned integer. +typedef uint32_t le32_t; +typedef uint32_t be32_t; +typedef int64_t S64; //!< 64-bit signed integer. +typedef uint64_t U64; //!< 64-bit unsigned integer. +typedef float F32; //!< 32-bit floating-point number. +typedef double F64; //!< 64-bit floating-point number. +typedef uint32_t iram_size_t; +//! @} + + +/*! \name Status Types + */ +//! @{ +typedef bool Status_bool_t; //!< Boolean status. +typedef U8 Status_t; //!< 8-bit-coded status. +//! @} + + +/*! \name Aliasing Aggregate Types + */ +//! @{ + +//! 16-bit union. +typedef union +{ + S16 s16 ; + U16 u16 ; + S8 s8 [2]; + U8 u8 [2]; +} Union16; + +//! 32-bit union. +typedef union +{ + S32 s32 ; + U32 u32 ; + S16 s16[2]; + U16 u16[2]; + S8 s8 [4]; + U8 u8 [4]; +} Union32; + +//! 64-bit union. +typedef union +{ + S64 s64 ; + U64 u64 ; + S32 s32[2]; + U32 u32[2]; + S16 s16[4]; + U16 u16[4]; + S8 s8 [8]; + U8 u8 [8]; +} Union64; + +//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} UnionPtr; + +//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} UnionVPtr; + +//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} UnionCPtr; + +//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} UnionCVPtr; + +//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} StructPtr; + +//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} StructVPtr; + +//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} StructCPtr; + +//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} StructCVPtr; + +//! @} + +#endif // #ifndef __ASSEMBLY__ + +/*! \name Usual Constants + */ +//! @{ +#define DISABLE 0 +#define ENABLE 1 +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +#define false 0 +#define true 1 +#endif +#endif +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +//! @} + + +#ifndef __ASSEMBLY__ // not for assembling. + +//! \name Optimization Control +//@{ + +/** + * \def likely(exp) + * \brief The expression \a exp is likely to be true + */ +#ifndef likely +# define likely(exp) (exp) +#endif + +/** + * \def unlikely(exp) + * \brief The expression \a exp is unlikely to be true + */ +#ifndef unlikely +# define unlikely(exp) (exp) +#endif + +/** + * \def is_constant(exp) + * \brief Determine if an expression evaluates to a constant value. + * + * \param exp Any expression + * + * \return true if \a exp is constant, false otherwise. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define is_constant(exp) __builtin_constant_p(exp) +#else +# define is_constant(exp) (0) +#endif + +//! @} + +/*! \name Bit-Field Handling + */ +//! @{ + +/*! \brief Reads the bits of a value specified by a given bit-mask. + * + * \param value Value to read bits from. + * \param mask Bit-mask indicating bits to read. + * + * \return Read bits. + */ +#define Rd_bits( value, mask) ((value) & (mask)) + +/*! \brief Writes the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write bits to. + * \param mask Bit-mask indicating bits to write. + * \param bits Bits to write. + * + * \return Resulting value with written bits. + */ +#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\ + ((bits ) & (mask))) + +/*! \brief Tests the bits of a value specified by a given bit-mask. + * + * \param value Value of which to test bits. + * \param mask Bit-mask indicating bits to test. + * + * \return \c 1 if at least one of the tested bits is set, else \c 0. + */ +#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0) + +/*! \brief Clears the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to clear bits. + * \param mask Bit-mask indicating bits to clear. + * + * \return Resulting value with cleared bits. + */ +#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask)) + +/*! \brief Sets the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to set bits. + * \param mask Bit-mask indicating bits to set. + * + * \return Resulting value with set bits. + */ +#define Set_bits(lvalue, mask) ((lvalue) |= (mask)) + +/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to toggle bits. + * \param mask Bit-mask indicating bits to toggle. + * + * \return Resulting value with toggled bits. + */ +#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask)) + +/*! \brief Reads the bit-field of a value specified by a given bit-mask. + * + * \param value Value to read a bit-field from. + * \param mask Bit-mask indicating the bit-field to read. + * + * \return Read bit-field. + */ +#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask)) + +/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write a bit-field to. + * \param mask Bit-mask indicating the bit-field to write. + * \param bitfield Bit-field to write. + * + * \return Resulting value with written bit-field. + */ +#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask))) + +//! @} + + +/*! \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + */ +//! @{ + +/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define clz(u) ((u) ? __builtin_clz(u) : 32) +#elif (defined __ICCARM__) +# define clz(u) ((u) ? __CLZ(u) : 32) +#else +# define clz(u) (((u) == 0) ? 32 : \ + ((u) & (1ul << 31)) ? 0 : \ + ((u) & (1ul << 30)) ? 1 : \ + ((u) & (1ul << 29)) ? 2 : \ + ((u) & (1ul << 28)) ? 3 : \ + ((u) & (1ul << 27)) ? 4 : \ + ((u) & (1ul << 26)) ? 5 : \ + ((u) & (1ul << 25)) ? 6 : \ + ((u) & (1ul << 24)) ? 7 : \ + ((u) & (1ul << 23)) ? 8 : \ + ((u) & (1ul << 22)) ? 9 : \ + ((u) & (1ul << 21)) ? 10 : \ + ((u) & (1ul << 20)) ? 11 : \ + ((u) & (1ul << 19)) ? 12 : \ + ((u) & (1ul << 18)) ? 13 : \ + ((u) & (1ul << 17)) ? 14 : \ + ((u) & (1ul << 16)) ? 15 : \ + ((u) & (1ul << 15)) ? 16 : \ + ((u) & (1ul << 14)) ? 17 : \ + ((u) & (1ul << 13)) ? 18 : \ + ((u) & (1ul << 12)) ? 19 : \ + ((u) & (1ul << 11)) ? 20 : \ + ((u) & (1ul << 10)) ? 21 : \ + ((u) & (1ul << 9)) ? 22 : \ + ((u) & (1ul << 8)) ? 23 : \ + ((u) & (1ul << 7)) ? 24 : \ + ((u) & (1ul << 6)) ? 25 : \ + ((u) & (1ul << 5)) ? 26 : \ + ((u) & (1ul << 4)) ? 27 : \ + ((u) & (1ul << 3)) ? 28 : \ + ((u) & (1ul << 2)) ? 29 : \ + ((u) & (1ul << 1)) ? 30 : \ + 31) +#endif + +/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define ctz(u) ((u) ? __builtin_ctz(u) : 32) +#else +# define ctz(u) ((u) & (1ul << 0) ? 0 : \ + (u) & (1ul << 1) ? 1 : \ + (u) & (1ul << 2) ? 2 : \ + (u) & (1ul << 3) ? 3 : \ + (u) & (1ul << 4) ? 4 : \ + (u) & (1ul << 5) ? 5 : \ + (u) & (1ul << 6) ? 6 : \ + (u) & (1ul << 7) ? 7 : \ + (u) & (1ul << 8) ? 8 : \ + (u) & (1ul << 9) ? 9 : \ + (u) & (1ul << 10) ? 10 : \ + (u) & (1ul << 11) ? 11 : \ + (u) & (1ul << 12) ? 12 : \ + (u) & (1ul << 13) ? 13 : \ + (u) & (1ul << 14) ? 14 : \ + (u) & (1ul << 15) ? 15 : \ + (u) & (1ul << 16) ? 16 : \ + (u) & (1ul << 17) ? 17 : \ + (u) & (1ul << 18) ? 18 : \ + (u) & (1ul << 19) ? 19 : \ + (u) & (1ul << 20) ? 20 : \ + (u) & (1ul << 21) ? 21 : \ + (u) & (1ul << 22) ? 22 : \ + (u) & (1ul << 23) ? 23 : \ + (u) & (1ul << 24) ? 24 : \ + (u) & (1ul << 25) ? 25 : \ + (u) & (1ul << 26) ? 26 : \ + (u) & (1ul << 27) ? 27 : \ + (u) & (1ul << 28) ? 28 : \ + (u) & (1ul << 29) ? 29 : \ + (u) & (1ul << 30) ? 30 : \ + (u) & (1ul << 31) ? 31 : \ + 32) +#endif + +//! @} + + +/*! \name Bit Reversing + */ +//! @{ + +/*! \brief Reverses the bits of \a u8. + * + * \param u8 U8 of which to reverse the bits. + * + * \return Value resulting from \a u8 with reversed bits. + */ +#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24)) + +/*! \brief Reverses the bits of \a u16. + * + * \param u16 U16 of which to reverse the bits. + * + * \return Value resulting from \a u16 with reversed bits. + */ +#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16)) + +/*! \brief Reverses the bits of \a u32. + * + * \param u32 U32 of which to reverse the bits. + * + * \return Value resulting from \a u32 with reversed bits. + */ +#define bit_reverse32(u32) __RBIT(u32) + +/*! \brief Reverses the bits of \a u64. + * + * \param u64 U64 of which to reverse the bits. + * + * \return Value resulting from \a u64 with reversed bits. + */ +#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\ + ((U64)bit_reverse32((U64)(u64)) << 32))) + +//! @} + + +/*! \name Alignment + */ +//! @{ + +/*! \brief Tests alignment of the number \a val with the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0. + */ +#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) ) + +/*! \brief Gets alignment of the number \a val with respect to the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Alignment of the number \a val with respect to the \a n boundary. + */ +#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) ) + +/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary. + * + * \param lval Input/output lvalue. + * \param n Boundary. + * \param alg Alignment. + * + * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary. + */ +#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) ) + +/*! \brief Aligns the number \a val with the upper \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the upper \a n boundary. + */ +#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1)) + +/*! \brief Aligns the number \a val with the lower \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the lower \a n boundary. + */ +#define Align_down(val, n ) ( (val) & ~((n) - 1)) + +//! @} + + +/*! \name Mathematics + * + * The same considerations as for clz and ctz apply here but GCC does not + * provide built-in functions to access the assembly instructions abs, min and + * max and it does not produce them by itself in most cases, so two sets of + * macros are defined here: + * - Abs, Min and Max to apply to constant expressions (values known at + * compile time); + * - abs, min and max to apply to non-constant expressions (values unknown at + * compile time), abs is found in stdlib.h. + */ +//! @{ + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values known at compile time. + */ +#define Abs(a) (((a) < 0 ) ? -(a) : (a)) + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Min(a, b) (((a) < (b)) ? (a) : (b)) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Max(a, b) (((a) > (b)) ? (a) : (b)) + +// abs() is already defined by stdlib.h + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define min(a, b) Min(a, b) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define max(a, b) Max(a, b) + +//! @} + + +/*! \brief Calls the routine at address \a addr. + * + * It generates a long call opcode. + * + * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if + * it is invoked from the CPU supervisor mode. + * + * \param addr Address of the routine to call. + * + * \note It may be used as a long jump opcode in some special cases. + */ +#define Long_call(addr) ((*(void (*)(void))(addr))()) + + +/*! \name MCU Endianism Handling + * ARM is MCU little endianism. + */ +//! @{ +#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16. +#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16. + +#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32. +#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32. +#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32. +#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32. +#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32. +#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32. +#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32. +#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32. +#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32. +#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32. + +#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64. +#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64. +#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64. +#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64. +#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64. +#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64. +#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64. +#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64. +#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64. +#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64. +#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64. +#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64. +#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64. +#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64. +#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64. +#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64. +#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64. +#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64. +#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64. +#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64. +#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64. +#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64. +#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64. +#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64. +#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64. +#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64. + +#define BE16(x) swap16(x) +#define LE16(x) (x) + +#define le16_to_cpu(x) (x) +#define cpu_to_le16(x) (x) +#define LE16_TO_CPU(x) (x) +#define CPU_TO_LE16(x) (x) + +#define be16_to_cpu(x) swap16(x) +#define cpu_to_be16(x) swap16(x) +#define BE16_TO_CPU(x) swap16(x) +#define CPU_TO_BE16(x) swap16(x) + +#define le32_to_cpu(x) (x) +#define cpu_to_le32(x) (x) +#define LE32_TO_CPU(x) (x) +#define CPU_TO_LE32(x) (x) + +#define be32_to_cpu(x) swap32(x) +#define cpu_to_be32(x) swap32(x) +#define BE32_TO_CPU(x) swap32(x) +#define CPU_TO_BE32(x) swap32(x) +//! @} + + +/*! \name Endianism Conversion + * + * The same considerations as for clz and ctz apply here but GCC's + * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when + * applied to constant expressions, so two sets of macros are defined here: + * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known + * at compile time); + * - swap16, swap32 and swap64 to apply to non-constant expressions (values + * unknown at compile time). + */ +//! @{ + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\ + ((U16)(u16) << 8))) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\ + ((U32)Swap16((U32)(u32)) << 16))) + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\ + ((U64)Swap32((U64)(u64)) << 32))) + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define swap16(u16) Swap16(u16) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) +# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32))) +#else +# define swap32(u32) Swap32(u32) +#endif + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) +# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64))) +#else +# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\ + ((U64)swap32((U64)(u64)) << 32))) +#endif + +//! @} + + +/*! \name Target Abstraction + */ +//! @{ + +#define _GLOBEXT_ extern //!< extern storage-class specifier. +#define _CONST_TYPE_ const //!< const type qualifier. +#define _MEM_TYPE_SLOW_ //!< Slow memory type. +#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type. +#define _MEM_TYPE_FAST_ //!< Fast memory type. + +typedef U8 Byte; //!< 8-bit unsigned integer. + +#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM. +#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM. +#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM. +#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM. + +#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32. +#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32. +#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32. +#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32. +#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32. +#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32. +#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32. +#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32. + +//! @} + +/** + * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using + * integer arithmetic. + * + * \param a An integer + * \param b Another integer + * + * \return (\a a / \a b) rounded up to the nearest integer. + */ +#define div_ceil(a, b) (((a) + (b) - 1) / (b)) + +#endif // #ifndef __ASSEMBLY__ + + +#if defined(__ICCARM__) +#define SHORTENUM __packed +#elif defined(__GNUC__) +#define SHORTENUM __attribute__((packed)) +#endif + +/* No operation */ +#if defined(__ICCARM__) +#define nop() __no_operation() +#elif defined(__GNUC__) +#define nop() __NOP() +#endif + +#define FLASH_DECLARE(x) const x +#define FLASH_EXTERN(x) extern const x +#define PGM_READ_BYTE(x) *(x) +#define PGM_READ_WORD(x) *(x) +#define PGM_READ_DWORD(x) *(x) +#define MEMCPY_ENDIAN memcpy +#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len)) + +/*Defines the Flash Storage for the request and response of MAC*/ +#define CMD_ID_OCTET (0) + +/* Converting of values from CPU endian to little endian. */ +#define CPU_ENDIAN_TO_LE16(x) (x) +#define CPU_ENDIAN_TO_LE32(x) (x) +#define CPU_ENDIAN_TO_LE64(x) (x) + +/* Converting of values from little endian to CPU endian. */ +#define LE16_TO_CPU_ENDIAN(x) (x) +#define LE32_TO_CPU_ENDIAN(x) (x) +#define LE64_TO_CPU_ENDIAN(x) (x) + +/* Converting of constants from little endian to CPU endian. */ +#define CLE16_TO_CPU_ENDIAN(x) (x) +#define CLE32_TO_CPU_ENDIAN(x) (x) +#define CLE64_TO_CPU_ENDIAN(x) (x) + +/* Converting of constants from CPU endian to little endian. */ +#define CCPU_ENDIAN_TO_LE16(x) (x) +#define CCPU_ENDIAN_TO_LE32(x) (x) +#define CCPU_ENDIAN_TO_LE64(x) (x) + +#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src)) +#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src)) + +/** + * @brief Converts a 64-Bit value into a 8 Byte array + * + * @param[in] value 64-Bit value + * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value + * @ingroup apiPalApi + */ +static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data) +{ + uint8_t val_index = 0; + + while (val_index < 8) + { + data[val_index++] = value & 0xFF; + value = value >> 8; + } +} + +/** + * @brief Converts a 16-Bit value into a 2 Byte array + * + * @param[in] value 16-Bit value + * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value + * @ingroup apiPalApi + */ +static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} + +/* Converts a 16-Bit value into a 2 Byte array */ +static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} + +/* Converts a 16-Bit value into a 2 Byte array */ +static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} + +/* + * @brief Converts a 2 Byte array into a 16-Bit value + * + * @param data Specifies the pointer to the 2 Byte array + * + * @return 16-Bit value + * @ingroup apiPalApi + */ +static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data) +{ + return (data[0] | ((uint16_t)data[1] << 8)); +} + +/* Converts a 8 Byte array into a 32-Bit value */ +static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data) +{ + union + { + uint32_t u32; + uint8_t u8[8]; + }long_addr; + uint8_t index; + for (index = 0; index < 4; index++) + { + long_addr.u8[index] = *data++; + } + return long_addr.u32; +} + +/** + * @brief Converts a 8 Byte array into a 64-Bit value + * + * @param data Specifies the pointer to the 8 Byte array + * + * @return 64-Bit value + * @ingroup apiPalApi + */ +static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data) +{ + union + { + uint64_t u64; + uint8_t u8[8]; + } long_addr; + + uint8_t val_index; + + for (val_index = 0; val_index < 8; val_index++) + { + long_addr.u8[val_index] = *data++; + } + + return long_addr.u64; +} +/** + * \} + */ + +#endif /* UTILS_COMPILER_H */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/fpu/fpu.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/fpu/fpu.h new file mode 100644 index 00000000..76781e6d --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/fpu/fpu.h @@ -0,0 +1,84 @@ +/** + * \file + * + * \brief FPU support for SAM. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _FPU_H_INCLUDED_ +#define _FPU_H_INCLUDED_ + +#include + +/** Address for ARM CPACR */ +#define ADDR_CPACR 0xE000ED88 + +/** CPACR Register */ +#define REG_CPACR (*((volatile uint32_t *)ADDR_CPACR)) + +/** + * \brief Enable FPU + */ +__always_inline static void fpu_enable(void) +{ + irqflags_t flags; + flags = cpu_irq_save(); + REG_CPACR |= (0xFu << 20); + __DSB(); + __ISB(); + cpu_irq_restore(flags); +} + +/** + * \brief Disable FPU + */ +__always_inline static void fpu_disable(void) +{ + irqflags_t flags; + flags = cpu_irq_save(); + REG_CPACR &= ~(0xFu << 20); + __DSB(); + __ISB(); + cpu_irq_restore(flags); +} + +/** + * \brief Check if FPU is enabled + * + * \return Return ture if FPU is enabled, otherwise return false. + */ +__always_inline static bool fpu_is_enabled(void) +{ + return (REG_CPACR & (0xFu << 20)); +} + +#endif /* _FPU_H_INCLUDED_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/header_files/io.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/header_files/io.h new file mode 100644 index 00000000..9b0fdc09 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/header_files/io.h @@ -0,0 +1,147 @@ +/** + * \file + * + * \brief Arch file for SAM. + * + * This file defines common SAM series. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAM_IO_ +#define _SAM_IO_ + +/* SAM3 family */ + +/* SAM3S series */ +#if (SAM3S) +# if (SAM3S8 || SAM3SD8) +# include "sam3s8.h" +# else +# include "sam3s.h" +# endif +#endif + +/* SAM3U series */ +#if (SAM3U) +# include "sam3u.h" +#endif + +/* SAM3N series */ +#if (SAM3N) +# include "sam3n.h" +#endif + +/* SAM3XA series */ +#if (SAM3XA) +# include "sam3xa.h" +#endif + +/* SAM4S series */ +#if (SAM4S) +# include "sam4s.h" +#endif + +/* SAM4L series */ +#if (SAM4L) +# include "sam4l.h" +#endif + +/* SAM4E series */ +#if (SAM4E) +# include "sam4e.h" +#endif + +/* SAM4N series */ +#if (SAM4N) +# include "sam4n.h" +#endif + +/* SAM4C series */ +#if (SAM4C) +# include "sam4c.h" +#endif + +/* SAM4CM series */ +#if (SAM4CM) +# if (SAM4CMP32 || SAM4CMS32) +# include "sam4cm32.h" +# else +# include "sam4cm.h" +# endif +#endif + +/* SAM4CP series */ +#if (SAM4CP) +# include "sam4cp.h" +#endif + +/* SAMG51 series */ +#if (SAMG51) +# include "samg51.h" +#endif + +/* SAMG53 series */ +#if (SAMG53) +# include "samg53.h" +#endif + +/* SAMG54 series */ +#if (SAMG54) +# include "samg54.h" +#endif + +/* SAMG55 series */ +#if (SAMG55) +# include "samg55.h" +#endif + +/* SAMV71 series */ +#if (SAMV71) +# include "samv71.h" +#endif + +/* SAMV70 series */ +#if (SAMV70) +# include "samv70.h" +#endif + +/* SAME70 series */ +#if (SAME70) +# include "same70.h" +#endif + +/* SAMS70 series */ +#if (SAMS70) +# include "sams70.h" +#endif + +#endif /* _SAM_IO_ */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/linker_scripts/same70/same70q21/gcc/flash.ld b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/linker_scripts/same70/same70q21/gcc/flash.ld new file mode 100644 index 00000000..ff960430 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/linker_scripts/same70/same70q21/gcc/flash.ld @@ -0,0 +1,174 @@ +/** + * \file + * + * Copyright (c) 2015 Microchip Technology Inc. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70Q21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; +__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; +} + diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/make/Makefile.sam.in b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/make/Makefile.sam.in new file mode 100644 index 00000000..1ba06e0b --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/make/Makefile.sam.in @@ -0,0 +1,486 @@ +# List of available make goals: +# +# all Default target, builds the project +# clean Clean up the project +# rebuild Rebuild the project +# debug_flash Builds the project and debug in flash +# debug_sram Builds the project and debug in sram +# +# doc Build the documentation +# cleandoc Clean up the documentation +# rebuilddoc Rebuild the documentation +# +# \file +# +# Copyright (c) 2011 - 2018 Microchip Technology Inc. and its subsidiaries. +# +# \asf_license_start +# +# \page License +# +# Subject to your compliance with these terms, you may use Microchip +# software and any derivatives exclusively with Microchip products. +# It is your responsibility to comply with third party license terms applicable +# to your use of third party software (including open source software) that +# may accompany Microchip software. +# +# THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, +# WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +# INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +# AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE +# LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL +# LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE +# SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE +# POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT +# ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY +# RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +# THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +# +# \asf_license_stop +# + +# Include the config.mk file from the current working path, e.g., where the +# user called make. +include config.mk + +# Tool to use to generate documentation from the source code +DOCGEN ?= doxygen + +# Look for source files relative to the top-level source directory +VPATH := $(PRJ_PATH) + +# Output target file +project_type := $(PROJECT_TYPE) + +# Output target file +ifeq ($(project_type),flash) +target := $(TARGET_FLASH) +linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH) +debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH) +else +target := $(TARGET_SRAM) +linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM) +debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM) +endif + +# Output project name (target name minus suffix) +project := $(basename $(target)) + +# Output target file (typically ELF or static library) +ifeq ($(suffix $(target)),.a) +target_type := lib +else +ifeq ($(suffix $(target)),.elf) +target_type := elf +else +$(error "Target type $(target_type) is not supported") +endif +endif + +# Allow override of operating system detection. The user can add OS=Linux or +# OS=Windows on the command line to explicit set the host OS. +# +# This allows to work around broken uname utility on certain systems. +ifdef OS + ifeq ($(strip $(OS)), Linux) + os_type := Linux + endif + ifeq ($(strip $(OS)), Windows) + os_type := windows32_64 + endif +endif + +os_type ?= $(strip $(shell uname)) + +ifeq ($(os_type),windows32) +os := Windows +else +ifeq ($(os_type),windows64) +os := Windows +else +ifeq ($(os_type),windows32_64) +os ?= Windows +else +ifeq ($(os_type),) +os := Windows +else +# Default to Linux style operating system. Both Cygwin and mingw are fully +# compatible (for this Makefile) with Linux. +os := Linux +endif +endif +endif +endif + +# Output documentation directory and configuration file. +docdir := ../doxygen/html +doccfg := ../doxygen/doxyfile.doxygen + +CROSS ?= arm-none-eabi- +AR := $(CROSS)ar +AS := $(CROSS)as +CC := $(CROSS)gcc +CPP := $(CROSS)gcc -E +CXX := $(CROSS)g++ +LD := $(CROSS)g++ +NM := $(CROSS)nm +OBJCOPY := $(CROSS)objcopy +OBJDUMP := $(CROSS)objdump +SIZE := $(CROSS)size +GDB := $(CROSS)gdb + +RM := rm +ifeq ($(os),Windows) +RMDIR := rmdir /S /Q +else +RMDIR := rmdir -p --ignore-fail-on-non-empty +endif + +# On Windows, we need to override the shell to force the use of cmd.exe +ifeq ($(os),Windows) +SHELL := cmd +endif + +# Strings for beautifying output +MSG_CLEAN_FILES = "RM *.o *.d" +MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))" +MSG_CLEAN_DOC = "RMDIR $(docdir)" +MSG_MKDIR = "MKDIR $(dir $@)" + +MSG_INFO = "INFO " +MSG_PREBUILD = "PREBUILD $(PREBUILD_CMD)" +MSG_POSTBUILD = "POSTBUILD $(POSTBUILD_CMD)" + +MSG_ARCHIVING = "AR $@" +MSG_ASSEMBLING = "AS $@" +MSG_BINARY_IMAGE = "OBJCOPY $@" +MSG_COMPILING = "CC $@" +MSG_COMPILING_CXX = "CXX $@" +MSG_EXTENDED_LISTING = "OBJDUMP $@" +MSG_IHEX_IMAGE = "OBJCOPY $@" +MSG_LINKING = "LN $@" +MSG_PREPROCESSING = "CPP $@" +MSG_SIZE = "SIZE $@" +MSG_SYMBOL_TABLE = "NM $@" + +MSG_GENERATING_DOC = "DOXYGEN $(docdir)" + +# Don't use make's built-in rules and variables +MAKEFLAGS += -rR + +# Don't print 'Entering directory ...' +MAKEFLAGS += --no-print-directory + +# Function for reversing the order of a list +reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1)) + +# Hide command output by default, but allow the user to override this +# by adding V=1 on the command line. +# +# This is inspired by the Kbuild system used by the Linux kernel. +ifdef V + ifeq ("$(origin V)", "command line") + VERBOSE = $(V) + endif +endif +ifndef VERBOSE + VERBOSE = 0 +endif + +ifeq ($(VERBOSE), 1) + Q = +else + Q = @ +endif + +arflags-gnu-y := $(ARFLAGS) +asflags-gnu-y := $(ASFLAGS) +cflags-gnu-y := $(CFLAGS) +cxxflags-gnu-y := $(CXXFLAGS) +cppflags-gnu-y := $(CPPFLAGS) +cpuflags-gnu-y := +dbgflags-gnu-y := $(DBGFLAGS) +libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB)) +ldflags-gnu-y := $(LDFLAGS) +flashflags-gnu-y := +clean-files := +clean-dirs := + +clean-files += $(wildcard $(target) $(project).map) +clean-files += $(wildcard $(project).hex $(project).bin) +clean-files += $(wildcard $(project).lss $(project).sym) +clean-files += $(wildcard $(build)) + +# Use pipes instead of temporary files for communication between processes +cflags-gnu-y += -pipe +asflags-gnu-y += -pipe +ldflags-gnu-y += -pipe + +# Archiver flags. +arflags-gnu-y += rcs + +# Always enable warnings. And be very careful about implicit +# declarations. +cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes +cflags-gnu-y += -Werror-implicit-function-declaration +cxxflags-gnu-y += -Wall +# IAR doesn't allow arithmetic on void pointers, so warn about that. +cflags-gnu-y += -Wpointer-arith +cxxflags-gnu-y += -Wpointer-arith + +# Preprocessor flags. +cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC)) +asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)') + +# CPU specific flags. +cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__ + +# Dependency file flags. +depflags = -MD -MP -MQ $@ + +# Debug specific flags. +ifdef BUILD_DEBUG_LEVEL +dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL) +else +dbgflags-gnu-y += -g3 +endif + +# Optimization specific flags. +ifdef BUILD_OPTIMIZATION +optflags-gnu-y = -O$(BUILD_OPTIMIZATION) +else +optflags-gnu-y = $(OPTIMIZATION) +endif + +# Always preprocess assembler files. +asflags-gnu-y += -x assembler-with-cpp +# Compile C files using the GNU99 standard. +cflags-gnu-y += -std=gnu99 +# Compile C++ files using the GNU++98 standard. +cxxflags-gnu-y += -std=gnu++98 + +# Don't use strict aliasing (very common in embedded applications). +cflags-gnu-y += -fno-strict-aliasing +cxxflags-gnu-y += -fno-strict-aliasing + +# Separate each function and data into its own separate section to allow +# garbage collection of unused sections. +cflags-gnu-y += -ffunction-sections -fdata-sections +cxxflags-gnu-y += -ffunction-sections -fdata-sections + +# Various cflags. +cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int +cflags-gnu-y += -Wmain -Wparentheses +cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused +cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef +cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings +cflags-gnu-y += -Wsign-compare -Waggregate-return +cflags-gnu-y += -Wmissing-declarations +cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations +cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long +cflags-gnu-y += -Wunreachable-code +cflags-gnu-y += -Wcast-align +cflags-gnu-y += --param max-inline-insns-single=500 + +# Garbage collect unreferred sections when linking. +ldflags-gnu-y += -Wl,--gc-sections + +# Use the linker script if provided by the project. +ifneq ($(strip $(linker_script)),) +ldflags-gnu-y += -Wl,-T $(linker_script) +endif + +# Output a link map file and a cross reference table +ldflags-gnu-y += -Wl,-Map=$(project).map,--cref + +# Add library search paths relative to the top level directory. +ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH)) + +a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__ +c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y) +cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y) +l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y) +ar_flags = $(arflags-gnu-y) + +# Source files list and part informations must already be included before +# running this makefile + +# If a custom build directory is specified, use it -- force trailing / in directory name. +ifdef BUILD_DIR + build-dir := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/) +else + build-dir = +endif + +# Create object files list from source files list. +obj-y := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS)))) +# Create dependency files list from source files list. +dep-files := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d)) + +clean-files += $(wildcard $(obj-y)) +clean-files += $(dep-files) + +clean-dirs += $(call reverse,$(sort $(wildcard $(dir $(obj-y))))) + +# Default target. +.PHONY: all +ifeq ($(project_type),all) +all: + $(MAKE) all PROJECT_TYPE=flash + $(MAKE) all PROJECT_TYPE=sram +else +ifeq ($(target_type),lib) +all: $(target) $(project).lss $(project).sym +else +ifeq ($(target_type),elf) +all: prebuild $(target) $(project).lss $(project).sym $(project).hex $(project).bin postbuild +endif +endif +endif + +prebuild: +ifneq ($(strip $(PREBUILD_CMD)),) + @echo $(MSG_PREBUILD) + $(Q)$(PREBUILD_CMD) +endif + +postbuild: +ifneq ($(strip $(POSTBUILD_CMD)),) + @echo $(MSG_POSTBUILD) + $(Q)$(POSTBUILD_CMD) +endif + +# Clean up the project. +.PHONY: clean +clean: + @$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES)) + $(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),) + @$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS)) +# Remove created directories, and make sure we only remove existing +# directories, since recursive rmdir might help us a bit on the way. +ifeq ($(os),Windows) + $(Q)$(if $(strip $(clean-dirs)), \ + $(RMDIR) $(strip $(subst /,\,$(clean-dirs)))) +else + $(Q)$(if $(strip $(clean-dirs)), \ + for directory in $(strip $(clean-dirs)); do \ + if [ -d "$$directory" ]; then \ + $(RMDIR) $$directory; \ + fi \ + done \ + ) +endif + +# Rebuild the project. +.PHONY: rebuild +rebuild: clean all + +# Debug the project in flash. +.PHONY: debug_flash +debug_flash: all + $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH) + +# Debug the project in sram. +.PHONY: debug_sram +debug_sram: all + $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM) + +.PHONY: objfiles +objfiles: $(obj-y) + +# Create object files from C source files. +$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk + $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) +ifeq ($(os),Windows) + $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) +else + $(Q)test -d $(dir $@) || mkdir -p $(dir $@) +endif + @echo $(MSG_COMPILING) + $(Q)$(CC) $(c_flags) -c $< -o $@ + +# Create object files from C++ source files. +$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk + $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) +ifeq ($(os),Windows) + $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) +else + $(Q)test -d $(dir $@) || mkdir -p $(dir $@) +endif + @echo $(MSG_COMPILING_CXX) + $(Q)$(CXX) $(cxx_flags) -c $< -o $@ + +# Preprocess and assemble: create object files from assembler source files. +$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk + $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) +ifeq ($(os),Windows) + $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) +else + $(Q)test -d $(dir $@) || mkdir -p $(dir $@) +endif + @echo $(MSG_ASSEMBLING) + $(Q)$(CC) $(a_flags) -c $< -o $@ + +# Include all dependency files to add depedency to all header files in use. +include $(dep-files) + +ifeq ($(target_type),lib) +# Archive object files into an archive +$(target): $(MAKEFILE_PATH) config.mk $(obj-y) + @echo $(MSG_ARCHIVING) + $(Q)$(AR) $(ar_flags) $@ $(obj-y) + @echo $(MSG_SIZE) + $(Q)$(SIZE) -Bxt $@ +else +ifeq ($(target_type),elf) +# Link the object files into an ELF file. Also make sure the target is rebuilt +# if the common Makefile.sam.in or project config.mk is changed. +$(target): $(linker_script) $(MAKEFILE_PATH) config.mk $(obj-y) + @echo $(MSG_LINKING) + $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@ + @echo $(MSG_SIZE) + $(Q)$(SIZE) -Ax $@ + $(Q)$(SIZE) -Bx $@ +endif +endif + +# Create extended function listing from target output file. +%.lss: $(target) + @echo $(MSG_EXTENDED_LISTING) + $(Q)$(OBJDUMP) -h -S $< > $@ + +# Create symbol table from target output file. +%.sym: $(target) + @echo $(MSG_SYMBOL_TABLE) + $(Q)$(NM) -n $< > $@ + +# Create Intel HEX image from ELF output file. +%.hex: $(target) + @echo $(MSG_IHEX_IMAGE) + $(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y) $< $@ + +# Create binary image from ELF output file. +%.bin: $(target) + @echo $(MSG_BINARY_IMAGE) + $(Q)$(OBJCOPY) -O binary $< $@ + +# Provide information about the detected host operating system. +.SECONDARY: info-os +info-os: + @echo $(MSG_INFO)$(os) build host detected + +# Build Doxygen generated documentation. +.PHONY: doc +doc: + @echo $(MSG_GENERATING_DOC) + $(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg)) + +# Clean Doxygen generated documentation. +.PHONY: cleandoc +cleandoc: + @$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC)) + $(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir)) + +# Rebuild the Doxygen generated documentation. +.PHONY: rebuilddoc +rebuilddoc: cleandoc doc diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/mrepeat.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/mrepeat.h new file mode 100644 index 00000000..7cacde3d --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/mrepeat.h @@ -0,0 +1,329 @@ +/** + * \file + * + * \brief Preprocessor macro repeating utils. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _MREPEAT_H_ +#define _MREPEAT_H_ + +/** + * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat + * + * \ingroup group_sam_utils + * + * \{ + */ + +#include "preprocessor.h" + + +//! Maximal number of repetitions supported by MREPEAT. +#define MREPEAT_LIMIT 256 + +/*! \brief Macro repeat. + * + * This macro represents a horizontal repetition construct. + * + * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT. + * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with + * the current repetition number and the auxiliary data argument. + * \param data Auxiliary data passed to macro. + * + * \return macro(0, data) macro(1, data) ... macro(count - 1, data) + */ +#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data) + +#define MREPEAT0( macro, data) +#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data) +#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data) +#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data) +#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data) +#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data) +#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data) +#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data) +#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data) +#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data) +#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data) +#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data) +#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data) +#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data) +#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data) +#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data) +#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data) +#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data) +#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data) +#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data) +#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data) +#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data) +#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data) +#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data) +#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data) +#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data) +#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data) +#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data) +#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data) +#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data) +#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data) +#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data) +#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data) +#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data) +#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data) +#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data) +#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data) +#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data) +#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data) +#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data) +#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data) +#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data) +#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data) +#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data) +#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data) +#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data) +#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data) +#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data) +#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data) +#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data) +#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data) +#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data) +#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data) +#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data) +#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data) +#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data) +#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data) +#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data) +#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data) +#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data) +#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data) +#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data) +#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data) +#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data) +#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data) +#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data) +#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data) +#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data) +#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data) +#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data) +#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data) +#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data) +#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data) +#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data) +#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data) +#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data) +#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data) +#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data) +#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data) +#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data) +#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data) +#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data) +#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data) +#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data) +#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data) +#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data) +#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data) +#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data) +#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data) +#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data) +#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data) +#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data) +#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data) +#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data) +#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data) +#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data) +#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data) +#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data) +#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data) +#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data) +#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data) +#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data) +#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data) +#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data) +#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data) +#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data) +#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data) +#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data) +#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data) +#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data) +#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data) +#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data) +#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data) +#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data) +#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data) +#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data) +#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data) +#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data) +#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data) +#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data) +#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data) +#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data) +#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data) +#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data) +#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data) +#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data) +#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data) +#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data) +#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data) +#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data) +#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data) +#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data) +#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data) +#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data) +#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data) +#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data) +#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data) +#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data) +#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data) +#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data) +#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data) +#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data) +#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data) +#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data) +#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data) +#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data) +#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data) +#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data) +#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data) +#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data) +#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data) +#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data) +#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data) +#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data) +#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data) +#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data) +#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data) +#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data) +#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data) +#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data) +#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data) +#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data) +#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data) +#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data) +#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data) +#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data) +#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data) +#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data) +#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data) +#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data) +#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data) +#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data) +#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data) +#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data) +#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data) +#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data) +#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data) +#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data) +#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data) +#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data) +#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data) +#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data) +#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data) +#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data) +#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data) +#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data) +#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data) +#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data) +#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data) +#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data) +#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data) +#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data) +#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data) +#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data) +#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data) +#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data) +#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data) +#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data) +#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data) +#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data) +#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data) +#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data) +#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data) +#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data) +#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data) +#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data) +#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data) +#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data) +#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data) +#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data) +#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data) +#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data) +#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data) +#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data) +#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data) +#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data) +#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data) +#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data) +#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data) +#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data) +#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data) +#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data) +#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data) +#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data) +#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data) +#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data) +#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data) +#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data) +#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data) +#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data) +#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data) +#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data) +#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data) +#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data) +#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data) +#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data) +#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data) +#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data) +#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data) +#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data) +#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data) +#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data) +#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data) +#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data) +#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data) +#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data) +#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data) +#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data) +#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data) +#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data) +#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data) +#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data) +#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data) +#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data) +#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data) +#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data) +#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data) + +/** + * \} + */ + +#endif // _MREPEAT_H_ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/preprocessor.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/preprocessor.h new file mode 100644 index 00000000..abf2c11e --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/preprocessor.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief Preprocessor utils. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _PREPROCESSOR_H_ +#define _PREPROCESSOR_H_ + +#include "tpaste.h" +#include "stringz.h" +#include "mrepeat.h" + + +#endif // _PREPROCESSOR_H_ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/stringz.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/stringz.h new file mode 100644 index 00000000..8e917041 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/stringz.h @@ -0,0 +1,75 @@ +/** + * \file + * + * \brief Preprocessor stringizing utils. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _STRINGZ_H_ +#define _STRINGZ_H_ + +/** + * \defgroup group_sam_utils_stringz Preprocessor - Stringize + * + * \ingroup group_sam_utils + * + * \{ + */ + +/*! \brief Stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * May be used only within macros with the token passed as an argument if the token is \#defined. + * + * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN) + * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to + * writing "A0". + */ +#define STRINGZ(x) #x + +/*! \brief Absolute stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * No restriction of use if the token is \#defined. + * + * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is + * equivalent to writing "A0". + */ +#define ASTRINGZ(x) STRINGZ(x) + +/** + * \} + */ + +#endif // _STRINGZ_H_ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/tpaste.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/tpaste.h new file mode 100644 index 00000000..68499289 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/preprocessor/tpaste.h @@ -0,0 +1,95 @@ +/** + * \file + * + * \brief Preprocessor token pasting utils. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _TPASTE_H_ +#define _TPASTE_H_ + +/** + * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste + * + * \ingroup group_sam_utils + * + * \{ + */ + +/*! \name Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. + * + * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by + * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is + * equivalent to writing U32. + */ +//! @{ +#define TPASTE2( a, b) a##b +#define TPASTE3( a, b, c) a##b##c +#define TPASTE4( a, b, c, d) a##b##c##d +#define TPASTE5( a, b, c, d, e) a##b##c##d##e +#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f +#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g +#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h +#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i +#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j +//! @} + +/*! \name Absolute Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * No restriction of use if the tokens are \#defined. + * + * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined + * as 32 is equivalent to writing U32. + */ +//! @{ +#define ATPASTE2( a, b) TPASTE2( a, b) +#define ATPASTE3( a, b, c) TPASTE3( a, b, c) +#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d) +#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e) +#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f) +#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g) +#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h) +#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i) +#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j) +//! @} + +/** + * \} + */ + +#endif // _TPASTE_H_ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/status_codes.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/status_codes.h new file mode 100644 index 00000000..225e751b --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/status_codes.h @@ -0,0 +1,103 @@ +/** + * \file + * + * \brief Status code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef STATUS_CODES_H_INCLUDED +#define STATUS_CODES_H_INCLUDED + +/* Note: this is a local workaround to avoid a pre-processor clash due to the + * lwIP macro ERR_TIMEOUT. */ +#if (defined(LWIP_HDR_ERR_H) || defined(__LWIP_ERR_H__)) && defined(ERR_TIMEOUT) +#if (ERR_TIMEOUT != -3) + +/* Internal check to make sure that the later restore of lwIP's ERR_TIMEOUT + * macro is set to the correct value. Note that it is highly improbable that + * this value ever changes in lwIP. */ +#error ASF developers: check lwip err.h new value for ERR_TIMEOUT +#endif +#undef ERR_TIMEOUT +#endif + +/** + * Status code that may be returned by shell commands and protocol + * implementations. + * + * \note Any change to these status codes and the corresponding + * message strings is strictly forbidden. New codes can be added, + * however, but make sure that any message string tables are updated + * at the same time. + */ +enum status_code { + STATUS_OK = 0, //!< Success + STATUS_ERR_BUSY = 0x19, + STATUS_ERR_DENIED = 0x1C, + STATUS_ERR_TIMEOUT = 0x12, + ERR_IO_ERROR = -1, //!< I/O error + ERR_FLUSHED = -2, //!< Request flushed from queue + ERR_TIMEOUT = -3, //!< Operation timed out + ERR_BAD_DATA = -4, //!< Data integrity check failed + ERR_PROTOCOL = -5, //!< Protocol error + ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device + ERR_NO_MEMORY = -7, //!< Insufficient memory + ERR_INVALID_ARG = -8, //!< Invalid argument + ERR_BAD_ADDRESS = -9, //!< Bad address + ERR_BUSY = -10, //!< Resource is busy + ERR_BAD_FORMAT = -11, //!< Data format not recognized + ERR_NO_TIMER = -12, //!< No timer available + ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running + ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running + ERR_ABORTED = -15, //!< Operation aborted by user + /** + * \brief Operation in progress + * + * This status code is for driver-internal use when an operation + * is currently being performed. + * + * \note Drivers should never return this status code to any + * callers. It is strictly for internal use. + */ + OPERATION_IN_PROGRESS = -128, +}; + +typedef enum status_code status_code_t; + +#if defined(LWIP_HDR_ERR_H) +#define ERR_TIMEOUT -3 +#endif + +#endif /* STATUS_CODES_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/syscalls/gcc/syscalls.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/syscalls/gcc/syscalls.c new file mode 100644 index 00000000..d74ba717 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/syscalls/gcc/syscalls.c @@ -0,0 +1,134 @@ +/** + * \file + * + * \brief Syscalls for SAM (GCC). + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include +#include +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#undef errno +extern int errno; +extern int _end; +extern int __ram_end__; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char *prev_heap; + int ramend = (int)&__ram_end__; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + if (((int)prev_heap + incr) > ramend) { + return (caddr_t) -1; + } + + heap += incr; + + return (caddr_t) prev_heap; +} + +extern int link(char *old, char *new) +{ + return -1; +} + +extern int _close(int file) +{ + return -1; +} + +extern int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + + return 0; +} + +extern int _isatty(int file) +{ + return 1; +} + +extern int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +extern void _exit(int status) +{ + asm("BKPT #0"); + for (;;); +} + +extern void _kill(int pid, int sig) +{ + return; +} + +extern int _getpid(void) +{ + return -1; +} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt new file mode 100644 index 00000000..422f7fe8 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt @@ -0,0 +1,20 @@ +/* + * Only the CMSIS required parts for ASF are included here, go to the below + * address for the full package: + * http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php + * + * The library file thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math_softfp.a was generated by ATMEL, which + * is support -mfloat-abi=softfp compiler flag, and this is also the default selection for device that + * have FPU module and enabled. + * If customer want to use -mfloat-abi=hard compiler flag, the project compile/link flag and link library + * should be manual modified. The library thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a is used for + * -mfloat-abi=hard configration. + * + * __CORTEX_SC is not defined for cortex-m0+, and may cause compiler warning, so the include file + * thirdparty/CMSIS/Include/core_cmInstr.h was modified to void such warning. + * Modified from: + * #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + * to: + * #if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300)) + * + */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf new file mode 100644 index 0000000000000000000000000000000000000000..c67c8672dbf9fdcf4bf64a22791e24c9f1688d1d GIT binary patch literal 179946 zcmdSARdgK7vaTzzm@Q_qn3*kRvY1&dW@gD2Gcz+<%*@QpXfZQOSN7a2IbP5i3js^~jb^w69wY38QBg>yI(t390 z;#Nl1A7*|Z0t^X0x&gj^eBht~R)&9E{5JM)zW(^26SQ`;av)%#lQcE7*C1f}ZH|C} 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zyC%;~Gnjv(J^xfz{&8YH&4+xdk^GaD`P6%ifz)^FxY_H$*SRgF2vPhD2kfoMQdMWH z48K2~(94ifX-D(|R=TH)r4>CLh+MxA^2-|4 z00+5UQEm(1fC4z601k4yr`#WagWSd`%K0B|4y97q5M62O53aFF{liu{lO4kUmB3E)5iIFOVMFuCvf{kUKd zr2`D2bbvvW4lucYqud{*0}P^c{Mq+VZcFI^lgA7c<-hLdB!^2`NS%@AC30XeiRt{bvjeqNn?R$xh_Hi={i)-%0&7<Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
    + * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
    + * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
    + *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
    + * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
    + *     pData[i*numCols + j]
+ *
    + * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
    + * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
    + * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
    + *     ARM_MATH_SIZE_MISMATCH
+ *
    + * Otherwise the functions return + * 
    + *     ARM_MATH_SUCCESS
+ *
    + * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
    + *     ARM_MATH_MATRIX_CHECK
+ *
    + * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
    +   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
    + * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
    +   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
    + * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
    +   *      x1 = x0 - f(x0)/f'(x0)
+   *
    + * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
    +   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
    + */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
    +   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
    + * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
    +   *     XF = floor(x)
+   *     YF = floor(y)
+   *
    + * \par + * The interpolated output point is computed as: + * 
    +   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
    + * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 00000000..94212eb8 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 00000000..2d9db15a --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/cmsis_version.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/cmsis_version.h new file mode 100644 index 00000000..3b6bae4b --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.4.0 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/core_cm7.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/core_cm7.h new file mode 100644 index 00000000..a14dc623 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h new file mode 100644 index 00000000..01422033 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a new file mode 100644 index 0000000000000000000000000000000000000000..b01e81b5a55fb53cab77db33891053bf6a19f614 GIT binary patch literal 3199620 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zk$x6Y={!set}2pj1Q&P!(GcZtK=(VeSj*(`6Q)&9n>lgD+)0xUv{(!NQ@Clv(PAHQ zv6f%qbC|=@U+mho{DkuI?p&1Rh;*V!S@-Tex+lhzCHf8NUxg*3u|i86cHZnSNvqhRWR85);jMR^+1#`>?Uz|MD z!;d7QA4b@Lszg?%|8N^`xS-9a@Iw%ePEi{z2RR=&7!4>cTAElEztV1nAK5O;ZvJm> zm_=K(L1a7dS(KsNLAd1|nV}sb^Wo9eLT)~5OQd`p+idhk;cq7u(CKxv;x&jvA_7mI z0=auMWiHH0Q0(TArwtO1+@YGnB`e|PDA&HfOL*3K&fdVLX*kx_YL*k;`;kG>Y)Dvtjo zY_n+YNPlIEXF@}4v$UzQO{OAd*=F6dN%ov;9I6rQ|2EDa`#tTFJh#LH*=N~rnBG&^ zS2#d;n(!>)XyJGv_l@Ow?Gx!IA@bTKUMsvo_zmH=gm()c5?-Uf zwDv>(0pbSrNS$O%Y^*T&-9yww+ZhM9?T9kRryMJe9ba; + * - SAMV71-Xplained-Ultra
    + * - SAME70-Xplained-Pro
    + * + * \section Description + * + * The acc_irq is aimed to demonstrate the usage of ACC peripheral with + * interrupt support. The DAC0 and AD0 are selected as two inputs. + * The user can change the output voltage of DAC0 and change the voltage + * on AD0. + * + * The output voltage of DAC0 is ranged from (1/6)*ADVREF to (5/6)*ADVREF,and + * the input voltage of AD0 is ranged from 0 to ADVREF. + * + * The comparison event would be generated if the voltage of one input is + * changed across the voltage of the other input. Both bigger and less events + * could be triggered by default. + * + * \section Usage + * + * -# Build the program and download it inside the evaluation board. + * -# On the computer, open and configure a terminal application + * (e.g. HyperTerminal on Microsoft Windows) with these settings: + * - 115200 bauds + * - 8 bits of data + * - No parity + * - 1 stop bit + * - No flow control + * -# In the terminal window, the + * following text should appear (values depend on the board and chip used): + * \code + * -- ACC IRQ Example xxx -- + * -- xxxxxx-xx + * -- Compiled: xxx xx xxxx xx:xx:xx -- + * -- Menu Choices for this example-- + * -- s: Set new DAC0 output voltage.-- + * -- v: Get voltage on potentiometer.-- + * -- m: Display this menu again.-- + * \endcode + * -# Input command according to the menu. + * -# Change voltage on AD0 to see what comparison event happen. + * + */ +/* + * Support and FAQ: visit     Microchip Support + */ + +#include "asf.h" +#include "stdio_serial.h" +#include "conf_board.h" +#include "conf_clock.h" + +/** Reference voltage for DACC,in mv */ +#define VOLT_REF (3300) + +/** The maximal digital value */ +#define MAX_DIGITAL (4095) + +/** The DAC Channel value */ +#define DACC_CHANNEL_0 0 + +/** Analog control value */ +#define DACC_ANALOG_CONTROL (DACC_ACR_IBCTLCH0(0x02) \ + | DACC_ACR_IBCTLCH1(0x02)) + +#define STRING_EOL "\r" +#define STRING_HEADER "-- ACC IRQ Example --\r\n" \ + "-- "BOARD_NAME" --\r\n" \ + "-- Compiled: "__DATE__" "__TIME__" --"STRING_EOL + +/** + * Interrupt handler for the ACC. + */ +void ACC_Handler(void) +{ + uint32_t ul_status; + + ul_status = acc_get_interrupt_status(ACC); + + /* Compare Output Interrupt */ + if ((ul_status & ACC_ISR_CE) == ACC_ISR_CE) { + if (acc_get_comparison_result(ACC)) { + puts("-ISR- Voltage Comparison Result: AD0 > DAC0\r"); + } else { + puts("-ISR- Voltage Comparison Result: AD0 < DAC0\r"); + } + } +} + +/** + * Configure UART console. + */ +static void configure_console(void) +{ + const usart_serial_options_t uart_serial_options = { + .baudrate = CONF_UART_BAUDRATE, +#ifdef CONF_UART_CHAR_LENGTH + .charlength = CONF_UART_CHAR_LENGTH, +#endif + .paritytype = CONF_UART_PARITY, +#ifdef CONF_UART_STOP_BITS + .stopbits = CONF_UART_STOP_BITS, +#endif + }; + + /* Configure console UART. */ + sysclk_enable_peripheral_clock(CONSOLE_UART_ID); + stdio_serial_init(CONF_UART, &uart_serial_options); +} + +/** + * \brief Display main menu + */ +static void dsplay_menu(void) +{ + puts("-- Menu Choices for this example--\n\r" + " s: Set new DAC0 output voltage.\n\r" + " v: Get voltage on potentiometer.\n\r" + " m: Display this menu again.\r"); +} + +/** + * \brief Get voltage from user input, the input range is: + * (1/6)*ADVREF~(5/6)*ADVREF (mv) + */ +static int16_t get_input_voltage(void) +{ + uint32_t i = 0, uc_key; + int16_t us_value = 0; + int8_t c_length = 0; + int8_t ac_str_temp[5] = { 0 }; + + while (1) { + while (usart_read(CONSOLE_UART, &uc_key)) { + } + if (uc_key == '\n' || uc_key == '\r') { + puts("\r"); + break; + } + + if ('0' <= uc_key && '9' >= uc_key) { + printf("%c", uc_key); + ac_str_temp[i++] = uc_key; + + if (i >= 4) + break; + } + } + + ac_str_temp[i] = '\0'; + /* Input string length */ + c_length = i; + us_value = 0; + + /* Convert string to integer */ + for (i = 0; i < 4; i++) { + if (ac_str_temp[i] != '0') { + switch (c_length - i - 1) { + case 0: + us_value += (ac_str_temp[i] - '0'); + break; + case 1: + us_value += (ac_str_temp[i] - '0') * 10; + break; + case 2: + us_value += (ac_str_temp[i] - '0') * 100; + break; + case 3: + us_value += (ac_str_temp[i] - '0') * 1000; + break; + } + } + } + + if (us_value > (5 * VOLT_REF / 6) || us_value < (1 * VOLT_REF / 6)) { + return -1; + } + + return us_value; +} + +/** + * \brief ACC example application entry point. + * + * \return Unused (ANSI-C compatibility). + */ +int main(void) +{ + uint32_t uc_key; + int16_t s_volt = 0; + uint32_t ul_value = 0; + volatile uint32_t ul_status = 0x0; + int32_t l_volt_dac0 = 0; + + /* Initialize the system */ + sysclk_init(); + board_init(); + + /* Initialize debug console */ + configure_console(); + + /* Output example information */ + puts(STRING_HEADER); + + /* Initialize DACC */ + /* Enable clock for DACC */ + pmc_enable_periph_clk(ID_DACC); + /* Reset DACC registers */ + dacc_reset(DACC); + /* External trigger mode disabled. DACC in free running mode. */ + dacc_disable_trigger(DACC, DACC_CHANNEL_0); + /* Half word transfer mode */ + dacc_set_transfer_mode(DACC, 0); +#if (SAM3S) || (SAM3XA) + /* Power save: + * sleep mode - 0 (disabled) + * fast wakeup - 0 (disabled) + */ + dacc_set_power_save(DACC, 0, 0); +#endif + + /* Enable output channel DACC_CHANNEL */ + dacc_enable_channel(DACC, DACC_CHANNEL_0); + /* Setup analog current */ + dacc_set_analog_control(DACC, DACC_ANALOG_CONTROL); + + /* Set DAC0 output at ADVREF/2. The DAC formula is: + * + * (5/6 * VOLT_REF) - (1/6 * VOLT_REF) volt - (1/6 * VOLT_REF) + * ----------------------------------- = -------------------------- + * MAX_DIGITAL digit + * + * Here, digit = MAX_DIGITAL/2 + */ + dacc_write_conversion_data(DACC, MAX_DIGITAL / 2, DACC_CHANNEL_0); + l_volt_dac0 = (MAX_DIGITAL / 2) * (2 * VOLT_REF / 3) / MAX_DIGITAL + + VOLT_REF / 6; + + /* Enable clock for AFEC */ + afec_enable(AFEC0); + + struct afec_config afec_cfg; + + afec_get_config_defaults(&afec_cfg); + /* Initialize AFEC */ + afec_init(AFEC0, &afec_cfg); + + struct afec_ch_config afec_ch_cfg; + afec_ch_get_config_defaults(&afec_ch_cfg); + afec_ch_cfg.gain = AFEC_GAINVALUE_0; + afec_ch_set_config(AFEC0, AFEC_CHANNEL_POTENTIOMETER, &afec_ch_cfg); + /* + * Because the internal ADC offset is 0x200, it should cancel it and shift + * down to 0. + */ + afec_channel_set_analog_offset(AFEC0, AFEC_CHANNEL_POTENTIOMETER, 0x200); + + afec_set_trigger(AFEC0, AFEC_TRIG_SW); + + /* Enable channel for potentiometer. */ + afec_channel_enable(AFEC0, AFEC_CHANNEL_POTENTIOMETER); + + /* Enable clock for ACC */ + pmc_enable_periph_clk(ID_ACC); + + /* Initialize ACC */ + acc_init(ACC, ACC_MR_SELPLUS_AFE0_AD0, ACC_MR_SELMINUS_DAC0, + ACC_MR_EDGETYP_ANY, ACC_MR_INV_DIS); + + /* Enable ACC interrupt */ + NVIC_EnableIRQ(ACC_IRQn); + + /* Enable */ + acc_enable_interrupt(ACC); + + dsplay_menu(); + + while (1) { + while (usart_read(CONSOLE_UART, &uc_key)) { + } + + printf("input: %c\r\n", uc_key); + + switch (uc_key) { + case 's': + case 'S': + printf("Input DAC0 output voltage (%d~%d mv): ", + (VOLT_REF / 6), (VOLT_REF * 5 / 6)); + s_volt = get_input_voltage(); + puts("\r"); + + if (s_volt > 0) { + l_volt_dac0 = s_volt; + /* The DAC formula is: + * + * (5/6 * VOLT_REF) - (1/6 * VOLT_REF) volt - (1/6 * VOLT_REF) + * ----------------------------------- = -------------------------- + * MAX_DIGITAL digit + * + */ + ul_value = ((s_volt - (VOLT_REF / 6)) + * (MAX_DIGITAL * 6) / 4) / VOLT_REF; + dacc_write_conversion_data(DACC, ul_value, DACC_CHANNEL_0); + puts("-I- Set ok\r"); + } else { + puts("-I- Input voltage is invalid\r"); + } + break; + case 'v': + case 'V': + /* Start conversion */ + afec_start_software_conversion(AFEC0); + ul_status = afec_get_interrupt_status(AFEC0); + while ((ul_status & AFEC_ISR_EOC0) != AFEC_ISR_EOC0) { + ul_status = afec_get_interrupt_status(AFEC0); + } + /* Conversion is done */ + ul_value = afec_channel_get_value(AFEC0, AFEC_CHANNEL_POTENTIOMETER); + + /* + * Convert AFEC sample data to voltage value: + * voltage value = (sample data / max. resolution) * reference voltage + */ + s_volt = (ul_value * VOLT_REF) / MAX_DIGITAL; + printf("-I- Voltage on potentiometer(AD0) is %d mv\n\r", s_volt); + printf("-I- Voltage on DAC0 is %ld mv \n\r", (long)l_volt_dac0); + break; + + case 'm': + case 'M': + dsplay_menu(); + break; + } + } +} diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/asf.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/asf.h new file mode 100644 index 00000000..b40a1d0c --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/asf.h @@ -0,0 +1,121 @@ +/** + * \file + * + * \brief Autogenerated API include file for the Atmel Software Framework (ASF) + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef ASF_H +#define ASF_H + +/* + * This file includes all API header files for the selected drivers from ASF. + * Note: There might be duplicate includes required by more than one driver. + * + * The file is automatically generated and will be re-written when + * running the ASF driver selector tool. Any changes will be discarded. + */ + +// From module: ACC - Analog Comparator Controller +#include + +// From module: AFEC - Analog-Front-End Controller +#include + +// From module: Common SAM compiler driver +#include +#include + +// From module: DACC - Digital-to-Analog Converter +#include + +// From module: GPIO - General purpose Input/Output +#include + +// From module: Generic board support +#include + +// From module: IOPORT - General purpose I/O service +#include + +// From module: Interrupt management - SAM implementation +#include + +// From module: MPU - Memory Protect Unit +#include + +// From module: PIO - Parallel Input/Output Controller +#include + +// From module: PMC - Power Management Controller +#include +#include + +// From module: Part identification macros +#include + +// From module: SAM FPU driver +#include + +// From module: SAME70 XPLD LED support enabled +#include + +// From module: Sleep manager - SAM implementation +#include +#include + +// From module: Standard serial I/O (stdio) - SAM implementation +#include + +// From module: System Clock Control - SAME70 implementation +#include + +// From module: UART - Univ. Async Rec/Trans +#include + +// From module: USART - Serial interface - SAM implementation for devices with both UART and USART +#include + +// From module: USART - Univ. Syn Async Rec/Trans +#include + +// From module: pio_handler support enabled +#include + +#endif // ASF_H diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_board.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_board.h new file mode 100644 index 00000000..b6e88f4b --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_board.h @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Board configuration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CONF_BOARD_H_INCLUDED +#define CONF_BOARD_H_INCLUDED + +/* Enable ICache and DCache */ +#define CONF_BOARD_ENABLE_CACHE + +/** Enable Com Port. */ +#define CONF_BOARD_UART_CONSOLE + +#endif /* CONF_BOARD_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_clock.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_clock.h new file mode 100644 index 00000000..807969fc --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_clock.h @@ -0,0 +1,94 @@ +/** + * \file + * + * \brief SAME70 clock configuration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CONF_CLOCK_H_INCLUDED +#define CONF_CLOCK_H_INCLUDED + +// ===== System Clock (MCK) Source Options +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS +#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK + +// ===== Processor Clock (HCLK) Prescaler Options (Fhclk = Fsys / (SYSCLK_PRES)) +#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3 + +// ===== System Clock (MCK) Division Options (Fmck = Fhclk / (SYSCLK_DIV)) +#define CONFIG_SYSCLK_DIV 2 + +// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div) +// Use mul and div effective values here. +#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL +#define CONFIG_PLL0_MUL 25 +#define CONFIG_PLL0_DIV 1 + +// ===== UPLL (UTMI) Hardware fixed at 480 MHz. + +// ===== USB Clock Source Options (Fusb = FpllX / USB_div) +// Use div effective value here. +//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 +#define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL +#define CONFIG_USBCLK_DIV 1 + +// ===== Target frequency (Processor clock) +// - XTAL frequency: 12MHz +// - System clock source: PLLA +// - System clock prescaler: 1 (divided by 1) +// - System clock divider: 2 (divided by 2) +// - PLLA source: XTAL +// - PLLA output: XTAL * 25 / 1 +// - Processor clock: 12 * 25 / 1 / 1 = 300MHz +// - System clock: 300 / 2 = 150MHz +// ===== Target frequency (USB Clock) +// - USB clock source: UPLL +// - USB clock divider: 1 (not divided) +// - UPLL frequency: 480MHz +// - USB clock: 480 / 1 = 480MHz + +#endif /* CONF_CLOCK_H_INCLUDED */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_sleepmgr.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_sleepmgr.h new file mode 100644 index 00000000..1d169755 --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_sleepmgr.h @@ -0,0 +1,42 @@ +/** + * \file + * + * \brief Chip-specific sleep manager configuration + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef CONF_SLEEPMGR_H +#define CONF_SLEEPMGR_H + +// Sleep manager options +#define CONFIG_SLEEPMGR_ENABLE + +#endif /* CONF_SLEEPMGR_H */ diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_uart_serial.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_uart_serial.h new file mode 100644 index 00000000..86f9b09e --- /dev/null +++ b/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_uart_serial.h @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief USART Serial Configuration + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CONF_USART_SERIAL_H_INCLUDED +#define CONF_USART_SERIAL_H_INCLUDED + +/** UART Interface */ +#define CONF_UART CONSOLE_UART +/** Baudrate setting */ +#define CONF_UART_BAUDRATE (115200UL) +/** Character length setting */ +#define CONF_UART_CHAR_LENGTH US_MR_CHRL_8_BIT +/** Parity setting */ +#define CONF_UART_PARITY US_MR_PAR_NO +/** Stop bits setting */ +#define CONF_UART_STOP_BITS US_MR_NBSTOP_1_BIT + +#endif/* CONF_USART_SERIAL_H_INCLUDED */ From c982482211b057c850229fad573428218a964f75 Mon Sep 17 00:00:00 2001 From: felipebpl Date: Sun, 5 Jun 2022 20:58:41 -0300 Subject: [PATCH 02/23] reorganizando pasta --- .../ACC_EXAMPLE1.componentinfo.xml | 0 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.../src/ASF/thirdparty/CMSIS/Lib/license.txt | 0 .../src/ASF/thirdparty/CMSIS/README.txt | 0 .../{ACC_EXAMPLE1 => }/src/acc_example_canopus.c | 0 .../ACC/ACC_EXAMPLE1/{ACC_EXAMPLE1 => }/src/asf.h | 0 .../{ACC_EXAMPLE1 => }/src/config/conf_board.h | 0 .../{ACC_EXAMPLE1 => }/src/config/conf_clock.h | 0 .../{ACC_EXAMPLE1 => }/src/config/conf_sleepmgr.h | 0 .../src/config/conf_uart_serial.h | 0 216 files changed, 0 insertions(+), 0 deletions(-) rename Perifericos-uC/ACC/ACC_EXAMPLE1/{ACC_EXAMPLE1 => }/ACC_EXAMPLE1.componentinfo.xml (100%) rename Perifericos-uC/ACC/ACC_EXAMPLE1/{ACC_EXAMPLE1 => }/ACC_EXAMPLE1.cproj (100%) rename Perifericos-uC/ACC/ACC_EXAMPLE1/{ACC_EXAMPLE1 => }/src/ASF/common/boards/board.h (100%) rename Perifericos-uC/ACC/ACC_EXAMPLE1/{ACC_EXAMPLE1 => }/src/ASF/common/services/clock/genclk.h (100%) rename Perifericos-uC/ACC/ACC_EXAMPLE1/{ACC_EXAMPLE1 => }/src/ASF/common/services/clock/osc.h (100%) rename Perifericos-uC/ACC/ACC_EXAMPLE1/{ACC_EXAMPLE1 => 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similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/read.c rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/stdio/read.c diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/write.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/stdio/write.c similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/common/utils/stdio/write.c rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/stdio/write.c diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/init.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/init.c similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/init.c rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/init.c diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/led.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/led.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/led.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/led.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/same70_xplained.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/same70_xplained.h similarity index 100% rename from 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a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/icm.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/icm.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/icm.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/icm.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/isi.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/isi.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/isi.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/isi.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/matrix.h 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Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/mcan1.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/mcan1.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioa.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioa.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioa.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioa.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piob.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piob.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piob.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piob.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piod.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piod.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piod.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/piod.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioe.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioe.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioe.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pioe.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pmc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pmc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pmc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pmc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtt.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtt.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtt.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rtt.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/sdramc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/sdramc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/sdramc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/sdramc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/smc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/smc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/smc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/smc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/ssc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/ssc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/ssc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/ssc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/supc.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/supc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/supc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/supc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc0.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc0.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc0.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc1.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc1.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc1.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc2.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc2.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc2.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc2.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc3.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc3.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc3.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/tc3.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/trng.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/trng.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/trng.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/trng.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart0.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart0.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart0.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart1.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart1.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart1.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart1.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart2.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart2.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart2.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart2.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart3.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart3.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart3.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart3.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart4.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart4.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart4.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/uart4.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart0.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart0.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart0.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart0.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usart1.h 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from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/utmi.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/utmi.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/utmi.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/utmi.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/wdt.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/wdt.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/wdt.h rename to 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a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Lib/license.txt b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Lib/license.txt similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Lib/license.txt rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/Lib/license.txt diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/README.txt b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/README.txt similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/README.txt rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/thirdparty/CMSIS/README.txt diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/acc_example_canopus.c b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/acc_example_canopus.c similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/acc_example_canopus.c rename to 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a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_sleepmgr.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_sleepmgr.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_sleepmgr.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_sleepmgr.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_uart_serial.h b/Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_uart_serial.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1/src/config/conf_uart_serial.h rename to Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_uart_serial.h From 2c13f077086743868716949c0916dd71032d2075 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 21:00:10 -0300 Subject: [PATCH 03/23] Create README.md --- Perifericos-uC/ACC/README.md | 1 + 1 file changed, 1 insertion(+) create mode 100644 Perifericos-uC/ACC/README.md diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/Perifericos-uC/ACC/README.md @@ -0,0 +1 @@ + From 6998c3f81decc440e1356e650c8662c90736fe02 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 21:02:44 -0300 Subject: [PATCH 04/23] Update README.md --- Perifericos-uC/ACC/README.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index 8b137891..1191a7b7 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -1 +1,7 @@ +# Analog Comparator Controller (ACC) +--- +Configura o comparador analógico e gera uma interrupção dependendo nas configurações do usuário. +# Conexão e configuração +--- +Não é necessária From 3823dc8fc0024cc395b0942c1490e93a8bf21e10 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 21:16:22 -0300 Subject: [PATCH 05/23] Update README.md --- Perifericos-uC/ACC/README.md | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index 1191a7b7..ddb888ce 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -1,7 +1,20 @@ # Analog Comparator Controller (ACC) ---- Configura o comparador analógico e gera uma interrupção dependendo nas configurações do usuário. # Conexão e configuração ---- Não é necessária + +# Explicação +![image](https://user-images.githubusercontent.com/62957465/172076354-d0085309-cc7c-4098-94a7-52673859c7b0.png) + +O DAC0 e o AD0 são selecionados como duas entradas. O usuário pode alterar a tensão de saída do DAC0 e alterar a tensão do AD0. + +A tensão de saída de DAC0 varia de (1/6)*ADVREF a (5/6)*ADVREF, e a tensão de entrada de AD0 varia de 0 a ADVREF. + +O evento de comparação seria gerado se a tensão de uma entrada fosse alterada pela tensão da outra entrada. Tanto eventos maiores quanto menores podem ser acionados por padrão. + +# Referências + +- Atmel Datasheet: https://www.tme.eu/Document/b85c146da65ff583bac4b0dfc098ee7b/ATSAME70-DTE.pdf + +- ASF Source Code Documentation https://asf.microchip.com/docs/3.49.1/sam.drivers.acc.example.same70_xplained/html/index.html From a1a160e3753e7ee56c334e9165e2abd66a1e1263 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 22:11:32 -0300 Subject: [PATCH 06/23] Update README.md --- Perifericos-uC/ACC/README.md | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index ddb888ce..b3e749e5 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -2,17 +2,44 @@ Configura o comparador analógico e gera uma interrupção dependendo nas configurações do usuário. # Conexão e configuração -Não é necessária +- Não é necessária # Explicação ![image](https://user-images.githubusercontent.com/62957465/172076354-d0085309-cc7c-4098-94a7-52673859c7b0.png) +O comparador analógico incorpora dois multiplexadores de 8 para 1 que geram duas entradas internas. Essas entradas são comparadas, resultando em uma saída de comparação. + O DAC0 e o AD0 são selecionados como duas entradas. O usuário pode alterar a tensão de saída do DAC0 e alterar a tensão do AD0. A tensão de saída de DAC0 varia de (1/6)*ADVREF a (5/6)*ADVREF, e a tensão de entrada de AD0 varia de 0 a ADVREF. O evento de comparação seria gerado se a tensão de uma entrada fosse alterada pela tensão da outra entrada. Tanto eventos maiores quanto menores podem ser acionados por padrão. + +### Main + +### Interrupção + +O ACC tem uma linha de interrupção conectada ao Interrupt Controller (IC). Para lidar com interrupções, o IC deve ser programado antes de configurar o ACC. + +/** + * Interrupt handler for the ACC. + */ +void ACC_Handler(void) +{ + uint32_t ul_status; + + ul_status = acc_get_interrupt_status(ACC); + + /* Compare Output Interrupt */ + if ((ul_status & ACC_ISR_CE) == ACC_ISR_CE) { + if (acc_get_comparison_result(ACC)) { + puts("-ISR- Voltage Comparison Result: AD0 > DAC0\r"); + } else { + puts("-ISR- Voltage Comparison Result: AD0 < DAC0\r"); + } + } + # Referências - Atmel Datasheet: https://www.tme.eu/Document/b85c146da65ff583bac4b0dfc098ee7b/ATSAME70-DTE.pdf From 0e07b9c211686628b3668f6fde1d42a7e0eecbd4 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 22:12:23 -0300 Subject: [PATCH 07/23] Update README.md --- Perifericos-uC/ACC/README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index b3e749e5..e9484102 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -22,6 +22,7 @@ O evento de comparação seria gerado se a tensão de uma entrada fosse alterada O ACC tem uma linha de interrupção conectada ao Interrupt Controller (IC). Para lidar com interrupções, o IC deve ser programado antes de configurar o ACC. +``` /** * Interrupt handler for the ACC. */ @@ -39,6 +40,7 @@ void ACC_Handler(void) puts("-ISR- Voltage Comparison Result: AD0 < DAC0\r"); } } +``` # Referências From 4b7adf95dbb8167e17d56b15b132a9312c57de64 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 22:13:14 -0300 Subject: [PATCH 08/23] Update README.md --- Perifericos-uC/ACC/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index e9484102..1f6f9da2 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -22,7 +22,7 @@ O evento de comparação seria gerado se a tensão de uma entrada fosse alterada O ACC tem uma linha de interrupção conectada ao Interrupt Controller (IC). Para lidar com interrupções, o IC deve ser programado antes de configurar o ACC. -``` +```c /** * Interrupt handler for the ACC. */ From 733729420daa903b70b76a9616a93137c55abf73 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 22:53:51 -0300 Subject: [PATCH 09/23] Update README.md --- Perifericos-uC/ACC/README.md | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index 1f6f9da2..f657f35c 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -1,10 +1,10 @@ # Analog Comparator Controller (ACC) Configura o comparador analógico e gera uma interrupção dependendo nas configurações do usuário. -# Conexão e configuração +## Conexão e configuração - Não é necessária -# Explicação +## Explicação ![image](https://user-images.githubusercontent.com/62957465/172076354-d0085309-cc7c-4098-94a7-52673859c7b0.png) O comparador analógico incorpora dois multiplexadores de 8 para 1 que geram duas entradas internas. Essas entradas são comparadas, resultando em uma saída de comparação. @@ -30,16 +30,18 @@ void ACC_Handler(void) { uint32_t ul_status; + /* Leitura do status do periférico */ ul_status = acc_get_interrupt_status(ACC); - /* Compare Output Interrupt */ + /* Comparação da interrupção de saída*/ if ((ul_status & ACC_ISR_CE) == ACC_ISR_CE) { - if (acc_get_comparison_result(ACC)) { + if (acc_get_comparison_result(ACC)) { puts("-ISR- Voltage Comparison Result: AD0 > DAC0\r"); } else { puts("-ISR- Voltage Comparison Result: AD0 < DAC0\r"); } } +} ``` # Referências From dae4e15943cd1d781aa0e08cccf7a1d21d671b5c Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 22:56:37 -0300 Subject: [PATCH 10/23] Update README.md --- Perifericos-uC/ACC/README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index f657f35c..e0335b34 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -16,7 +16,7 @@ A tensão de saída de DAC0 varia de (1/6)*ADVREF a (5/6)*ADVREF, e a tensão de O evento de comparação seria gerado se a tensão de uma entrada fosse alterada pela tensão da outra entrada. Tanto eventos maiores quanto menores podem ser acionados por padrão. -### Main +#### Main ### Interrupção @@ -44,7 +44,7 @@ void ACC_Handler(void) } ``` -# Referências +### Referências - Atmel Datasheet: https://www.tme.eu/Document/b85c146da65ff583bac4b0dfc098ee7b/ATSAME70-DTE.pdf From 326cbb080687b63d2aa537448be7dbe8eb8d6689 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 23:14:17 -0300 Subject: [PATCH 11/23] Update README.md --- Perifericos-uC/ACC/README.md | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index e0335b34..415e9f9e 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -4,7 +4,7 @@ Configura o comparador analógico e gera uma interrupção dependendo nas config ## Conexão e configuração - Não é necessária -## Explicação +## Diagrama de Blocos ![image](https://user-images.githubusercontent.com/62957465/172076354-d0085309-cc7c-4098-94a7-52673859c7b0.png) O comparador analógico incorpora dois multiplexadores de 8 para 1 que geram duas entradas internas. Essas entradas são comparadas, resultando em uma saída de comparação. @@ -15,8 +15,15 @@ A tensão de saída de DAC0 varia de (1/6)*ADVREF a (5/6)*ADVREF, e a tensão de O evento de comparação seria gerado se a tensão de uma entrada fosse alterada pela tensão da outra entrada. Tanto eventos maiores quanto menores podem ser acionados por padrão. +## Analog Comparator Controller - ACC +O ACC é um módulo que compara duas tensões de entrada analógicas e emite um nível de sinal indicando qual das entradas é maior ou menor. Um comparador analógico é basicamente um amplificador sem feedback e, portanto, tem ganho muito alto. -#### Main +![image](https://user-images.githubusercontent.com/62957465/172083444-b36941b3-36df-4993-ab29-b3cab1f9e7a7.png) + +Quando a tensão na entrada positiva (Vin0) é maior que a tensão na entrada negativa (Vin1), então a tensão de saída (VOUT) está saturada para seu alimentação positiva (+VSUPPLY), caso contrário, a saída é saturada com alimentação negativa (-VSUPPLY). Em microcontroladores, como não há tensão de alimentação negativa, GND (nível de terra) é tomado como –VSUPPLY e VCC nível é considerado +VSUPPLY. + + +### Main ### Interrupção @@ -44,7 +51,7 @@ void ACC_Handler(void) } ``` -### Referências +## Referências - Atmel Datasheet: https://www.tme.eu/Document/b85c146da65ff583bac4b0dfc098ee7b/ATSAME70-DTE.pdf From c4b46b167b6c9fcf2af87b45294d0577cc54c615 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 23:26:50 -0300 Subject: [PATCH 12/23] Update README.md --- Perifericos-uC/ACC/README.md | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index 415e9f9e..26cb1aeb 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -7,8 +7,6 @@ Configura o comparador analógico e gera uma interrupção dependendo nas config ## Diagrama de Blocos ![image](https://user-images.githubusercontent.com/62957465/172076354-d0085309-cc7c-4098-94a7-52673859c7b0.png) -O comparador analógico incorpora dois multiplexadores de 8 para 1 que geram duas entradas internas. Essas entradas são comparadas, resultando em uma saída de comparação. - O DAC0 e o AD0 são selecionados como duas entradas. O usuário pode alterar a tensão de saída do DAC0 e alterar a tensão do AD0. A tensão de saída de DAC0 varia de (1/6)*ADVREF a (5/6)*ADVREF, e a tensão de entrada de AD0 varia de 0 a ADVREF. @@ -16,7 +14,15 @@ A tensão de saída de DAC0 varia de (1/6)*ADVREF a (5/6)*ADVREF, e a tensão de O evento de comparação seria gerado se a tensão de uma entrada fosse alterada pela tensão da outra entrada. Tanto eventos maiores quanto menores podem ser acionados por padrão. ## Analog Comparator Controller - ACC -O ACC é um módulo que compara duas tensões de entrada analógicas e emite um nível de sinal indicando qual das entradas é maior ou menor. Um comparador analógico é basicamente um amplificador sem feedback e, portanto, tem ganho muito alto. + +O ACC configura o Comparador Analógico e gera uma interrupção de acordo com as configurações do aplicativo do usuário. + +O comparador analógico incorpora 8 a 1 multiplexadores em ambos suas entradas. O Comparador Analógico compara duas tensões de entrada analógicas, e o resultado dessa comparação fornece uma comparação saída (emite um nível de sinal indicando qual das entradas é maior ou menor) e uma interrupção pode ser gerada de acordo. Um comparador analógico é basicamente um amplificador sem feedback e, portanto, tem ganho muito alto. + +O aplicativo do usuário pode selecionar uma alta velocidade ou +opção de baixa potência, o nível de histerese, detecção de borda e polaridade. + +O ACC também pode gerar um evento de comparação que pode ser usado pelo Pulse Width Modulation (PWM). ![image](https://user-images.githubusercontent.com/62957465/172083444-b36941b3-36df-4993-ab29-b3cab1f9e7a7.png) From fb8c11ccd6cc40609f60fb9c94f594fe79788684 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 23:45:51 -0300 Subject: [PATCH 13/23] Update README.md --- Perifericos-uC/ACC/README.md | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index 26cb1aeb..2449e657 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -19,8 +19,13 @@ O ACC configura o Comparador Analógico e gera uma interrupção de acordo com a O comparador analógico incorpora 8 a 1 multiplexadores em ambos suas entradas. O Comparador Analógico compara duas tensões de entrada analógicas, e o resultado dessa comparação fornece uma comparação saída (emite um nível de sinal indicando qual das entradas é maior ou menor) e uma interrupção pode ser gerada de acordo. Um comparador analógico é basicamente um amplificador sem feedback e, portanto, tem ganho muito alto. -O aplicativo do usuário pode selecionar uma alta velocidade ou -opção de baixa potência, o nível de histerese, detecção de borda e polaridade. +O usuário pode selecionar uma alta velocidade ou opção de baixa potência, o nível de histerese, detecção de borda e polaridade. + +Quando as configurações do comparador analógico são modificadas, a saída da célula analógica pode ser inválida. + +Um sinalizador de comparação é acionado por um evento na saída do comparador analógico e uma interrupção é gerada. + +O evento na saída do comparador analógico pode ser selecionado entre `` fall edge``, flanco ascendente ou qualquer flanco. O ACC também pode gerar um evento de comparação que pode ser usado pelo Pulse Width Modulation (PWM). @@ -28,7 +33,6 @@ O ACC também pode gerar um evento de comparação que pode ser usado pelo Pulse Quando a tensão na entrada positiva (Vin0) é maior que a tensão na entrada negativa (Vin1), então a tensão de saída (VOUT) está saturada para seu alimentação positiva (+VSUPPLY), caso contrário, a saída é saturada com alimentação negativa (-VSUPPLY). Em microcontroladores, como não há tensão de alimentação negativa, GND (nível de terra) é tomado como –VSUPPLY e VCC nível é considerado +VSUPPLY. - ### Main ### Interrupção From fd5d3cc0f910ab9d7ed2e193b9bdb18916382554 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 23:46:47 -0300 Subject: [PATCH 14/23] Update README.md --- Perifericos-uC/ACC/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index 2449e657..42918861 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -25,7 +25,7 @@ Quando as configurações do comparador analógico são modificadas, a saída da Um sinalizador de comparação é acionado por um evento na saída do comparador analógico e uma interrupção é gerada. -O evento na saída do comparador analógico pode ser selecionado entre `` fall edge``, flanco ascendente ou qualquer flanco. +O evento na saída do comparador analógico pode ser selecionado entre `` falling edge``, ``rising edge`` ou ``any edge``. O ACC também pode gerar um evento de comparação que pode ser usado pelo Pulse Width Modulation (PWM). From a17d2c741cb018331d987733910420bf5a3c3e74 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Sun, 5 Jun 2022 23:48:24 -0300 Subject: [PATCH 15/23] Update README.md --- Perifericos-uC/ACC/README.md | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index 42918861..37385fe9 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -7,6 +7,8 @@ Configura o comparador analógico e gera uma interrupção dependendo nas config ## Diagrama de Blocos ![image](https://user-images.githubusercontent.com/62957465/172076354-d0085309-cc7c-4098-94a7-52673859c7b0.png) +O comparador analógico incorpora 8 a 1 multiplexadores em ambos suas entradas. + O DAC0 e o AD0 são selecionados como duas entradas. O usuário pode alterar a tensão de saída do DAC0 e alterar a tensão do AD0. A tensão de saída de DAC0 varia de (1/6)*ADVREF a (5/6)*ADVREF, e a tensão de entrada de AD0 varia de 0 a ADVREF. @@ -17,9 +19,7 @@ O evento de comparação seria gerado se a tensão de uma entrada fosse alterada O ACC configura o Comparador Analógico e gera uma interrupção de acordo com as configurações do aplicativo do usuário. -O comparador analógico incorpora 8 a 1 multiplexadores em ambos suas entradas. O Comparador Analógico compara duas tensões de entrada analógicas, e o resultado dessa comparação fornece uma comparação saída (emite um nível de sinal indicando qual das entradas é maior ou menor) e uma interrupção pode ser gerada de acordo. Um comparador analógico é basicamente um amplificador sem feedback e, portanto, tem ganho muito alto. - -O usuário pode selecionar uma alta velocidade ou opção de baixa potência, o nível de histerese, detecção de borda e polaridade. +O comparador analógico compara duas tensões de entrada analógicas, e o resultado dessa comparação fornece uma comparação saída (emite um nível de sinal indicando qual das entradas é maior ou menor) e uma interrupção pode ser gerada de acordo. Um comparador analógico é basicamente um amplificador sem feedback e, portanto, tem ganho muito alto. Quando as configurações do comparador analógico são modificadas, a saída da célula analógica pode ser inválida. @@ -27,6 +27,8 @@ Um sinalizador de comparação é acionado por um evento na saída do comparador O evento na saída do comparador analógico pode ser selecionado entre `` falling edge``, ``rising edge`` ou ``any edge``. +O usuário pode selecionar uma alta velocidade ou opção de baixa potência, o nível de histerese, detecção de borda e polaridade. + O ACC também pode gerar um evento de comparação que pode ser usado pelo Pulse Width Modulation (PWM). ![image](https://user-images.githubusercontent.com/62957465/172083444-b36941b3-36df-4993-ab29-b3cab1f9e7a7.png) From 353f4a0e93005f56eaa5915b308e4026bf902c56 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Mon, 6 Jun 2022 00:16:11 -0300 Subject: [PATCH 16/23] Update README.md --- Perifericos-uC/ACC/README.md | 101 +++++++++++++++++++++++++++++++---- 1 file changed, 90 insertions(+), 11 deletions(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index 37385fe9..927f5b8c 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -4,17 +4,6 @@ Configura o comparador analógico e gera uma interrupção dependendo nas config ## Conexão e configuração - Não é necessária -## Diagrama de Blocos -![image](https://user-images.githubusercontent.com/62957465/172076354-d0085309-cc7c-4098-94a7-52673859c7b0.png) - -O comparador analógico incorpora 8 a 1 multiplexadores em ambos suas entradas. - -O DAC0 e o AD0 são selecionados como duas entradas. O usuário pode alterar a tensão de saída do DAC0 e alterar a tensão do AD0. - -A tensão de saída de DAC0 varia de (1/6)*ADVREF a (5/6)*ADVREF, e a tensão de entrada de AD0 varia de 0 a ADVREF. - -O evento de comparação seria gerado se a tensão de uma entrada fosse alterada pela tensão da outra entrada. Tanto eventos maiores quanto menores podem ser acionados por padrão. - ## Analog Comparator Controller - ACC O ACC configura o Comparador Analógico e gera uma interrupção de acordo com as configurações do aplicativo do usuário. @@ -35,7 +24,97 @@ O ACC também pode gerar um evento de comparação que pode ser usado pelo Pulse Quando a tensão na entrada positiva (Vin0) é maior que a tensão na entrada negativa (Vin1), então a tensão de saída (VOUT) está saturada para seu alimentação positiva (+VSUPPLY), caso contrário, a saída é saturada com alimentação negativa (-VSUPPLY). Em microcontroladores, como não há tensão de alimentação negativa, GND (nível de terra) é tomado como –VSUPPLY e VCC nível é considerado +VSUPPLY. +## Diagrama de Blocos +![image](https://user-images.githubusercontent.com/62957465/172076354-d0085309-cc7c-4098-94a7-52673859c7b0.png) + +O comparador analógico incorpora 8 a 1 multiplexadores em ambos suas entradas. + +O DAC0 e o AD0 são selecionados como duas entradas. O usuário pode alterar a tensão de saída do DAC0 e alterar a tensão do AD0. + +A tensão de saída de DAC0 varia de (1/6)*ADVREF a (5/6)*ADVREF, e a tensão de entrada de AD0 varia de 0 a ADVREF. + +O evento de comparação seria gerado se a tensão de uma entrada fosse alterada pela tensão da outra entrada. Tanto eventos maiores quanto menores podem ser acionados por padrão. + ### Main +```c + +int main(void) +{ + uint32_t uc_key; + int16_t s_volt = 0; + uint32_t ul_value = 0; + volatile uint32_t ul_status = 0x0; + int32_t l_volt_dac0 = 0; + + /* Função para iniçialização do sistema, clocks, DACC e AFEC */ + init(); + + /* Iniciando a entrada DAC0 em ADVREF/2 */ + dacc_write_conversion_data(DACC, MAX_DIGITAL / 2, DACC_CHANNEL_0); + l_volt_dac0 = (MAX_DIGITAL / 2) * (2 * VOLT_REF / 3) / MAX_DIGITAL +VOLT_REF / 6; + + /* Enable clock for ACC */ + pmc_enable_periph_clk(ID_ACC); + + /* Inicializa o ACC*/ + acc_init(ACC, ACC_MR_SELPLUS_AFE0_AD0, ACC_MR_SELMINUS_DAC0, ACC_MR_EDGETYP_ANY, ACC_MR_INV_DIS); + + /* Enable ACC interrupt */ + NVIC_EnableIRQ(ACC_IRQn); + + /* Enable */ + acc_enable_interrupt(ACC); + + dsplay_menu(); /* Função para colocar na Terminal Window as opções do menu */ + + while (1) { + while (usart_read(CONSOLE_UART, &uc_key)) { + } + + printf("input: %c\r\n", uc_key); + + switch (uc_key) { + case 's': /*s: Set new DAC0 output voltage */ + case 'S': + printf("Input DAC0 output voltage (%d~%d mv): ",(VOLT_REF / 6), (VOLT_REF * 5 / 6)); + s_volt = get_input_voltage(); /*Pega o valor de tensão da entrada inserida pelo usuário*/ + puts("\r"); + + if (s_volt > 0) { + l_volt_dac0 = s_volt; + ul_value = ((s_volt - (VOLT_REF / 6))* (MAX_DIGITAL * 6) / 4) / VOLT_REF; /*Coloca novo valor de tensão*/ + dacc_write_conversion_data(DACC, ul_value, DACC_CHANNEL_0); + puts("-I- Set ok\r"); + } else { + puts("-I- Input voltage is invalid\r"); + } + break; + case 'v': /*v: Pega a voltagem do potenciometro*/ + case 'V': + /* Começa conversão */ + afec_start_software_conversion(AFEC0); + ul_status = afec_get_interrupt_status(AFEC0); /* Leitura do status do periférico */ + while ((ul_status & AFEC_ISR_EOC0) != AFEC_ISR_EOC0) { + ul_status = afec_get_interrupt_status(AFEC0); + } + /* Fim da conversão */ + ul_value = afec_channel_get_value(AFEC0, AFEC_CHANNEL_POTENTIOMETER); + + /* Converte de AFEC data para valor em voltagem*/ + s_volt = (ul_value * VOLT_REF) / MAX_DIGITAL; + printf("-I- Voltage on potentiometer(AD0) is %d mv\n\r", s_volt); + printf("-I- Voltage on DAC0 is %ld mv \n\r", (long)l_volt_dac0); + break; + + case 'm': /*m: Display this menu again*/ + case 'M': + dsplay_menu(); + break; + } + } +} + +``` ### Interrupção From fd534c11c5ec07d805843dd5b65a6f629ff34957 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Mon, 6 Jun 2022 00:18:59 -0300 Subject: [PATCH 17/23] Update README.md --- Perifericos-uC/ACC/README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index 927f5b8c..f8fe1237 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -74,7 +74,7 @@ int main(void) printf("input: %c\r\n", uc_key); switch (uc_key) { - case 's': /*s: Set new DAC0 output voltage */ + case 's': /*s: Definir nova tensão de saída DAC0 */ case 'S': printf("Input DAC0 output voltage (%d~%d mv): ",(VOLT_REF / 6), (VOLT_REF * 5 / 6)); s_volt = get_input_voltage(); /*Pega o valor de tensão da entrada inserida pelo usuário*/ @@ -106,7 +106,7 @@ int main(void) printf("-I- Voltage on DAC0 is %ld mv \n\r", (long)l_volt_dac0); break; - case 'm': /*m: Display this menu again*/ + case 'm': /* m: Exibir este menu novamente */ case 'M': dsplay_menu(); break; From b34e4bc4544a8fb9e6cf4ab2c0fbf371a11199cb Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Mon, 6 Jun 2022 00:19:56 -0300 Subject: [PATCH 18/23] Update README.md --- Perifericos-uC/ACC/README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index f8fe1237..da088b65 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -82,7 +82,8 @@ int main(void) if (s_volt > 0) { l_volt_dac0 = s_volt; - ul_value = ((s_volt - (VOLT_REF / 6))* (MAX_DIGITAL * 6) / 4) / VOLT_REF; /*Coloca novo valor de tensão*/ + /*Coloca novo valor de tensão*/ + ul_value = ((s_volt - (VOLT_REF / 6))* (MAX_DIGITAL * 6) / 4) / VOLT_REF; dacc_write_conversion_data(DACC, ul_value, DACC_CHANNEL_0); puts("-I- Set ok\r"); } else { From cde206bdf814e0dd989038e81d32e5de6d532c6e Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Mon, 6 Jun 2022 00:25:18 -0300 Subject: [PATCH 19/23] Update README.md --- Perifericos-uC/ACC/README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index da088b65..8bd6c05a 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -36,6 +36,9 @@ A tensão de saída de DAC0 varia de (1/6)*ADVREF a (5/6)*ADVREF, e a tensão de O evento de comparação seria gerado se a tensão de uma entrada fosse alterada pela tensão da outra entrada. Tanto eventos maiores quanto menores podem ser acionados por padrão. ### Main + +A função ``main`` desse programa é responsável por inicializar todos os periféricos envolvidos no projeto e exibir um menu para o usuário que permite definir uma nova tensão de entrada, como também pegar a voltagem do potênciometro. + ```c int main(void) From d56ef01b02b6d8a006a27224f98e2915314e5a94 Mon Sep 17 00:00:00 2001 From: felipebpl Date: Mon, 6 Jun 2022 00:33:02 -0300 Subject: [PATCH 20/23] finalizando codigo comentado --- .../ACC_EXAMPLE/.vs/ACC_EXAMPLE/v14/.atsuo | Bin 0 -> 15872 bytes .../ACC_EXAMPLE.atsln} | 2 +- .../ACC_EXAMPLE.componentinfo.xml} | 0 .../ACC_EXAMPLE/ACC_EXAMPLE.cproj} | 490 +++++++++--------- .../src/ASF/common/boards/board.h | 0 .../src/ASF/common/services/clock/genclk.h | 0 .../src/ASF/common/services/clock/osc.h | 0 .../src/ASF/common/services/clock/pll.h | 0 .../ASF/common/services/clock/same70/genclk.h | 0 .../ASF/common/services/clock/same70/osc.h | 0 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Perifericos-uC/ACC/{ACC_EXAMPLE1/ACC_EXAMPLE1.atsln => ACC_EXAMPLE/ACC_EXAMPLE.atsln} (91%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1/ACC_EXAMPLE1.componentinfo.xml => ACC_EXAMPLE/ACC_EXAMPLE/ACC_EXAMPLE.componentinfo.xml} (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1/ACC_EXAMPLE1.cproj => ACC_EXAMPLE/ACC_EXAMPLE/ACC_EXAMPLE.cproj} (53%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/boards/board.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/clock/genclk.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/clock/osc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/clock/pll.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/clock/same70/genclk.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/clock/same70/osc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/clock/same70/pll.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/clock/same70/sysclk.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/clock/same70/sysclk.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/clock/sysclk.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/gpio/gpio.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/gpio/sam_gpio/sam_gpio.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/ioport/ioport.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/ioport/sam/ioport_pio.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/serial/sam_uart/uart_serial.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/serial/serial.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/serial/usart_serial.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/sleepmgr/sam/sleepmgr.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/sleepmgr/sam/sleepmgr.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/services/sleepmgr/sleepmgr.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/utils/interrupt.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/utils/parts.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/utils/stdio/read.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/common/utils/stdio/write.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/boards/same70_xplained/init.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/boards/same70_xplained/led.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/boards/same70_xplained/same70_xplained.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/acc/acc.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/acc/acc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/acc/acc_example/acc_example.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/afec/afec.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/afec/afec.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/dacc/dacc.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/dacc/dacc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/mpu/mpu.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/mpu/mpu.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/pio/pio.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/pio/pio.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/pio/pio_handler.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/pio/pio_handler.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/pmc/pmc.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/pmc/pmc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/pmc/sleep.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/pmc/sleep.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/uart/uart.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/uart/uart.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/usart/usart.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/drivers/usart/usart.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/acc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/aes.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/afec.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/chipid.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/dacc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/efc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/gmac.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/gpbr.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/hsmci.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/i2sc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/icm.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/isi.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/matrix.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/mcan.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/pio.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/pmc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/pwm.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/qspi.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/rstc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/rswdt.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/rtc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/rtt.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/sdramc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/smc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/spi.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/ssc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/supc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/tc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/trng.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/twihs.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/uart.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/usart.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/usbhs.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/utmi.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/wdt.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/component/xdmac.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/acc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/aes.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/afec0.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/afec1.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/chipid.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/dacc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/efc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/gmac.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/gpbr.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/hsmci.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/i2sc0.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/i2sc1.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/icm.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/isi.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/matrix.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/mcan0.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/mcan1.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/pioa.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/piob.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/pioc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/piod.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/pioe.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/pmc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/rtc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/rtt.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/sdramc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/smc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/ssc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/supc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/tc0.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/tc1.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/tc2.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/tc3.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/trng.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/uart0.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/uart1.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/uart2.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/uart3.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/uart4.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/usart0.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/usart1.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/usart2.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/utmi.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/wdt.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/instance/xdmac.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70j19.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70j19b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70j20.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70j20b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70j21.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70j21b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70n19.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70n19b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70n20.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70n20b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70n21.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70n21b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70q19.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70q19b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70q20.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70q20b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70q21.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/pio/same70q21b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70j19.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70j19b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70j20.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70j20b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70j21.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70j21b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70n19.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70n19b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70n20.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70n20b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70n21.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70n21b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70q19.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70q19b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70q20.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70q20b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70q21.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/include/same70q21b.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/source/templates/gcc/startup_same70.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/source/templates/system_same70.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/cmsis/same70/source/templates/system_same70.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/compiler.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/fpu/fpu.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/header_files/io.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/linker_scripts/same70/same70q21/gcc/flash.ld (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/make/Makefile.sam.in (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/preprocessor/mrepeat.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/preprocessor/preprocessor.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/preprocessor/stringz.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/preprocessor/tpaste.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/status_codes.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/sam/utils/syscalls/gcc/syscalls.c (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/Include/arm_common_tables.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/Include/arm_const_structs.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/Include/arm_math.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/Include/cmsis_version.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/Include/core_cm7.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math_softfp.a (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/Lib/license.txt (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/ASF/thirdparty/CMSIS/README.txt (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/acc_example_canopus.c (52%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/asf.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/config/conf_board.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/config/conf_clock.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/config/conf_sleepmgr.h (100%) rename Perifericos-uC/ACC/{ACC_EXAMPLE1 => ACC_EXAMPLE/ACC_EXAMPLE}/src/config/conf_uart_serial.h (100%) delete mode 100644 Perifericos-uC/ACC/ACC_EXAMPLE1/.vs/ACC_EXAMPLE1/v14/.atsuo diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE/.vs/ACC_EXAMPLE/v14/.atsuo b/Perifericos-uC/ACC/ACC_EXAMPLE/.vs/ACC_EXAMPLE/v14/.atsuo new file mode 100644 index 0000000000000000000000000000000000000000..334bc904f59bcbbd4c1cec3985069eb31e7dbf27 GIT binary patch literal 15872 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to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE.atsln index fd81924c..9e14d297 100644 --- a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1.atsln +++ b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE.atsln @@ -3,7 +3,7 @@ Microsoft Visual Studio Solution File, Format Version 12.00 # Atmel Studio Solution File, Format Version 11.00 VisualStudioVersion = 14.0.23107.0 MinimumVisualStudioVersion = 10.0.40219.1 -Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "ACC_EXAMPLE1", "ACC_EXAMPLE1\ACC_EXAMPLE1.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "ACC_EXAMPLE", "ACC_EXAMPLE\ACC_EXAMPLE.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1.componentinfo.xml b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/ACC_EXAMPLE.componentinfo.xml similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1.componentinfo.xml rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/ACC_EXAMPLE.componentinfo.xml diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1.cproj b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/ACC_EXAMPLE.cproj similarity index 53% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1.cproj rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/ACC_EXAMPLE.cproj index 7cee73e2..ad9fdd9b 100644 --- a/Perifericos-uC/ACC/ACC_EXAMPLE1/ACC_EXAMPLE1.cproj +++ b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/ACC_EXAMPLE.cproj @@ -12,9 +12,9 @@ $(MSBuildProjectName) .elf $(MSBuildProjectDirectory)\$(Configuration) - ACC_EXAMPLE1 - ACC_EXAMPLE1 - ACC_EXAMPLE1 + ACC_EXAMPLE + ACC_EXAMPLE + ACC_EXAMPLE Native true false @@ -30,248 +30,248 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/boards/board.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/boards/board.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/boards/board.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/boards/board.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/genclk.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/genclk.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/genclk.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/genclk.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/osc.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/osc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/osc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/osc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/pll.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/pll.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/pll.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/pll.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/genclk.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/same70/genclk.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/genclk.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/same70/genclk.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/osc.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/same70/osc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/osc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/same70/osc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/pll.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/same70/pll.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/pll.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/same70/pll.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/sysclk.c b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/same70/sysclk.c similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/sysclk.c rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/same70/sysclk.c diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/sysclk.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/same70/sysclk.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/same70/sysclk.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/same70/sysclk.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/sysclk.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/sysclk.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/clock/sysclk.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/clock/sysclk.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/gpio/gpio.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/gpio/gpio.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/gpio/gpio.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/gpio/gpio.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/gpio/sam_gpio/sam_gpio.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/gpio/sam_gpio/sam_gpio.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/gpio/sam_gpio/sam_gpio.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/gpio/sam_gpio/sam_gpio.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/ioport/ioport.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/ioport/ioport.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/ioport/ioport.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/ioport/ioport.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/ioport/sam/ioport_pio.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/ioport/sam/ioport_pio.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/ioport/sam/ioport_pio.h rename to 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b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/serial/usart_serial.c similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/serial/usart_serial.c rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/serial/usart_serial.c diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sam/sleepmgr.c b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/sleepmgr/sam/sleepmgr.c similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sam/sleepmgr.c rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/sleepmgr/sam/sleepmgr.c diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/services/sleepmgr/sam/sleepmgr.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/services/sleepmgr/sam/sleepmgr.h similarity index 100% rename from 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a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/parts.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/parts.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/parts.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/parts.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/stdio/read.c b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/stdio/read.c similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/stdio/read.c rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/stdio/read.c diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/stdio/write.c b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/stdio/write.c similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/common/utils/stdio/write.c rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/common/utils/stdio/write.c diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/init.c b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/boards/same70_xplained/init.c similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/init.c rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/boards/same70_xplained/init.c diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/led.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/boards/same70_xplained/led.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/boards/same70_xplained/led.h rename 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rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/drivers/uart/uart.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/drivers/usart/usart.c b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/drivers/usart/usart.c similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/drivers/usart/usart.c rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/drivers/usart/usart.c diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/drivers/usart/usart.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/drivers/usart/usart.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/drivers/usart/usart.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/drivers/usart/usart.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/acc.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/acc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/acc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/acc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/aes.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/aes.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/aes.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/aes.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/afec.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/afec.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/afec.h rename to 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a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/efc.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/efc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/efc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/efc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/gmac.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/gmac.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/gmac.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/gmac.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/gpbr.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/gpbr.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/gpbr.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/gpbr.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/hsmci.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/hsmci.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/hsmci.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/hsmci.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/i2sc.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/i2sc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/i2sc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/i2sc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/icm.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/icm.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/icm.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/icm.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/isi.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/isi.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/isi.h rename to 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a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pio.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/pio.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pio.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/pio.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pmc.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/pmc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pmc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/component/pmc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/component/pwm.h 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a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/matrix.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/matrix.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/matrix.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/matrix.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/mcan0.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/mcan0.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/mcan0.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/mcan0.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/mcan1.h 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a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/rstc.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h similarity index 100% rename from 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a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/spi0.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/spi1.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/ssc.h 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a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h 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a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/acc_example_canopus.c +++ b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/acc_example_canopus.c @@ -1,92 +1,3 @@ -/** - * \file - * - * \brief Analog Comparator Controller (ACC) example for SAMV71/SAME70. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -/** - * \mainpage acc_irq ACC IRQ Example - * - * \section Purpose - * - * The acc_irq example demonstrates how to use the ACC peripheral to - * detect comparison event on the input pair. - * - * \section Requirements - * - * This example can be used on the following boards:
    - * - SAMV71-Xplained-Ultra
    - * - SAME70-Xplained-Pro
    - * - * \section Description - * - * The acc_irq is aimed to demonstrate the usage of ACC peripheral with - * interrupt support. The DAC0 and AD0 are selected as two inputs. - * The user can change the output voltage of DAC0 and change the voltage - * on AD0. - * - * The output voltage of DAC0 is ranged from (1/6)*ADVREF to (5/6)*ADVREF,and - * the input voltage of AD0 is ranged from 0 to ADVREF. - * - * The comparison event would be generated if the voltage of one input is - * changed across the voltage of the other input. Both bigger and less events - * could be triggered by default. - * - * \section Usage - * - * -# Build the program and download it inside the evaluation board. - * -# On the computer, open and configure a terminal application - * (e.g. HyperTerminal on Microsoft Windows) with these settings: - * - 115200 bauds - * - 8 bits of data - * - No parity - * - 1 stop bit - * - No flow control - * -# In the terminal window, the - * following text should appear (values depend on the board and chip used): - * \code - * -- ACC IRQ Example xxx -- - * -- xxxxxx-xx - * -- Compiled: xxx xx xxxx xx:xx:xx -- - * -- Menu Choices for this example-- - * -- s: Set new DAC0 output voltage.-- - * -- v: Get voltage on potentiometer.-- - * -- m: Display this menu again.-- - * \endcode - * -# Input command according to the menu. - * -# Change voltage on AD0 to see what comparison event happen. - * - */ -/* - * Support and FAQ: visit Microchip Support - */ #include "asf.h" #include "stdio_serial.h" @@ -118,11 +29,12 @@ void ACC_Handler(void) { uint32_t ul_status; + /* Leitura do status do periférico */ ul_status = acc_get_interrupt_status(ACC); - /* Compare Output Interrupt */ + /* Comparação da interrupção de saída*/ if ((ul_status & ACC_ISR_CE) == ACC_ISR_CE) { - if (acc_get_comparison_result(ACC)) { + if (acc_get_comparison_result(ACC)) { puts("-ISR- Voltage Comparison Result: AD0 > DAC0\r"); } else { puts("-ISR- Voltage Comparison Result: AD0 < DAC0\r"); @@ -191,11 +103,11 @@ static int16_t get_input_voltage(void) } ac_str_temp[i] = '\0'; - /* Input string length */ + /* Tamanho da string de entrada*/ c_length = i; us_value = 0; - /* Convert string to integer */ + /* Converte de string para int */ for (i = 0; i < 4; i++) { if (ac_str_temp[i] != '0') { switch (c_length - i - 1) { @@ -222,63 +134,25 @@ static int16_t get_input_voltage(void) return us_value; } -/** - * \brief ACC example application entry point. - * - * \return Unused (ANSI-C compatibility). - */ -int main(void) -{ - uint32_t uc_key; - int16_t s_volt = 0; - uint32_t ul_value = 0; - volatile uint32_t ul_status = 0x0; - int32_t l_volt_dac0 = 0; - +void init(void){ /* Initialize the system */ sysclk_init(); board_init(); - - /* Initialize debug console */ configure_console(); /* Output example information */ puts(STRING_HEADER); /* Initialize DACC */ - /* Enable clock for DACC */ pmc_enable_periph_clk(ID_DACC); - /* Reset DACC registers */ dacc_reset(DACC); - /* External trigger mode disabled. DACC in free running mode. */ dacc_disable_trigger(DACC, DACC_CHANNEL_0); - /* Half word transfer mode */ dacc_set_transfer_mode(DACC, 0); -#if (SAM3S) || (SAM3XA) - /* Power save: - * sleep mode - 0 (disabled) - * fast wakeup - 0 (disabled) - */ - dacc_set_power_save(DACC, 0, 0); -#endif - + /* Enable output channel DACC_CHANNEL */ dacc_enable_channel(DACC, DACC_CHANNEL_0); - /* Setup analog current */ - dacc_set_analog_control(DACC, DACC_ANALOG_CONTROL); - - /* Set DAC0 output at ADVREF/2. The DAC formula is: - * - * (5/6 * VOLT_REF) - (1/6 * VOLT_REF) volt - (1/6 * VOLT_REF) - * ----------------------------------- = -------------------------- - * MAX_DIGITAL digit - * - * Here, digit = MAX_DIGITAL/2 - */ - dacc_write_conversion_data(DACC, MAX_DIGITAL / 2, DACC_CHANNEL_0); - l_volt_dac0 = (MAX_DIGITAL / 2) * (2 * VOLT_REF / 3) / MAX_DIGITAL + - VOLT_REF / 6; - + dacc_set_analog_control(DACC, DACC_ANALOG_CONTROL); /* Setup analog current */ + /* Enable clock for AFEC */ afec_enable(AFEC0); @@ -302,13 +176,43 @@ int main(void) /* Enable channel for potentiometer. */ afec_channel_enable(AFEC0, AFEC_CHANNEL_POTENTIOMETER); + + /* Set DAC0 output at ADVREF/2. The DAC formula is: + * + * (5/6 * VOLT_REF) - (1/6 * VOLT_REF) volt - (1/6 * VOLT_REF) + * ----------------------------------- = -------------------------- + * MAX_DIGITAL digit + * + * Here, digit = MAX_DIGITAL/2 + */ + +} + +/** + * \brief ACC example application entry point. + * + * \return Unused (ANSI-C compatibility). + */ +int main(void) +{ + uint32_t uc_key; + int16_t s_volt = 0; + uint32_t ul_value = 0; + volatile uint32_t ul_status = 0x0; + int32_t l_volt_dac0 = 0; + + /* Função para iniçialização do sistema, clocks, DACC e AFEC */ + init(); + + /* Iniciando a entrada DAC0 em ADVREF/2 */ + dacc_write_conversion_data(DACC, MAX_DIGITAL / 2, DACC_CHANNEL_0); + l_volt_dac0 = (MAX_DIGITAL / 2) * (2 * VOLT_REF / 3) / MAX_DIGITAL +VOLT_REF / 6; /* Enable clock for ACC */ pmc_enable_periph_clk(ID_ACC); - /* Initialize ACC */ - acc_init(ACC, ACC_MR_SELPLUS_AFE0_AD0, ACC_MR_SELMINUS_DAC0, - ACC_MR_EDGETYP_ANY, ACC_MR_INV_DIS); + /* Inicializa o ACC*/ + acc_init(ACC, ACC_MR_SELPLUS_AFE0_AD0, ACC_MR_SELMINUS_DAC0, ACC_MR_EDGETYP_ANY, ACC_MR_INV_DIS); /* Enable ACC interrupt */ NVIC_EnableIRQ(ACC_IRQn); @@ -316,7 +220,7 @@ int main(void) /* Enable */ acc_enable_interrupt(ACC); - dsplay_menu(); + dsplay_menu(); /* Função para colocar na Terminal Window as opções do menu */ while (1) { while (usart_read(CONSOLE_UART, &uc_key)) { @@ -325,51 +229,40 @@ int main(void) printf("input: %c\r\n", uc_key); switch (uc_key) { - case 's': - case 'S': - printf("Input DAC0 output voltage (%d~%d mv): ", - (VOLT_REF / 6), (VOLT_REF * 5 / 6)); - s_volt = get_input_voltage(); + case 's': /*s: Definir nova tensão de saída DAC0 */ + case 'S': + printf("Input DAC0 output voltage (%d~%d mv): ",(VOLT_REF / 6), (VOLT_REF * 5 / 6)); + s_volt = get_input_voltage(); /*Pega o valor de tensão da entrada inserida pelo usuário*/ puts("\r"); if (s_volt > 0) { l_volt_dac0 = s_volt; - /* The DAC formula is: - * - * (5/6 * VOLT_REF) - (1/6 * VOLT_REF) volt - (1/6 * VOLT_REF) - * ----------------------------------- = -------------------------- - * MAX_DIGITAL digit - * - */ - ul_value = ((s_volt - (VOLT_REF / 6)) - * (MAX_DIGITAL * 6) / 4) / VOLT_REF; - dacc_write_conversion_data(DACC, ul_value, DACC_CHANNEL_0); + /*Coloca novo valor de tensão*/ + ul_value = ((s_volt - (VOLT_REF / 6))* (MAX_DIGITAL * 6) / 4) / VOLT_REF; + dacc_write_conversion_data(DACC, ul_value, DACC_CHANNEL_0); puts("-I- Set ok\r"); } else { puts("-I- Input voltage is invalid\r"); } break; - case 'v': - case 'V': - /* Start conversion */ + case 'v': /*v: Pega a voltagem do potenciometro*/ + case 'V': + /* Começa conversão */ afec_start_software_conversion(AFEC0); - ul_status = afec_get_interrupt_status(AFEC0); + ul_status = afec_get_interrupt_status(AFEC0); /* Leitura do status do periférico */ while ((ul_status & AFEC_ISR_EOC0) != AFEC_ISR_EOC0) { ul_status = afec_get_interrupt_status(AFEC0); } - /* Conversion is done */ + /* Fim da conversão */ ul_value = afec_channel_get_value(AFEC0, AFEC_CHANNEL_POTENTIOMETER); - - /* - * Convert AFEC sample data to voltage value: - * voltage value = (sample data / max. resolution) * reference voltage - */ + + /* Converte de AFEC data para valor em voltagem*/ s_volt = (ul_value * VOLT_REF) / MAX_DIGITAL; printf("-I- Voltage on potentiometer(AD0) is %d mv\n\r", s_volt); printf("-I- Voltage on DAC0 is %ld mv \n\r", (long)l_volt_dac0); break; - case 'm': + case 'm': /* m: Exibir este menu novamente */ case 'M': dsplay_menu(); break; diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/asf.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/asf.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/asf.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/asf.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_board.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/config/conf_board.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_board.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/config/conf_board.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_clock.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/config/conf_clock.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_clock.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/config/conf_clock.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_sleepmgr.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/config/conf_sleepmgr.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_sleepmgr.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/config/conf_sleepmgr.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_uart_serial.h b/Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/config/conf_uart_serial.h similarity index 100% rename from Perifericos-uC/ACC/ACC_EXAMPLE1/src/config/conf_uart_serial.h rename to Perifericos-uC/ACC/ACC_EXAMPLE/ACC_EXAMPLE/src/config/conf_uart_serial.h diff --git a/Perifericos-uC/ACC/ACC_EXAMPLE1/.vs/ACC_EXAMPLE1/v14/.atsuo b/Perifericos-uC/ACC/ACC_EXAMPLE1/.vs/ACC_EXAMPLE1/v14/.atsuo deleted file mode 100644 index 3ae884c137e80747eb7109e3c61714ca63a449fc..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 18944 zcmeHOO>iSe6&`Q0$>t9TOO_BqaKf^LXk|;XER8nVkeSh+_5W|l@v@OdqaRy;p3#3c zRlpr8#f2&^6cikwxP+pLDo)`*r8tGZs-!3mfl%DYiQ<+l-y3P{kyf%LuXnTF_{nd6 zx_kP)e*OCO>(}i+zWwNXKYrthe=uY4B6AP((e($I`*i6Gx@YDy4E-^b_R;n0*C~sh z@puBqNCGjYj$e~mWL!)QcbVx?SI!LQnA5v`{>TAeEne8Ntn}Vpco^lr_1K_r1QhGc z7PAKG1w6T!?g6!oW}jnD?b0W)kLFH(OCp(cmq4RWbQ??s9LS6Wj6)V#pfo5p^?IH; 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Para lidar com interrupções, o IC deve ser programado antes de configurar o ACC. ```c From 64b9f247064915dba3aca6509d861ffd385cdf77 Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Mon, 6 Jun 2022 00:48:59 -0300 Subject: [PATCH 22/23] Update README.md --- Perifericos-uC/ACC/README.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index d1b57b0b..d4b64125 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -120,6 +120,11 @@ int main(void) ``` +### Inicialização +```c +void acc_init(Acc * p_acc, uint32_t ul_select_plus, uint32_t ul_select_minus, uint32_t ul_edge_type, uint32_t ul_invert) + ``` + ### Interrupção ![image](https://user-images.githubusercontent.com/62957465/172090861-626aff4b-a012-4188-9ba5-185cfa5ff998.png) @@ -148,6 +153,8 @@ void ACC_Handler(void) } ``` + + ## Referências - Atmel Datasheet: https://www.tme.eu/Document/b85c146da65ff583bac4b0dfc098ee7b/ATSAME70-DTE.pdf From db03bf32799e2f54b4c968a5ba7185ce3e8a9eec Mon Sep 17 00:00:00 2001 From: felipebpl <62957465+felipebpl@users.noreply.github.com> Date: Mon, 6 Jun 2022 00:57:16 -0300 Subject: [PATCH 23/23] Update README.md --- Perifericos-uC/ACC/README.md | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Perifericos-uC/ACC/README.md b/Perifericos-uC/ACC/README.md index d4b64125..1d8231e3 100644 --- a/Perifericos-uC/ACC/README.md +++ b/Perifericos-uC/ACC/README.md @@ -124,6 +124,21 @@ int main(void) ```c void acc_init(Acc * p_acc, uint32_t ul_select_plus, uint32_t ul_select_minus, uint32_t ul_edge_type, uint32_t ul_invert) ``` +- p_acc: Ponteiro de endereço do registrador + +- ul_select_plus: Seleção para a entrada positiva do comparador +![image](https://user-images.githubusercontent.com/62957465/172091682-3917c68b-4fe6-4ebc-ac25-07d6b7750aee.png) + +- ul_select_minus: Seleção para a entrada negativa do comparador +![image](https://user-images.githubusercontent.com/62957465/172091766-b4dd8465-732d-4def-a4fd-a619584e438d.png) + +- ul_edge_type: Modo de acionamento do sinal de comparação +-![image](https://user-images.githubusercontent.com/62957465/172092077-e7aa590c-e937-43a7-adea-befbdc433081.png) + +- ul_invert: Inverter o modo de saída do comparador +- ![image](https://user-images.githubusercontent.com/62957465/172092173-5dcfc376-f212-4386-bfbf-fd9e60263a28.png) + + ### Interrupção

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