diff --git a/.gitmodules b/.gitmodules index 2888e69d7..a5b5db0b3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -6,4 +6,7 @@ url = https://github.com/PrincetonUniversity/openpiton-aws.git [submodule "piton/design/chipset/rv64_platform/bootrom/u-boot/uboot"] path = piton/design/chipset/rv64_platform/bootrom/u-boot/uboot - url = git@github.com:u-boot/u-boot.git + url = https://github.com/u-boot/u-boot.git +[submodule "piton/design/chipset/io_ctrl/xilinx/common/ip_cores/eth_cmac_syst"] + path = piton/design/chipset/io_ctrl/xilinx/common/ip_cores/eth_cmac_syst + url = https://github.com/bsc-loca/100gb-ethernet diff --git a/README.md b/README.md index 4129ecd86..c46c71e58 100644 --- a/README.md +++ b/README.md @@ -505,3 +505,64 @@ The command will tell print the afi and agfi of your image. You can track the sy 8. After the synthesis is done - you can go load it in your F1 instance! +### Synthesizing OpenPiton for ALVEO boards + +This section has been added under MEEP project. For an eventual PR to OpenPiton team, we will need to review it. + +The flow is very simillar to synthesizing image for any other FPGA OpenPiton supports: + +1. Clone OpenPiton repo (MEEP version): git clone https://gitlab.bsc.es/hwdesign/frameworks/meep_openpiton.git + +2. cd into repo, run these bash commands: + +``` + source piton/piton_settings.bash + source piton/ariane_setup.sh + (Follow instructions in the top of the README in case this is the first time you install OpenPiton in your machine.) +``` + +4. Run the synthesis: + +``` + protosyn --board alveou280 --design system --core ariane --x_tiles 1 --y_tiles 1 --uart-dmw ddr --zeroer_off + + Extra avaialble protosyn options: + --eth # adding CMAC based Ethernet unit + --ethport # optional board-level Ethernet port (default=0) + + --hbm # define HBM as primary system memory + --multimc # implement design with multiple connections to system memory (valid only for HBM) + --multimc_indices # optional list of particular edge tiles for above `multimc` option + + --bram-test hello_world.c # compiling and runniing VCS-based simulation before synthesis + --verdi-dbg # creating Verdi compliant simulation database for above test (verdi run inside ./build dir (-sx is optional): verdi -ssf ./novas.fsdb) +``` + +This will create a Vivado design under $ROOT_DIR/build/... + +5. After the synthesis is complete (takes about 2-3 hours on fast PC), you can program the FPGA via JTAG + +6. Probably you would need to reboot to be able to use the new QDMA PCIe interface. + +7. Now you can download from the intranet the bbl containing the Linux kernel, a script to load it to the SDRAM and the bitstream itself in case you want to skip steps above. + +``` + /home/fpga-runnerMEEP/lagarto_sdk_deploy/rv64gc/ +``` + +In a separated bash window, open a client for the UART: + +``` + picocom -b 115200 /dev/ttyUSB2 +``` + +8. Clone FPGA tools repo: https://gitlab.bsc.es/hwdesign/fpga/integration-lab/fpga-tools.git + +Issue the next commands inside the downloaded repo: + +``` + ./fpga/load-bitstream-onic.sh qdma .bit + ./boot_riscv/boot_acme.sh .bin +``` + +You should be able to see Linux booting on the other terminal. diff --git a/piton/design/chip/rtl/chip.v.pyv b/piton/design/chip/rtl/chip.v.pyv index 9f553283c..24db1137d 100644 --- a/piton/design/chip/rtl/chip.v.pyv +++ b/piton/design/chip/rtl/chip.v.pyv @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // Modified by Princeton University on June 9th, 2015 // ========== Copyright Header Begin ========================================== // @@ -139,6 +140,17 @@ module chip( output offchip_processor_noc3_yummy `endif // endif PITON_NO_CHIP_BRIDGE + `ifdef PITON_EXTRA_MEMS + , + output [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] processor_mcx_noc2_data, + output [`PITON_EXTRA_MEMS-1:0] processor_mcx_noc2_valid, + input [`PITON_EXTRA_MEMS-1:0] processor_mcx_noc2_yummy, + + input [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] mcx_processor_noc3_data, + input [`PITON_EXTRA_MEMS-1:0] mcx_processor_noc3_valid, + output [`PITON_EXTRA_MEMS-1:0] mcx_processor_noc3_yummy + `endif + `ifdef PITON_RV64_PLATFORM `ifdef PITON_RV64_DEBUGUNIT // Debug @@ -1037,6 +1049,15 @@ module chip( assign default_total_num_tiles = `PITON_NUM_TILES; // Generate tile instances <% + sub_assign = r''' + assign default_coreid_x [_FLAT_ID_] =COREIDX; + assign default_coreid_y [_FLAT_ID_] =COREIDY; + assign flat_tileid [_FLAT_ID_] = _FLAT_ID_; + ''' + assign = r''' + + + ''' template = r''' tile #(.TILE_TYPE(TYPE_OF_TILE)) tile0 ( @@ -1114,6 +1135,32 @@ module chip( template = template[:-1] + r''' ); ''' + + + edge_sub1=r''' + assign default_coreid_x [ENDP] = COREIDX; + assign default_coreid_y [ENDP] = COREIDY; + assign flat_tileid [ENDP]= ENDP; + + assign dataOut_NN [ENDP] = endp_DatOut_NN; + assign validOut_NN[ENDP] = endp_ValidOut_NN; + assign endp_YummyIn_NN = yummyIn_NN[ENDP]; + ''' + edge_sub2=r''' + assign endp_DatIn_NN = dataIn_NN [ENDP]; + assign endp_ValidIn_NN = validIn_NN[ENDP]; + assign yummyOut_NN[ENDP] = endp_YummyOut_NN; + + ''' + edge_assign=r''' + + ''' + + + MC_POS=get_mc_mapping(PITON_X_TILES,PITON_Y_TILES,PITON_MC_INDICES,PITON_EXTRA_MEMS,PITON_NETWORK_CONFIG) + edge_idx=len(MC_POS) + + # generate the tiles for i in range(PITON_X_TILES): @@ -1122,10 +1169,67 @@ module chip( flatid = i + (j * PITON_X_TILES); # print template currenttile = template.replace("tile0", "tile%d" % (flatid)); + # special case for core 0 + if i == 0 and j == 0: + for k in [1,2,3]: + tmp = edge_sub1 + edge_sub2; + tmp = tmp.replace("endp_DatOut_NN","offchip_out_E_noc%d_data" %k); + tmp = tmp.replace("endp_ValidOut_NN","offchip_out_E_noc%d_valid" %k); + tmp = tmp.replace("endp_YummyOut_NN","offchip_out_E_noc%d_yummy" %k); + tmp = tmp.replace("endp_DatIn_NN","tile_0_0_out_W_noc%d_data" %k); + tmp = tmp.replace("endp_ValidIn_NN","tile_0_0_out_W_noc%d_valid" %k); + tmp = tmp.replace("endp_YummyIn_NN","tile_0_0_out_W_noc%d_yummy" %k); + tmp = tmp.replace("_NN", str(k)) + tmp = tmp.replace("ENDP","CHIP_SET_ID"); + tmp = tmp.replace("COREIDX", "8'd" + repr(i)); + tmp = tmp.replace("COREIDY", "8'd" + repr(j)); + + edge_assign=edge_assign + tmp; + # place the memory controllers + for k in range(edge_idx): + ax = MC_POS[k]['x'] + ay = MC_POS[k]['y'] + ap = MC_POS[k]['p'] + id = MC_POS[k]['endp'] + if(i==ax and j==ay): + currenttile = currenttile.replace("out_%s_noc2_data" % MC_POS[k]['p'], "processor_mcx_noc2_data [%d * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]" % k); + currenttile = currenttile.replace("out_%s_noc2_valid" % MC_POS[k]['p'], "processor_mcx_noc2_valid[%d]" % k); + currenttile = currenttile.replace("in_%s_noc2_yummy" % MC_POS[k]['p'], "processor_mcx_noc2_yummy[%d]" % k); + currenttile = currenttile.replace("in_%s_noc3_data" % MC_POS[k]['p'], "mcx_processor_noc3_data [%d * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]" % k); + currenttile = currenttile.replace("in_%s_noc3_valid" % MC_POS[k]['p'], "mcx_processor_noc3_valid[%d]" % k); + currenttile = currenttile.replace("out_%s_noc3_yummy" % MC_POS[k]['p'], "mcx_processor_noc3_yummy[%d]" % k); + tmp = ("//Connect MC %d to enp %d:\n" % (k,id)) + tmp = tmp + edge_sub1; + tmp = tmp.replace("ENDP",str(id)); + tmp = tmp.replace("COREIDX", "8'd" + repr(i)); + tmp = tmp.replace("COREIDY", "8'd" + repr(j)); + tmp = tmp.replace("endp_DatOut_NN","mcx_processor_noc3_data [%d * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]" % k); + tmp = tmp.replace("endp_ValidOut_NN","mcx_processor_noc3_valid[%d]" % k); + tmp = tmp.replace("endp_YummyIn_NN","mcx_processor_noc3_yummy[%d]" % k); + tmp = tmp.replace("_NN", "3"); + edge_assign=edge_assign + tmp; + tmp = edge_sub2 ; + tmp = tmp.replace("ENDP",str(id)); + tmp = tmp.replace("COREIDX", "8'd" + repr(i)); + tmp = tmp.replace("COREIDY", "8'd" + repr(j)); + tmp = tmp.replace("endp_DatIn_NN","processor_mcx_noc2_data [%d * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]" % k); + tmp = tmp.replace("endp_ValidIn_NN","processor_mcx_noc2_valid[%d]" % k); + tmp = tmp.replace("endp_YummyOut_NN", "processor_mcx_noc2_yummy[%d]" % k); + tmp = tmp.replace("_NN", "2"); + edge_assign=edge_assign + tmp; + currenttile = currenttile.replace("COREIDX", "8'd" + repr(i)); currenttile = currenttile.replace("COREIDY", "8'd" + repr(j)); currenttile = currenttile.replace("out_", "tile_%d_%d_out_" % (j,i)); currenttile = currenttile.replace("_FLAT_ID_", repr(flatid)); + + assign_tmp = sub_assign + assign_tmp = assign_tmp.replace("COREIDX", "8'd" + repr(i)); + assign_tmp = assign_tmp.replace("COREIDY", "8'd" + repr(j)); + assign_tmp = assign_tmp.replace("_FLAT_ID_", repr(flatid)); + + assign = assign + assign_tmp; + currenttype = "`SPARC_TILE" if (PITON_PICO_HET): diff --git a/piton/design/chip/tile/ariane b/piton/design/chip/tile/ariane index 4c01614f8..575cb445f 160000 --- a/piton/design/chip/tile/ariane +++ b/piton/design/chip/tile/ariane @@ -1 +1 @@ -Subproject commit 4c01614f83cd9dd91d115aa190bd4fc6a284b59e +Subproject commit 575cb445f8e31be4328557720c4c962740935686 diff --git a/piton/design/chip/tile/ariane_patch/ariane.patch b/piton/design/chip/tile/ariane_patch/ariane.patch new file mode 100644 index 000000000..a0010cb58 --- /dev/null +++ b/piton/design/chip/tile/ariane_patch/ariane.patch @@ -0,0 +1,36 @@ +diff --git a/Flist.ariane b/Flist.ariane +--- a/Flist.ariane ++++ b/Flist.ariane +@@ -76,6 +76,8 @@ src/axi_mem_if/src/axi2mem.sv + src/tech_cells_generic/src/pulp_clock_gating.sv + src/tech_cells_generic/src/cluster_clock_inverter.sv + src/tech_cells_generic/src/pulp_clock_mux2.sv ++src/pmp/src/pmp.sv ++src/pmp/src/pmp_entry.sv + src/axi_adapter.sv + src/alu.sv + src/fpu_wrap.sv +@@ -133,8 +135,6 @@ src/riscv-dbg/src/dmi_jtag_tap.sv + src/riscv-dbg/debug_rom/debug_rom.sv + openpiton/ariane_verilog_wrap.sv + openpiton/riscv_peripherals.sv +-openpiton/bootrom/baremetal/bootrom.sv +-openpiton/bootrom/linux/bootrom_linux.sv + src/rv_plic/rtl/rv_plic_target.sv + src/rv_plic/rtl/rv_plic_gateway.sv + src/rv_plic/rtl/plic_regmap.sv +diff --git a/src/frontend/frontend.sv b/src/frontend/frontend.sv +--- a/src/frontend/frontend.sv ++++ b/src/frontend/frontend.sv +@@ -343,10 +343,8 @@ module frontend #( + icache_data_q <= icache_data; + icache_vaddr_q <= icache_dreq_i.vaddr; + // Map the only three exceptions which can occur in the frontend to a two bit enum +- if (icache_dreq_i.ex.cause == riscv::INSTR_PAGE_FAULT) begin ++ if (icache_dreq_i.ex.valid) begin + icache_ex_valid_q <= ariane_pkg::FE_INSTR_PAGE_FAULT; +- end else if (icache_dreq_i.ex.cause == riscv::INSTR_ACCESS_FAULT) begin +- icache_ex_valid_q <= ariane_pkg::FE_INSTR_ACCESS_FAULT; + end else icache_ex_valid_q <= ariane_pkg::FE_NONE; + // save the uppermost prediction + btb_q <= btb_prediction[INSTR_PER_FETCH-1]; diff --git a/piton/design/chip/tile/ariane_patch/ariane_patch.sh b/piton/design/chip/tile/ariane_patch/ariane_patch.sh new file mode 100755 index 000000000..a24a547c5 --- /dev/null +++ b/piton/design/chip/tile/ariane_patch/ariane_patch.sh @@ -0,0 +1,4 @@ + +echo "Patching Ariane submodule..." +cd $ARIANE_ROOT +git apply $DV_ROOT/design/chip/tile/ariane_patch/ariane.patch diff --git a/piton/design/chip/tile/l15/rtl/noc1encoder.v b/piton/design/chip/tile/l15/rtl/noc1encoder.v index 33bd0cc58..d5e32035d 100644 --- a/piton/design/chip/tile/l15/rtl/noc1encoder.v +++ b/piton/design/chip/tile/l15/rtl/noc1encoder.v @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 /* Copyright (c) 2015 Princeton University All rights reserved. @@ -436,6 +437,8 @@ begin msg_options_2[`MSG_CACHE_TYPE_] = msg_cache_type; msg_options_2[`MSG_SUBLINE_VECTOR_] = msg_subline_vector; + msg_options_3[`MSG_INI_X_] = coreid_x; + msg_options_3[`MSG_INI_Y_] = coreid_y; msg_options_3[`MSG_SDID_] = req_csm_sdid; msg_options_3[`MSG_LSID_] = req_csm_lsid; end diff --git a/piton/design/chip/tile/l15/rtl/noc3encoder.v b/piton/design/chip/tile/l15/rtl/noc3encoder.v index eb91ad40c..9e3593010 100644 --- a/piton/design/chip/tile/l15/rtl/noc3encoder.v +++ b/piton/design/chip/tile/l15/rtl/noc3encoder.v @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 /* Copyright (c) 2015 Princeton University All rights reserved. @@ -231,6 +232,9 @@ begin msg_options_2[`MSG_CACHE_TYPE_] = msg_cache_type; msg_options_2[`MSG_SUBLINE_VECTOR_] = msg_subline_vector; + msg_options_3[`MSG_INI_X_] = coreid_x; + msg_options_3[`MSG_INI_Y_] = coreid_y; + msg_options_4[`MSG_LAST_SUBLINE] = msg_last_subline || (l15_noc3encoder_req_type == `L15_NOC3_REQTYPE_ICACHE_INVAL_ACK); msg_options_4[`MSG_SUBLINE_ID] = l15_noc3encoder_req_sequenceid; // does not need to specify cache line state diff --git a/piton/design/chip/tile/l2/rtl/Flist.l2 b/piton/design/chip/tile/l2/rtl/Flist.l2 index f523c2ee1..e124acdd2 100644 --- a/piton/design/chip/tile/l2/rtl/Flist.l2 +++ b/piton/design/chip/tile/l2/rtl/Flist.l2 @@ -58,6 +58,7 @@ l2_config_regs.v l2_priority_encoder.v l2_broadcast_counter.v l2_broadcast_counter_wrap.v +l2_to_mc.v sram_wrappers/sram_l2_tag.v sram_wrappers/sram_l2_data.v diff --git a/piton/design/chip/tile/l2/rtl/l2.core b/piton/design/chip/tile/l2/rtl/l2.core index 03ee57d86..fd79785ca 100644 --- a/piton/design/chip/tile/l2/rtl/l2.core +++ b/piton/design/chip/tile/l2/rtl/l2.core @@ -67,6 +67,7 @@ generate: [l2_pipe2_dpath.v.pyv, l2_pipe2_dpath.tmp.v], [l2_priority_encoder.v.pyv, l2_priority_encoder.tmp.v], [l2_smc.v.pyv, l2_smc.tmp.v], + [l2_to_mc.v.pyv, l2_to_mc.v], [l2_state.v.pyv, l2_state.tmp.v]] diff --git a/piton/design/chip/tile/l2/rtl/l2.v b/piton/design/chip/tile/l2/rtl/l2.v index ed1faf985..1165cd417 100644 --- a/piton/design/chip/tile/l2/rtl/l2.v +++ b/piton/design/chip/tile/l2/rtl/l2.v @@ -659,6 +659,12 @@ l2_pipe1 pipe1( .smc_tag_out (smc_tag_out), `endif +`ifdef PITON_EXTRA_MEMS + .chipid (chipid), + .coreid_x (coreid_x), + .coreid_y (coreid_y), +`endif + .data_clk_en (data_clk_en_p1), .data_rdw_en (data_rdw_en_p1), .data_addr (data_addr_p1), diff --git a/piton/design/chip/tile/l2/rtl/l2_decoder.v b/piton/design/chip/tile/l2/rtl/l2_decoder.v index ab2bb3911..747599cba 100644 --- a/piton/design/chip/tile/l2/rtl/l2_decoder.v +++ b/piton/design/chip/tile/l2/rtl/l2_decoder.v @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 /* Copyright (c) 2015 Princeton University All rights reserved. @@ -59,6 +60,8 @@ module l2_decoder( output reg [`MSG_SRC_CHIPID_WIDTH-1:0] msg_src_chipid, output reg [`MSG_SRC_X_WIDTH-1:0] msg_src_x, output reg [`MSG_SRC_Y_WIDTH-1:0] msg_src_y, + output reg [`MSG_SRC_X_WIDTH-1:0] msg_ini_x, + output reg [`MSG_SRC_Y_WIDTH-1:0] msg_ini_y, output reg [`MSG_SRC_FBITS_WIDTH-1:0] msg_src_fbits, output reg [`MSG_SDID_WIDTH-1:0] msg_sdid, output reg [`MSG_LSID_WIDTH-1:0] msg_lsid, @@ -81,6 +84,8 @@ begin msg_src_chipid = msg_header[`MSG_SRC_CHIPID]; msg_src_x = msg_header[`MSG_SRC_X]; msg_src_y = msg_header[`MSG_SRC_Y]; + msg_ini_x = msg_header[`MSG_INI_X]; + msg_ini_y = msg_header[`MSG_INI_Y]; msg_src_fbits = msg_header[`MSG_SRC_FBITS]; msg_sdid = msg_header[`MSG_SDID]; msg_lsid = msg_header[`MSG_LSID]; diff --git a/piton/design/chip/tile/l2/rtl/l2_encoder.v b/piton/design/chip/tile/l2/rtl/l2_encoder.v index ca170487b..3b32eaea5 100644 --- a/piton/design/chip/tile/l2/rtl/l2_encoder.v +++ b/piton/design/chip/tile/l2/rtl/l2_encoder.v @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 /* Copyright (c) 2015 Princeton University All rights reserved. @@ -62,14 +63,82 @@ module l2_encoder( input wire [`MSG_SRC_CHIPID_WIDTH-1:0] msg_src_chipid, input wire [`MSG_SRC_X_WIDTH-1:0] msg_src_x, input wire [`MSG_SRC_Y_WIDTH-1:0] msg_src_y, + input wire [`MSG_SRC_X_WIDTH-1:0] msg_ini_x, + input wire [`MSG_SRC_Y_WIDTH-1:0] msg_ini_y, input wire [`MSG_SRC_FBITS_WIDTH-1:0] msg_src_fbits, input wire [`MSG_SDID_WIDTH-1:0] msg_sdid, input wire [`MSG_LSID_WIDTH-1:0] msg_lsid, +`ifdef PITON_EXTRA_MEMS + input wire [`NOC_CHIPID_WIDTH-1:0] chipid, + input wire [`NOC_X_WIDTH-1:0] coreid_x, + input wire [`NOC_Y_WIDTH-1:0] coreid_y, +`endif + output reg [`MSG_HEADER_WIDTH-1:0] msg_header ); + +`ifdef PITON_EXTRA_MEMS + + localparam EXTRA_MEMS = `PITON_EXTRA_MEMS; + + wire [`MSG_SRC_X_WIDTH-1:0] mc_dst_x; + wire [`MSG_SRC_Y_WIDTH-1:0] mc_dst_y; + wire [`MSG_SRC_FBITS_WIDTH-1:0] mc_dst_fbits; + + wire [`MSG_SRC_CHIPID_WIDTH-1:0] msg_dst_chipid_tmp; + reg [`MSG_SRC_X_WIDTH-1:0] msg_dst_x_tmp; + reg [`MSG_SRC_Y_WIDTH-1:0] msg_dst_y_tmp; + reg [`MSG_SRC_FBITS_WIDTH-1:0] msg_dst_fbits_tmp; + + l2_to_mc mc_map( + .msg_addr(msg_addr), + .coreid_x(coreid_x), + .coreid_y(coreid_y), + .mc_dst_x(mc_dst_x), + .mc_dst_y(mc_dst_y), + .mc_dst_fbits(mc_dst_fbits) + ); + + reg off_chip; + + always @ (*) begin + if(!msg_dst_chipid [`CHIP_ID_WIDTH-1]) begin // it is not goinig to offchip + msg_dst_x_tmp = msg_dst_x; + msg_dst_y_tmp = msg_dst_y; + msg_dst_fbits_tmp=msg_dst_fbits; + off_chip=1'b0; + end else if (msg_addr[`PHY_ADDR_WIDTH-1]) begin // it is IO. not goinig to mmc + msg_dst_fbits_tmp=msg_dst_fbits;// abs_mmc = `W_EDGE; + msg_dst_x_tmp = `OFF_CHIP_NODE_X; + msg_dst_y_tmp = `OFF_CHIP_NODE_Y; + off_chip=1'b1; + end else begin // It is a message to MC + msg_dst_fbits_tmp=mc_dst_fbits; + msg_dst_x_tmp = mc_dst_x; + msg_dst_y_tmp = mc_dst_y; + off_chip=1'b0; //TODO should be asserted it if the mc is in another chip + end + end + + assign msg_dst_chipid_tmp = {off_chip,msg_dst_chipid[`CHIP_ID_WIDTH-2:0]}; + + +`else + wire [`MSG_SRC_CHIPID_WIDTH-1:0] msg_dst_chipid_tmp; + wire [`MSG_SRC_X_WIDTH -1:0] msg_dst_x_tmp; + wire [`MSG_SRC_Y_WIDTH -1:0] msg_dst_y_tmp; + wire [`MSG_SRC_FBITS_WIDTH -1:0] msg_dst_fbits_tmp; + + assign msg_dst_fbits_tmp = msg_dst_fbits; + assign msg_dst_chipid_tmp = msg_dst_chipid; + assign msg_dst_x_tmp = msg_dst_x; + assign msg_dst_y_tmp = msg_dst_y; +`endif + + always @ * begin msg_header = {msg_src_chipid, @@ -78,7 +147,9 @@ begin msg_src_fbits, msg_sdid, msg_lsid, - {(`NOC_DATA_WIDTH-`NOC_NODEID_WIDTH-`MSG_SDID_WIDTH-`MSG_LSID_WIDTH){1'b0}}, + msg_ini_x[`MSG_INI_X_WIDTH-1:0], + msg_ini_y[`MSG_INI_Y_WIDTH-1:0], + {(`NOC_DATA_WIDTH-`NOC_NODEID_WIDTH-`MSG_SDID_WIDTH-`MSG_LSID_WIDTH-`MSG_INI_X_WIDTH-`MSG_INI_Y_WIDTH){1'b0}}, 8'd0, msg_addr, @@ -87,10 +158,10 @@ begin msg_data_size, 8'd0, - msg_dst_chipid, - msg_dst_x, - msg_dst_y, - msg_dst_fbits, + msg_dst_chipid_tmp, + msg_dst_x_tmp, + msg_dst_y_tmp, + msg_dst_fbits_tmp, msg_length, msg_type, msg_mshrid, diff --git a/piton/design/chip/tile/l2/rtl/l2_pipe1.v b/piton/design/chip/tile/l2/rtl/l2_pipe1.v index 531c6d040..f8c9093cf 100644 --- a/piton/design/chip/tile/l2/rtl/l2_pipe1.v +++ b/piton/design/chip/tile/l2/rtl/l2_pipe1.v @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 /* Copyright (c) 2015 Princeton University All rights reserved. @@ -178,6 +179,12 @@ module l2_pipe1( output wire [`L2_DATA_INDEX_WIDTH-1:0] data_ecc_addr, output wire [`PHY_ADDR_WIDTH-1:0] error_addr, +`ifdef PITON_EXTRA_MEMS + input wire [`NOC_CHIPID_WIDTH-1:0] chipid, + input wire [`NOC_X_WIDTH-1:0] coreid_x, + input wire [`NOC_Y_WIDTH-1:0] coreid_y, +`endif + output wire reg_rd_en, output wire reg_wr_en, output wire [`L2_ADDR_TYPE_WIDTH-1:0] reg_rd_addr_type, @@ -196,6 +203,8 @@ wire [`PHY_ADDR_WIDTH-1:0] msg_addr; wire [`MSG_SRC_CHIPID_WIDTH-1:0] msg_src_chipid; wire [`MSG_SRC_X_WIDTH-1:0] msg_src_x; wire [`MSG_SRC_Y_WIDTH-1:0] msg_src_y; +wire [`MSG_SRC_X_WIDTH-1:0] msg_ini_x; +wire [`MSG_SRC_Y_WIDTH-1:0] msg_ini_y; wire [`MSG_SRC_FBITS_WIDTH-1:0] msg_src_fbits; wire [`MSG_SDID_WIDTH-1:0] msg_sdid; wire [`MSG_LSID_WIDTH-1:0] msg_lsid; @@ -384,6 +393,8 @@ wire [`PHY_ADDR_WIDTH-1:0] msg_send_addr; wire [`MSG_SRC_CHIPID_WIDTH-1:0] msg_send_dst_chipid; wire [`MSG_SRC_X_WIDTH-1:0] msg_send_dst_x; wire [`MSG_SRC_Y_WIDTH-1:0] msg_send_dst_y; +wire [`MSG_SRC_X_WIDTH-1:0] msg_send_ini_x; +wire [`MSG_SRC_Y_WIDTH-1:0] msg_send_ini_y; wire [`MSG_SRC_FBITS_WIDTH-1:0] msg_send_dst_fbits; wire [`NOC_DATA_WIDTH*2-1:0] msg_send_data; wire [`NOC_DATA_WIDTH*3-1:0] msg_send_header; @@ -425,6 +436,8 @@ l2_decoder decoder( .msg_src_chipid (msg_src_chipid), .msg_src_x (msg_src_x), .msg_src_y (msg_src_y), + .msg_ini_x (msg_ini_x), + .msg_ini_y (msg_ini_y), .msg_src_fbits (msg_src_fbits), .msg_sdid (msg_sdid), .msg_lsid (msg_lsid), @@ -803,6 +816,8 @@ l2_pipe1_dpath dpath( .msg_src_chipid_S1 (msg_src_chipid), .msg_src_x_S1 (msg_src_x), .msg_src_y_S1 (msg_src_y), + .msg_ini_x_S1 (msg_ini_x), + .msg_ini_y_S1 (msg_ini_y), .msg_src_fbits_S1 (msg_src_fbits), .msg_sdid_S1 (msg_sdid), .msg_lsid_S1 (msg_lsid), @@ -948,6 +963,8 @@ l2_pipe1_dpath dpath( .msg_send_dst_chipid_S4 (msg_send_dst_chipid), .msg_send_dst_x_S4 (msg_send_dst_x), .msg_send_dst_y_S4 (msg_send_dst_y), + .msg_send_ini_x_S4 (msg_send_ini_x), + .msg_send_ini_y_S4 (msg_send_ini_y), .msg_send_dst_fbits_S4 (msg_send_dst_fbits), .msg_send_data_S4 (msg_send_data), .mshr_data_in_S4 (mshr_data_in), @@ -964,6 +981,11 @@ l2_pipe1_dpath dpath( ); l2_encoder encoder( +`ifdef PITON_EXTRA_MEMS + .chipid (chipid), + .coreid_x (coreid_x), + .coreid_y (coreid_y), +`endif .msg_dst_chipid (msg_send_dst_chipid), .msg_dst_x (msg_send_dst_x), .msg_dst_y (msg_send_dst_y), @@ -983,6 +1005,8 @@ l2_encoder encoder( .msg_src_x (my_nodeid[`NOC_NODEID_X]), .msg_src_y (my_nodeid[`NOC_NODEID_Y]), .msg_src_fbits (my_nodeid[`NOC_NODEID_FBITS]), + .msg_ini_x (msg_send_ini_x), + .msg_ini_y (msg_send_ini_y), .msg_sdid ({`MSG_SDID_WIDTH{1'b0}}), .msg_lsid ({`MSG_LSID_WIDTH{1'b0}}), .msg_header (msg_send_header) diff --git a/piton/design/chip/tile/l2/rtl/l2_pipe1_dpath.v.pyv b/piton/design/chip/tile/l2/rtl/l2_pipe1_dpath.v.pyv index eed51240c..49c602901 100644 --- a/piton/design/chip/tile/l2/rtl/l2_pipe1_dpath.v.pyv +++ b/piton/design/chip/tile/l2/rtl/l2_pipe1_dpath.v.pyv @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 /* Copyright (c) 2015 Princeton University All rights reserved. @@ -115,6 +116,8 @@ module l2_pipe1_dpath( input wire [`MSG_SRC_CHIPID_WIDTH-1:0] msg_src_chipid_S1, input wire [`MSG_SRC_X_WIDTH-1:0] msg_src_x_S1, input wire [`MSG_SRC_Y_WIDTH-1:0] msg_src_y_S1, + input wire [`MSG_SRC_X_WIDTH-1:0] msg_ini_x_S1, + input wire [`MSG_SRC_Y_WIDTH-1:0] msg_ini_y_S1, input wire [`MSG_SRC_FBITS_WIDTH-1:0] msg_src_fbits_S1, input wire [`MSG_SDID_WIDTH-1:0] msg_sdid_S1, input wire [`MSG_LSID_WIDTH-1:0] msg_lsid_S1, @@ -295,6 +298,8 @@ module l2_pipe1_dpath( output reg [`MSG_SRC_CHIPID_WIDTH-1:0] msg_send_dst_chipid_S4, output reg [`MSG_SRC_X_WIDTH-1:0] msg_send_dst_x_S4, output reg [`MSG_SRC_Y_WIDTH-1:0] msg_send_dst_y_S4, + output reg [`MSG_SRC_X_WIDTH-1:0] msg_send_ini_x_S4, + output reg [`MSG_SRC_Y_WIDTH-1:0] msg_send_ini_y_S4, output reg [`MSG_SRC_FBITS_WIDTH-1:0] msg_send_dst_fbits_S4, output reg [`L2_DATA_DATA_WIDTH-1:0] msg_send_data_S4, @@ -327,6 +332,8 @@ reg [`MSG_MSHRID_WIDTH-1:0] mshrid_S1; reg [`MSG_SRC_CHIPID_WIDTH-1:0] src_chipid_S1; reg [`MSG_SRC_X_WIDTH-1:0] src_x_S1; reg [`MSG_SRC_Y_WIDTH-1:0] src_y_S1; +reg [`MSG_SRC_X_WIDTH-1:0] ini_x_S1; +reg [`MSG_SRC_Y_WIDTH-1:0] ini_y_S1; reg [`MSG_SRC_FBITS_WIDTH-1:0] src_fbits_S1; reg [`MSG_SDID_WIDTH-1:0] sdid_S1; reg [`MSG_LSID_WIDTH-1:0] lsid_S1; @@ -344,6 +351,8 @@ begin src_chipid_S1 = mshr_src_chipid_S1; src_x_S1 = mshr_src_x_S1; src_y_S1 = mshr_src_y_S1; + ini_x_S1 = mshr_src_x_S1; + ini_y_S1 = mshr_src_y_S1; src_fbits_S1 = mshr_src_fbits_S1; sdid_S1 = mshr_sdid_S1; lsid_S1 = mshr_lsid_S1; @@ -355,6 +364,8 @@ begin src_chipid_S1 = pending_mshr_src_chipid_S1; src_x_S1 = pending_mshr_src_x_S1; src_y_S1 = pending_mshr_src_y_S1; + ini_x_S1 = pending_mshr_src_x_S1; + ini_y_S1 = pending_mshr_src_y_S1; src_fbits_S1 = pending_mshr_src_fbits_S1; sdid_S1 = pending_mshr_sdid_S1; lsid_S1 = pending_mshr_lsid_S1; @@ -369,6 +380,8 @@ begin src_chipid_S1 = msg_src_chipid_S1; src_x_S1 = msg_src_x_S1; src_y_S1 = msg_src_y_S1; + ini_x_S1 = msg_ini_x_S1; + ini_y_S1 = msg_ini_y_S1; src_fbits_S1 = msg_src_fbits_S1; sdid_S1 = msg_sdid_S1; lsid_S1 = msg_lsid_S1; @@ -468,6 +481,8 @@ reg [`MSG_MSHRID_WIDTH-1:0] mshrid_S2_f; reg [`MSG_SRC_CHIPID_WIDTH-1:0] src_chipid_S2_f; reg [`MSG_SRC_X_WIDTH-1:0] src_x_S2_f; reg [`MSG_SRC_Y_WIDTH-1:0] src_y_S2_f; +reg [`MSG_SRC_X_WIDTH-1:0] ini_x_S2_f; +reg [`MSG_SRC_Y_WIDTH-1:0] ini_y_S2_f; reg [`MSG_SRC_FBITS_WIDTH-1:0] src_fbits_S2_f; reg [`MSG_SDID_WIDTH-1:0] sdid_S2_f; reg [`MSG_LSID_WIDTH-1:0] lsid_S2_f; @@ -486,6 +501,8 @@ begin src_chipid_S2_f <= 0; src_x_S2_f <= 0; src_y_S2_f <= 0; + ini_x_S2_f <= 0; + ini_y_S2_f <= 0; src_fbits_S2_f <= 0; sdid_S2_f <= 0; lsid_S2_f <= 0; @@ -502,6 +519,8 @@ begin src_chipid_S2_f <= src_chipid_S1; src_x_S2_f <= src_x_S1; src_y_S2_f <= src_y_S1; + ini_x_S2_f <= ini_x_S1; + ini_y_S2_f <= ini_y_S1; src_fbits_S2_f <= src_fbits_S1; sdid_S2_f <= sdid_S1; lsid_S2_f <= lsid_S1; @@ -1344,6 +1363,8 @@ reg [`MSG_MSHRID_WIDTH-1:0] mshrid_S3_f; reg [`MSG_SRC_CHIPID_WIDTH-1:0] src_chipid_S3_f; reg [`MSG_SRC_X_WIDTH-1:0] src_x_S3_f; reg [`MSG_SRC_Y_WIDTH-1:0] src_y_S3_f; +reg [`MSG_SRC_X_WIDTH-1:0] ini_x_S3_f; +reg [`MSG_SRC_Y_WIDTH-1:0] ini_y_S3_f; reg [`MSG_SRC_FBITS_WIDTH-1:0] src_fbits_S3_f; reg [`MSG_SDID_WIDTH-1:0] sdid_S3_f; reg [`MSG_LSID_WIDTH-1:0] lsid_S3_f; @@ -1374,6 +1395,8 @@ begin src_chipid_S3_f <= 0; src_x_S3_f <= 0; src_y_S3_f <= 0; + ini_x_S3_f <= 0; + ini_y_S3_f <= 0; src_fbits_S3_f <= 0; sdid_S3_f <= 0; lsid_S3_f <= 0; @@ -1402,6 +1425,8 @@ begin src_chipid_S3_f <= src_chipid_S2_f; src_x_S3_f <= src_x_S2_f; src_y_S3_f <= src_y_S2_f; + ini_x_S3_f <= ini_x_S2_f; + ini_y_S3_f <= ini_y_S2_f; src_fbits_S3_f <= src_fbits_S2_f; sdid_S3_f <= sdid_S2_f; lsid_S3_f <= lsid_S2_f; @@ -1443,6 +1468,8 @@ reg [`MSG_MSHRID_WIDTH-1:0] mshrid_S4_f; reg [`MSG_SRC_CHIPID_WIDTH-1:0] src_chipid_S4_f; reg [`MSG_SRC_X_WIDTH-1:0] src_x_S4_f; reg [`MSG_SRC_Y_WIDTH-1:0] src_y_S4_f; +reg [`MSG_SRC_X_WIDTH-1:0] ini_x_S4_f; +reg [`MSG_SRC_Y_WIDTH-1:0] ini_y_S4_f; reg [`MSG_SRC_FBITS_WIDTH-1:0] src_fbits_S4_f; reg [`MSG_SDID_WIDTH-1:0] sdid_S4_f; reg [`MSG_LSID_WIDTH-1:0] lsid_S4_f; @@ -1476,6 +1503,8 @@ begin src_chipid_S4_f <= 0; src_x_S4_f <= 0; src_y_S4_f <= 0; + ini_x_S4_f <= 0; + ini_y_S4_f <= 0; src_fbits_S4_f <= 0; sdid_S4_f <= 0; lsid_S4_f <= 0; @@ -1504,6 +1533,8 @@ begin src_chipid_S4_f <= src_chipid_S3_f; src_x_S4_f <= src_x_S3_f; src_y_S4_f <= src_y_S3_f; + ini_x_S4_f <= ini_x_S3_f; + ini_y_S4_f <= ini_y_S3_f; src_fbits_S4_f <= src_fbits_S3_f; sdid_S4_f <= sdid_S3_f; lsid_S4_f <= lsid_S3_f; @@ -2050,6 +2081,8 @@ begin msg_send_dst_fbits_S4 = `NOC_FBITS_L1; end endcase + msg_send_ini_x_S4 = ini_x_S4_f; + msg_send_ini_y_S4 = ini_y_S4_f; end always @ * diff --git a/piton/design/chip/tile/l2/rtl/l2_to_mc.v.pyv b/piton/design/chip/tile/l2/rtl/l2_to_mc.v.pyv new file mode 100644 index 000000000..436af1a61 --- /dev/null +++ b/piton/design/chip/tile/l2/rtl/l2_to_mc.v.pyv @@ -0,0 +1,82 @@ +`include "define.tmp.h" + + + +module l2_to_mc ( + + input wire [`PHY_ADDR_WIDTH-1:0] msg_addr, + input wire [`NOC_X_WIDTH-1:0] coreid_x, + input wire [`NOC_Y_WIDTH-1:0] coreid_y, + + + output reg [`MSG_SRC_X_WIDTH-1:0] mc_dst_x, + output reg [`MSG_SRC_Y_WIDTH-1:0] mc_dst_y, + output reg [`MSG_SRC_FBITS_WIDTH-1:0] mc_dst_fbits + +); + + +// The destination MC should be selected according to msg_addr or L2 id. Currently its selected based on min Manhattan distance from L2 + +<% +import math +import sys + +import pyhplib +from pyhplib import * + +mmc=PITON_EXTRA_MEMS +if(mmc==0): + mmc=1 + PITON_MC_INDICES="0" + +lc_num=PITON_X_TILES*PITON_Y_TILES +lc_per_mmc=lc_num//mmc +if(lc_per_mmc*mmc !=lc_num): + lc_per_mmc+=1 + +print("//fbit declarations\n\t`define FBIT_NONE 4'b0000\n\t`define FBIT_W 4'b0010\n\t`define FBIT_S 4'b0011\n\t`define FBIT_E 4'b0100\n\t`define FBIT_N 4'b0101\n") +print("\t`define LC_NUM_PER_MC %d\n" %lc_per_mmc) + + + +MC_POS=get_mc_mapping(PITON_X_TILES,PITON_Y_TILES,PITON_MC_INDICES,mmc,PITON_NETWORK_CONFIG) +edge_idx=len(MC_POS) + +print("/*\n\tMC mapping table:\n \tMC# \tTile# \tTile_x \tTile_y \tPort\n") +for k in range(edge_idx): + print("\t%d \t%d \t%d \t%d \t%s" % (k, MC_POS[k]['id'], MC_POS[k]['x'], MC_POS[k]['y'],MC_POS[k]['p'] )) +print("*/") + + + + + + + +print ("always @ (*) begin\n \tmc_dst_fbits='b000;\tmc_dst_x=0;\tmc_dst_y=0;") + +#take the MC with minimum manhatan distance +for j in range(PITON_Y_TILES): + for i in range(PITON_X_TILES): + mind=1000000 + min_index=100000 + for k in range(edge_idx): + a = (MC_POS[k]['x'], MC_POS[k]['y']) + b = (i , j) + d = get_manhattan_distance(a, b) + + if(MC_POS[k]['n'] < lc_per_mmc and d < mind): + mind=d + min_index=k + + MC_POS[min_index]['n']+=1 + mc=j*PITON_X_TILES+i + print("//\tL2_id%d -> MC_id%d ; L2(%d,%d) -> MC(%d,%d) manhattan_dst %d" % (mc,min_index, i, j, MC_POS[min_index]['x'], MC_POS[min_index]['y'],mind)) + print("\tif (coreid_x == %d && coreid_y == %d) begin mc_dst_x = %d; mc_dst_y = %d; mc_dst_fbits = `FBIT_%s; end" %(i, j, MC_POS[min_index]['x'], MC_POS[min_index]['y'], MC_POS[min_index]['p'])) + +%> + +end //always + +endmodule diff --git a/piton/design/chipset/include/mc_define.h b/piton/design/chipset/include/mc_define.h index 133877099..e48548919 100644 --- a/piton/design/chipset/include/mc_define.h +++ b/piton/design/chipset/include/mc_define.h @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // ========== Copyright Header Begin ============================================ // Copyright (c) 2015 Princeton University // All rights reserved. @@ -86,6 +87,25 @@ `define DDR3_CS_WIDTH 1 `define DDR3_BG_WIDTH 1 `define DDR3_ODT_WIDTH 1 +`elsif ALVEO_BOARD + `define BOARD_MEM_SIZE_MB 8192 // Valid for HBM and DDR4 + `define WORDS_PER_BURST 8 + `define WORD_SIZE 8 // in bytes + `define MIG_APP_ADDR_WIDTH 31 + `define MIG_APP_CMD_WIDTH 3 + `define MIG_APP_DATA_WIDTH 512 + `define MIG_APP_MASK_WIDTH 64 + + `define DDR3_DQ_WIDTH 72 + `define DDR3_DQS_WIDTH 18 + `define DDR3_ADDR_WIDTH 17 + `define DDR3_BA_WIDTH 2 + `define DDR3_DM_WIDTH 8 + `define DDR3_CK_WIDTH 1 + `define DDR3_CKE_WIDTH 1 + `define DDR3_CS_WIDTH 1 + `define DDR3_BG_WIDTH 2 + `define DDR3_ODT_WIDTH 1 `elsif XUPP3R_BOARD `define BOARD_MEM_SIZE_MB 32768 `define WORDS_PER_BURST 8 @@ -179,3 +199,104 @@ `define DDR3_ODT_WIDTH 1 `endif + +//Verilog macro metaprogramming: https://veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf +// reassignment of multiple name-indexed AXI buses to/from vectorized ones +`define MC_AXI(idx) \ +\ +wire [`AXI4_ID_WIDTH -1:0] mcx_axi``idx``_awid = mcx_axi_awid [idx * `AXI4_ID_WIDTH +: `AXI4_ID_WIDTH ]; \ +wire [`AXI4_ADDR_WIDTH -1:0] mcx_axi``idx``_awaddr = mcx_axi_awaddr [idx * `AXI4_ADDR_WIDTH +: `AXI4_ADDR_WIDTH ]; \ +wire [`AXI4_LEN_WIDTH -1:0] mcx_axi``idx``_awlen = mcx_axi_awlen [idx * `AXI4_LEN_WIDTH +: `AXI4_LEN_WIDTH ]; \ +wire [`AXI4_SIZE_WIDTH -1:0] mcx_axi``idx``_awsize = mcx_axi_awsize [idx * `AXI4_SIZE_WIDTH +: `AXI4_SIZE_WIDTH ]; \ +wire [`AXI4_BURST_WIDTH -1:0] mcx_axi``idx``_awburst = mcx_axi_awburst [idx * `AXI4_BURST_WIDTH +: `AXI4_BURST_WIDTH ]; \ +wire mcx_axi``idx``_awlock = mcx_axi_awlock [idx ]; \ +wire [`AXI4_CACHE_WIDTH -1:0] mcx_axi``idx``_awcache = mcx_axi_awcache [idx * `AXI4_CACHE_WIDTH +: `AXI4_CACHE_WIDTH ]; \ +wire [`AXI4_PROT_WIDTH -1:0] mcx_axi``idx``_awprot = mcx_axi_awprot [idx * `AXI4_PROT_WIDTH +: `AXI4_PROT_WIDTH ]; \ +wire [`AXI4_QOS_WIDTH -1:0] mcx_axi``idx``_awqos = mcx_axi_awqos [idx * `AXI4_QOS_WIDTH +: `AXI4_QOS_WIDTH ]; \ +wire [`AXI4_REGION_WIDTH -1:0] mcx_axi``idx``_awregion = mcx_axi_awregion [idx * `AXI4_REGION_WIDTH +: `AXI4_REGION_WIDTH]; \ +wire [`AXI4_USER_WIDTH -1:0] mcx_axi``idx``_awuser = mcx_axi_awuser [idx * `AXI4_USER_WIDTH +: `AXI4_USER_WIDTH ]; \ +wire mcx_axi``idx``_awvalid = mcx_axi_awvalid [idx ]; \ +wire mcx_axi``idx``_awready; \ +assign mcx_axi_awready[idx] = mcx_axi``idx``_awready; \ +\ +wire [`AXI4_ID_WIDTH -1:0] mcx_axi``idx``_wid = mcx_axi_wid [idx * `AXI4_ID_WIDTH +: `AXI4_ID_WIDTH ]; \ +wire [`AXI4_DATA_WIDTH -1:0] mcx_axi``idx``_wdata = mcx_axi_wdata [idx * `AXI4_DATA_WIDTH +: `AXI4_DATA_WIDTH]; \ +wire [`AXI4_STRB_WIDTH -1:0] mcx_axi``idx``_wstrb = mcx_axi_wstrb [idx * `AXI4_STRB_WIDTH +: `AXI4_STRB_WIDTH]; \ +wire mcx_axi``idx``_wlast = mcx_axi_wlast [idx ]; \ +wire [`AXI4_USER_WIDTH -1:0] mcx_axi``idx``_wuser = mcx_axi_wuser [idx * `AXI4_USER_WIDTH +: `AXI4_USER_WIDTH]; \ +wire mcx_axi``idx``_wvalid = mcx_axi_wvalid [idx ]; \ +wire mcx_axi``idx``_wready; \ +assign mcx_axi_wready[idx] = mcx_axi``idx``_wready; \ +\ +wire [`AXI4_ID_WIDTH -1:0] mcx_axi``idx``_arid = mcx_axi_arid [idx * `AXI4_ID_WIDTH +: `AXI4_ID_WIDTH ]; \ +wire [`AXI4_ADDR_WIDTH -1:0] mcx_axi``idx``_araddr = mcx_axi_araddr [idx * `AXI4_ADDR_WIDTH +: `AXI4_ADDR_WIDTH ]; \ +wire [`AXI4_LEN_WIDTH -1:0] mcx_axi``idx``_arlen = mcx_axi_arlen [idx * `AXI4_LEN_WIDTH +: `AXI4_LEN_WIDTH ]; \ +wire [`AXI4_SIZE_WIDTH -1:0] mcx_axi``idx``_arsize = mcx_axi_arsize [idx * `AXI4_SIZE_WIDTH +: `AXI4_SIZE_WIDTH ]; \ +wire [`AXI4_BURST_WIDTH -1:0] mcx_axi``idx``_arburst = mcx_axi_arburst [idx * `AXI4_BURST_WIDTH +: `AXI4_BURST_WIDTH ]; \ +wire mcx_axi``idx``_arlock = mcx_axi_arlock [idx ]; \ +wire [`AXI4_CACHE_WIDTH -1:0] mcx_axi``idx``_arcache = mcx_axi_arcache [idx * `AXI4_CACHE_WIDTH +: `AXI4_CACHE_WIDTH ]; \ +wire [`AXI4_PROT_WIDTH -1:0] mcx_axi``idx``_arprot = mcx_axi_arprot [idx * `AXI4_PROT_WIDTH +: `AXI4_PROT_WIDTH ]; \ +wire [`AXI4_QOS_WIDTH -1:0] mcx_axi``idx``_arqos = mcx_axi_arqos [idx * `AXI4_QOS_WIDTH +: `AXI4_QOS_WIDTH ]; \ +wire [`AXI4_REGION_WIDTH -1:0] mcx_axi``idx``_arregion = mcx_axi_arregion [idx * `AXI4_REGION_WIDTH +: `AXI4_REGION_WIDTH]; \ +wire [`AXI4_USER_WIDTH -1:0] mcx_axi``idx``_aruser = mcx_axi_aruser [idx * `AXI4_USER_WIDTH +: `AXI4_USER_WIDTH ]; \ +wire mcx_axi``idx``_arvalid = mcx_axi_arvalid [idx ]; \ +wire mcx_axi``idx``_arready; \ +assign mcx_axi_arready[idx] = mcx_axi``idx``_arready; \ +\ +wire [`AXI4_ID_WIDTH -1:0] mcx_axi``idx``_rid; \ +wire [`AXI4_DATA_WIDTH -1:0] mcx_axi``idx``_rdata; \ +wire [`AXI4_RESP_WIDTH -1:0] mcx_axi``idx``_rresp; \ +wire mcx_axi``idx``_rlast; \ +wire [`AXI4_USER_WIDTH -1:0] mcx_axi``idx``_ruser; \ +wire mcx_axi``idx``_rvalid; \ +wire mcx_axi``idx``_rready = mcx_axi_rready[idx]; \ +assign mcx_axi_rid [idx * `AXI4_ID_WIDTH +: `AXI4_ID_WIDTH ] = mcx_axi``idx``_rid; \ +assign mcx_axi_rdata [idx * `AXI4_DATA_WIDTH +: `AXI4_DATA_WIDTH] = mcx_axi``idx``_rdata; \ +assign mcx_axi_rresp [idx * `AXI4_RESP_WIDTH +: `AXI4_RESP_WIDTH] = mcx_axi``idx``_rresp; \ +assign mcx_axi_rlast [idx ] = mcx_axi``idx``_rlast; \ +assign mcx_axi_ruser [idx * `AXI4_USER_WIDTH +: `AXI4_USER_WIDTH] = mcx_axi``idx``_ruser; \ +assign mcx_axi_rvalid[idx ] = mcx_axi``idx``_rvalid; \ +\ +wire [`AXI4_ID_WIDTH -1:0] mcx_axi``idx``_bid; \ +wire [`AXI4_RESP_WIDTH -1:0] mcx_axi``idx``_bresp; \ +wire [`AXI4_USER_WIDTH -1:0] mcx_axi``idx``_buser; \ +wire mcx_axi``idx``_bvalid; \ +wire mcx_axi``idx``_bready = mcx_axi_bready[idx]; \ +assign mcx_axi_bid [idx * `AXI4_ID_WIDTH +: `AXI4_ID_WIDTH ] = mcx_axi``idx``_bid; \ +assign mcx_axi_bresp [idx * `AXI4_RESP_WIDTH +: `AXI4_RESP_WIDTH] = mcx_axi``idx``_bresp; \ +assign mcx_axi_buser [idx * `AXI4_USER_WIDTH +: `AXI4_USER_WIDTH] = mcx_axi``idx``_buser; \ +assign mcx_axi_bvalid[idx ] = mcx_axi``idx``_bvalid; + +`define MCX_AXI_0 +`define MCX_AXI_1 `MCX_AXI_0 `MC_AXI(0) +`define MCX_AXI_2 `MCX_AXI_1 `MC_AXI(1) +`define MCX_AXI_3 `MCX_AXI_2 `MC_AXI(2) +`define MCX_AXI_4 `MCX_AXI_3 `MC_AXI(3) +`define MCX_AXI_5 `MCX_AXI_4 `MC_AXI(4) +`define MCX_AXI_6 `MCX_AXI_5 `MC_AXI(5) +`define MCX_AXI_7 `MCX_AXI_6 `MC_AXI(6) +`define MCX_AXI_8 `MCX_AXI_7 `MC_AXI(7) +`define MCX_AXI_9 `MCX_AXI_8 `MC_AXI(8) +`define MCX_AXI_10 `MCX_AXI_9 `MC_AXI(9) +`define MCX_AXI_11 `MCX_AXI_10 `MC_AXI(10) +`define MCX_AXI_12 `MCX_AXI_11 `MC_AXI(11) +`define MCX_AXI_13 `MCX_AXI_12 `MC_AXI(12) +`define MCX_AXI_14 `MCX_AXI_13 `MC_AXI(13) +`define MCX_AXI_15 `MCX_AXI_14 `MC_AXI(14) +`define MCX_AXI_16 `MCX_AXI_15 `MC_AXI(15) +`define MCX_AXI_17 `MCX_AXI_16 `MC_AXI(16) +`define MCX_AXI_18 `MCX_AXI_17 `MC_AXI(17) +`define MCX_AXI_19 `MCX_AXI_18 `MC_AXI(18) +`define MCX_AXI_20 `MCX_AXI_19 `MC_AXI(19) +`define MCX_AXI_21 `MCX_AXI_20 `MC_AXI(20) +`define MCX_AXI_22 `MCX_AXI_21 `MC_AXI(21) +`define MCX_AXI_23 `MCX_AXI_22 `MC_AXI(22) +`define MCX_AXI_24 `MCX_AXI_23 `MC_AXI(23) +`define MCX_AXI_25 `MCX_AXI_24 `MC_AXI(24) +`define MCX_AXI_26 `MCX_AXI_25 `MC_AXI(25) +`define MCX_AXI_27 `MCX_AXI_26 `MC_AXI(26) +`define MCX_AXI_28 `MCX_AXI_27 `MC_AXI(27) +`define MCX_AXI_29 `MCX_AXI_28 `MC_AXI(28) +`define MCX_AXI_30 `MCX_AXI_29 `MC_AXI(29) + +`define MCX_AXI(n) `MCX_AXI_``n diff --git a/piton/design/chipset/io_ctrl/rtl/ciop_iob.v b/piton/design/chipset/io_ctrl/rtl/ciop_iob.v index c955e1d71..95b076267 100644 --- a/piton/design/chipset/io_ctrl/rtl/ciop_iob.v +++ b/piton/design/chipset/io_ctrl/rtl/ciop_iob.v @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // Copyright (c) 2015 Princeton University // All rights reserved. // @@ -150,7 +151,7 @@ always @(posedge fpga_clk) begin end else begin flit_cnt <= flit_cnt; -`ifdef PITON_FPGA_ETHERNETLITE +`ifdef PITON_FPGA_ETH if (pending_net_interrupt & ~uart_interrupt_in_prog) begin net_flit_cnt <= 2'b0; pending_net_interrupt <= 1'b0; @@ -202,7 +203,7 @@ always @(posedge fpga_clk) begin end assign noc2_out_val = iob_buffer_val & (((flit_cnt < FLIT_TO_SEND) && !ok_iob_sent) -`ifdef PITON_FPGA_ETHERNETLITE +`ifdef PITON_FPGA_ETH || (ok_iob_sent & net_interrupt_in_prog & (net_flit_cnt < FLIT_TO_SEND)) `endif `ifdef PITON_UART_INTR @@ -222,7 +223,7 @@ always @(*) begin end end else begin -`ifdef PITON_FPGA_ETHERNETLITE +`ifdef PITON_FPGA_ETH if (net_interrupt_in_prog) begin if(net_flit_cnt == 2'b0) begin noc2_out_data = iob_buffer_flit1; @@ -240,7 +241,7 @@ always @(*) begin `endif `endif -`ifdef PITON_FPGA_ETHERNETLITE +`ifdef PITON_FPGA_ETH `ifdef PITON_UART_INTR // Make the uart_ one an else if in the case they're both defined else @@ -258,14 +259,14 @@ always @(*) begin noc2_out_data = {`NOC_DATA_WIDTH{1'b0}}; end end -`ifndef PITON_FPGA_ETHERNETLITE +`ifndef PITON_FPGA_ETH else begin noc2_out_data = {`NOC_DATA_WIDTH{1'b0}}; end `endif `endif -`ifdef PITON_FPGA_ETHERNETLITE +`ifdef PITON_FPGA_ETH `ifdef PITON_UART_INTR else begin noc2_out_data = {`NOC_DATA_WIDTH{1'b0}}; @@ -273,7 +274,7 @@ always @(*) begin `endif `endif -`ifndef PITON_FPGA_ETHERNETLITE +`ifndef PITON_FPGA_ETH `ifndef PITON_UART_INTR noc2_out_data = {`NOC_DATA_WIDTH{1'b0}}; `endif diff --git a/piton/design/chipset/io_ctrl/rtl/eth_top.v b/piton/design/chipset/io_ctrl/rtl/eth_top.v index bb326e9d9..8a96af360 100644 --- a/piton/design/chipset/io_ctrl/rtl/eth_top.v +++ b/piton/design/chipset/io_ctrl/rtl/eth_top.v @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // ========== Copyright Header Begin ============================================ // Copyright (c) 2017 Princeton University // All rights reserved. @@ -32,14 +33,21 @@ // Created: 1/25/2017 //-------------------------------------------------- +`ifdef PITON_FPGA_ETH +`ifndef PITON_FPGA_ETHERNETLITE +`include "noc_axi4_bridge_define.vh" +`endif +`endif + module eth_top #( - parameter SWAP_ENDIANESS = 0 + parameter SWAP_ENDIANESS = 0, + parameter NUM_INTR = 1 ) ( input chipset_clk, input rst_n, - output net_interrupt, + output [NUM_INTR-1:0] net_interrupt, input noc_in_val, input [`NOC_DATA_WIDTH-1:0] noc_in_data, @@ -47,8 +55,10 @@ module eth_top #( output noc_out_val, output [`NOC_DATA_WIDTH-1:0] noc_out_data, - input noc_out_rdy, + input noc_out_rdy +`ifdef PITON_FPGA_ETHERNETLITE + , input net_axi_clk, output net_phy_rst_n, @@ -63,9 +73,178 @@ module eth_top #( inout net_phy_mdio_io, output net_phy_mdc +`elsif PITON_FPGA_ETH_CMAC // PITON_FPGA_ETHERNETLITE + , + // Eth DMA master channels + output [`AXI4_ID_WIDTH -1:0] eth_sg_dma_awid, + output [`AXI4_ADDR_WIDTH -1:0] eth_sg_dma_awaddr, + output [`AXI4_LEN_WIDTH -1:0] eth_sg_dma_awlen, + output [`AXI4_SIZE_WIDTH -1:0] eth_sg_dma_awsize, + output [`AXI4_BURST_WIDTH -1:0] eth_sg_dma_awburst, + output eth_sg_dma_awlock, + output [`AXI4_CACHE_WIDTH -1:0] eth_sg_dma_awcache, + output [`AXI4_PROT_WIDTH -1:0] eth_sg_dma_awprot, + output [`AXI4_QOS_WIDTH -1:0] eth_sg_dma_awqos, + output [`AXI4_REGION_WIDTH -1:0] eth_sg_dma_awregion, + output [`AXI4_USER_WIDTH -1:0] eth_sg_dma_awuser, + output eth_sg_dma_awvalid, + input eth_sg_dma_awready, + + output [`AXI4_ID_WIDTH -1:0] eth_sg_dma_wid, + output [`AXI4_DATA_WIDTH -1:0] eth_sg_dma_wdata, + output [`AXI4_STRB_WIDTH -1:0] eth_sg_dma_wstrb, + output eth_sg_dma_wlast, + output [`AXI4_USER_WIDTH -1:0] eth_sg_dma_wuser, + output eth_sg_dma_wvalid, + input eth_sg_dma_wready, + + output [`AXI4_ID_WIDTH -1:0] eth_sg_dma_arid, + output [`AXI4_ADDR_WIDTH -1:0] eth_sg_dma_araddr, + output [`AXI4_LEN_WIDTH -1:0] eth_sg_dma_arlen, + output [`AXI4_SIZE_WIDTH -1:0] eth_sg_dma_arsize, + output [`AXI4_BURST_WIDTH -1:0] eth_sg_dma_arburst, + output eth_sg_dma_arlock, + output [`AXI4_CACHE_WIDTH -1:0] eth_sg_dma_arcache, + output [`AXI4_PROT_WIDTH -1:0] eth_sg_dma_arprot, + output [`AXI4_QOS_WIDTH -1:0] eth_sg_dma_arqos, + output [`AXI4_REGION_WIDTH -1:0] eth_sg_dma_arregion, + output [`AXI4_USER_WIDTH -1:0] eth_sg_dma_aruser, + output eth_sg_dma_arvalid, + input eth_sg_dma_arready, + + input [`AXI4_ID_WIDTH -1:0] eth_sg_dma_rid, + input [`AXI4_DATA_WIDTH -1:0] eth_sg_dma_rdata, + input [`AXI4_RESP_WIDTH -1:0] eth_sg_dma_rresp, + input eth_sg_dma_rlast, + input [`AXI4_USER_WIDTH -1:0] eth_sg_dma_ruser, + input eth_sg_dma_rvalid, + output eth_sg_dma_rready, + + input [`AXI4_ID_WIDTH -1:0] eth_sg_dma_bid, + input [`AXI4_RESP_WIDTH -1:0] eth_sg_dma_bresp, + input [`AXI4_USER_WIDTH -1:0] eth_sg_dma_buser, + input eth_sg_dma_bvalid, + output eth_sg_dma_bready, + + + output [`AXI4_ID_WIDTH -1:0] eth_tx_dma_awid, + output [`AXI4_ADDR_WIDTH -1:0] eth_tx_dma_awaddr, + output [`AXI4_LEN_WIDTH -1:0] eth_tx_dma_awlen, + output [`AXI4_SIZE_WIDTH -1:0] eth_tx_dma_awsize, + output [`AXI4_BURST_WIDTH -1:0] eth_tx_dma_awburst, + output eth_tx_dma_awlock, + output [`AXI4_CACHE_WIDTH -1:0] eth_tx_dma_awcache, + output [`AXI4_PROT_WIDTH -1:0] eth_tx_dma_awprot, + output [`AXI4_QOS_WIDTH -1:0] eth_tx_dma_awqos, + output [`AXI4_REGION_WIDTH -1:0] eth_tx_dma_awregion, + output [`AXI4_USER_WIDTH -1:0] eth_tx_dma_awuser, + output eth_tx_dma_awvalid, + input eth_tx_dma_awready, + + output [`AXI4_ID_WIDTH -1:0] eth_tx_dma_wid, + output [`AXI4_DATA_WIDTH -1:0] eth_tx_dma_wdata, + output [`AXI4_STRB_WIDTH -1:0] eth_tx_dma_wstrb, + output eth_tx_dma_wlast, + output [`AXI4_USER_WIDTH -1:0] eth_tx_dma_wuser, + output eth_tx_dma_wvalid, + input eth_tx_dma_wready, + + output [`AXI4_ID_WIDTH -1:0] eth_tx_dma_arid, + output [`AXI4_ADDR_WIDTH -1:0] eth_tx_dma_araddr, + output [`AXI4_LEN_WIDTH -1:0] eth_tx_dma_arlen, + output [`AXI4_SIZE_WIDTH -1:0] eth_tx_dma_arsize, + output [`AXI4_BURST_WIDTH -1:0] eth_tx_dma_arburst, + output eth_tx_dma_arlock, + output [`AXI4_CACHE_WIDTH -1:0] eth_tx_dma_arcache, + output [`AXI4_PROT_WIDTH -1:0] eth_tx_dma_arprot, + output [`AXI4_QOS_WIDTH -1:0] eth_tx_dma_arqos, + output [`AXI4_REGION_WIDTH -1:0] eth_tx_dma_arregion, + output [`AXI4_USER_WIDTH -1:0] eth_tx_dma_aruser, + output eth_tx_dma_arvalid, + input eth_tx_dma_arready, + + input [`AXI4_ID_WIDTH -1:0] eth_tx_dma_rid, + input [`AXI4_DATA_WIDTH -1:0] eth_tx_dma_rdata, + input [`AXI4_RESP_WIDTH -1:0] eth_tx_dma_rresp, + input eth_tx_dma_rlast, + input [`AXI4_USER_WIDTH -1:0] eth_tx_dma_ruser, + input eth_tx_dma_rvalid, + output eth_tx_dma_rready, + + input [`AXI4_ID_WIDTH -1:0] eth_tx_dma_bid, + input [`AXI4_RESP_WIDTH -1:0] eth_tx_dma_bresp, + input [`AXI4_USER_WIDTH -1:0] eth_tx_dma_buser, + input eth_tx_dma_bvalid, + output eth_tx_dma_bready, + + output eth_tx_dma_clk, + output eth_tx_dma_rstn, + + + output [`AXI4_ID_WIDTH -1:0] eth_rx_dma_awid, + output [`AXI4_ADDR_WIDTH -1:0] eth_rx_dma_awaddr, + output [`AXI4_LEN_WIDTH -1:0] eth_rx_dma_awlen, + output [`AXI4_SIZE_WIDTH -1:0] eth_rx_dma_awsize, + output [`AXI4_BURST_WIDTH -1:0] eth_rx_dma_awburst, + output eth_rx_dma_awlock, + output [`AXI4_CACHE_WIDTH -1:0] eth_rx_dma_awcache, + output [`AXI4_PROT_WIDTH -1:0] eth_rx_dma_awprot, + output [`AXI4_QOS_WIDTH -1:0] eth_rx_dma_awqos, + output [`AXI4_REGION_WIDTH -1:0] eth_rx_dma_awregion, + output [`AXI4_USER_WIDTH -1:0] eth_rx_dma_awuser, + output eth_rx_dma_awvalid, + input eth_rx_dma_awready, + + output [`AXI4_ID_WIDTH -1:0] eth_rx_dma_wid, + output [`AXI4_DATA_WIDTH -1:0] eth_rx_dma_wdata, + output [`AXI4_STRB_WIDTH -1:0] eth_rx_dma_wstrb, + output eth_rx_dma_wlast, + output [`AXI4_USER_WIDTH -1:0] eth_rx_dma_wuser, + output eth_rx_dma_wvalid, + input eth_rx_dma_wready, + + output [`AXI4_ID_WIDTH -1:0] eth_rx_dma_arid, + output [`AXI4_ADDR_WIDTH -1:0] eth_rx_dma_araddr, + output [`AXI4_LEN_WIDTH -1:0] eth_rx_dma_arlen, + output [`AXI4_SIZE_WIDTH -1:0] eth_rx_dma_arsize, + output [`AXI4_BURST_WIDTH -1:0] eth_rx_dma_arburst, + output eth_rx_dma_arlock, + output [`AXI4_CACHE_WIDTH -1:0] eth_rx_dma_arcache, + output [`AXI4_PROT_WIDTH -1:0] eth_rx_dma_arprot, + output [`AXI4_QOS_WIDTH -1:0] eth_rx_dma_arqos, + output [`AXI4_REGION_WIDTH -1:0] eth_rx_dma_arregion, + output [`AXI4_USER_WIDTH -1:0] eth_rx_dma_aruser, + output eth_rx_dma_arvalid, + input eth_rx_dma_arready, + + input [`AXI4_ID_WIDTH -1:0] eth_rx_dma_rid, + input [`AXI4_DATA_WIDTH -1:0] eth_rx_dma_rdata, + input [`AXI4_RESP_WIDTH -1:0] eth_rx_dma_rresp, + input eth_rx_dma_rlast, + input [`AXI4_USER_WIDTH -1:0] eth_rx_dma_ruser, + input eth_rx_dma_rvalid, + output eth_rx_dma_rready, + + input [`AXI4_ID_WIDTH -1:0] eth_rx_dma_bid, + input [`AXI4_RESP_WIDTH -1:0] eth_rx_dma_bresp, + input [`AXI4_USER_WIDTH -1:0] eth_rx_dma_buser, + input eth_rx_dma_bvalid, + output eth_rx_dma_bready, + + output eth_rx_dma_clk, + output eth_rx_dma_rstn, + + input eth_init_clk, + input qsfp_ref_clk_n, + input qsfp_ref_clk_p, + input [3:0] qsfp_4x_grx_n, + input [3:0] qsfp_4x_grx_p, + output [3:0] qsfp_4x_gtx_n, + output [3:0] qsfp_4x_gtx_p +`endif // PITON_FPGA_ETH_CMAC ); -`ifdef PITON_FPGA_ETHERNETLITE +`ifdef PITON_FPGA_ETH // afifo <-> netbridge wire afifo_netbridge_val; @@ -77,25 +256,26 @@ wire [`NOC_DATA_WIDTH-1:0] netbridge_afifo_data; wire fifo_netbridge_rdy; // netbridge <-> mac axi -wire [12:0] net_s_axi_awaddr; +`ifdef PITON_FPGA_ETHERNETLITE +wire [`C_M_AXI_LITE_ADDR_WIDTH-1:0] net_s_axi_awaddr; wire net_s_axi_awvalid; wire net_s_axi_awready; -wire [31:0] net_s_axi_wdata; -wire [3:0] net_s_axi_wstrb; +wire [`C_M_AXI_LITE_DATA_WIDTH-1:0] net_s_axi_wdata; +wire [`C_M_AXI_LITE_DATA_WIDTH/8-1:0] net_s_axi_wstrb; wire net_s_axi_wvalid; wire net_s_axi_wready; -wire [1:0] net_s_axi_bresp; +wire [`C_M_AXI_LITE_RESP_WIDTH-1:0] net_s_axi_bresp; wire net_s_axi_bvalid; wire net_s_axi_bready; -wire [12:0] net_s_axi_araddr; +wire [`C_M_AXI_LITE_ADDR_WIDTH-1:0] net_s_axi_araddr; wire net_s_axi_arvalid; wire net_s_axi_arready; -wire [31:0] net_s_axi_rdata; -wire [1:0] net_s_axi_rresp; +wire [`C_M_AXI_LITE_DATA_WIDTH-1:0] net_s_axi_rdata; +wire [`C_M_AXI_LITE_RESP_WIDTH-1:0] net_s_axi_rresp; wire net_s_axi_rvalid; wire net_s_axi_rready; @@ -107,14 +287,79 @@ wire net_phy_mdio_t; wire net_phy_crs = 1'b0; wire net_phy_col = 1'b0; +wire net_axi_arstn = rst_n; (* dont_touch = "true" *) wire unsync_net_int; +`else // PITON_FPGA_ETHERNETLITE, full AXI4 for rest Eth cores +wire [`AXI4_ID_WIDTH -1:0] core_axi_awid; +wire [`AXI4_ADDR_WIDTH -1:0] core_axi_awaddr; +wire [`AXI4_LEN_WIDTH -1:0] core_axi_awlen; +wire [`AXI4_SIZE_WIDTH -1:0] core_axi_awsize; +wire [`AXI4_BURST_WIDTH -1:0] core_axi_awburst; +wire core_axi_awlock; +wire [`AXI4_CACHE_WIDTH -1:0] core_axi_awcache; +wire [`AXI4_PROT_WIDTH -1:0] core_axi_awprot; +wire [`AXI4_QOS_WIDTH -1:0] core_axi_awqos; +wire [`AXI4_REGION_WIDTH -1:0] core_axi_awregion; +wire [`AXI4_USER_WIDTH -1:0] core_axi_awuser; +wire core_axi_awvalid; +wire core_axi_awready; + +wire [`AXI4_ID_WIDTH -1:0] core_axi_wid; +wire [`AXI4_DATA_WIDTH -1:0] core_axi_wdata; +wire [`AXI4_STRB_WIDTH -1:0] core_axi_wstrb; +wire core_axi_wlast; +wire [`AXI4_USER_WIDTH -1:0] core_axi_wuser; +wire core_axi_wvalid; +wire core_axi_wready; + +wire [`AXI4_ID_WIDTH -1:0] core_axi_arid; +wire [`AXI4_ADDR_WIDTH -1:0] core_axi_araddr; +wire [`AXI4_LEN_WIDTH -1:0] core_axi_arlen; +wire [`AXI4_SIZE_WIDTH -1:0] core_axi_arsize; +wire [`AXI4_BURST_WIDTH -1:0] core_axi_arburst; +wire core_axi_arlock; +wire [`AXI4_CACHE_WIDTH -1:0] core_axi_arcache; +wire [`AXI4_PROT_WIDTH -1:0] core_axi_arprot; +wire [`AXI4_QOS_WIDTH -1:0] core_axi_arqos; +wire [`AXI4_REGION_WIDTH -1:0] core_axi_arregion; +wire [`AXI4_USER_WIDTH -1:0] core_axi_aruser; +wire core_axi_arvalid; +wire core_axi_arready; + +wire [`AXI4_ID_WIDTH -1:0] core_axi_rid; +wire [`AXI4_DATA_WIDTH -1:0] core_axi_rdata; +wire [`AXI4_RESP_WIDTH -1:0] core_axi_rresp; +wire core_axi_rlast; +wire [`AXI4_USER_WIDTH -1:0] core_axi_ruser; +wire core_axi_rvalid; +wire core_axi_rready; + +wire [`AXI4_ID_WIDTH -1:0] core_axi_bid; +wire [`AXI4_RESP_WIDTH -1:0] core_axi_bresp; +wire [`AXI4_USER_WIDTH -1:0] core_axi_buser; +wire core_axi_bvalid; +wire core_axi_bready; + +wire net_axi_clk = chipset_clk; +wire net_axi_arstn = rst_n; +wire [NUM_INTR-1:0] unsync_net_int; +`endif + + +`ifndef PITON_FPGA_ETH_CMAC +`ifndef PITON_FPGA_ETHERNETLITE + `define NO_ETH_CORE +`endif +`endif + +`ifndef NO_ETH_CORE noc_bidir_afifo net_afifo ( .clk_1 (chipset_clk ), .rst_1 (~rst_n ), .clk_2 (net_axi_clk ), - .rst_2 (~rst_n ), + .rst_2 (~net_axi_arstn ), // CPU --> EMACLITE .flit_in_val_1 (noc_in_val ), @@ -134,7 +379,18 @@ noc_bidir_afifo net_afifo ( .flit_out_data_1 (noc_out_data ), .flit_out_rdy_1 (noc_out_rdy ) ); +`else // NO_ETH_CORE + // NO ETHERNET CORE + assign afifo_netbridge_val = noc_in_val; + assign afifo_netbridge_data = noc_in_data; + assign noc_in_rdy = netbridge_afifo_rdy; + assign noc_out_val = netbridge_afifo_val; + assign noc_out_data = netbridge_afifo_data; + assign afifo_netbridge_rdy = noc_out_rdy; +`endif + +`ifdef PITON_FPGA_ETHERNETLITE noc_axilite_bridge #( .SLAVE_RESP_BYTEWIDTH (4), .SWAP_ENDIANESS (SWAP_ENDIANESS) @@ -179,14 +435,89 @@ noc_axilite_bridge #( .m_axi_bready (net_s_axi_bready) ); +`else // PITON_FPGA_ETHERNETLITE, full AXI4 for rest Eth cores +noc_axi4_bridge #( + .SWAP_ENDIANESS (SWAP_ENDIANESS) +) noc_ethernet_bridge ( + .clk (net_axi_clk ), + .rst_n (net_axi_arstn ), + .uart_boot_en (1'b0 ), + .phy_init_done (1'b1 ), + + .src_bridge_vr_noc2_val(afifo_netbridge_val ), + .src_bridge_vr_noc2_dat(afifo_netbridge_data), + .src_bridge_vr_noc2_rdy(netbridge_afifo_rdy ), + + .bridge_dst_vr_noc3_val(netbridge_afifo_val ), + .bridge_dst_vr_noc3_dat(netbridge_afifo_data), + .bridge_dst_vr_noc3_rdy(afifo_netbridge_rdy ), + + .m_axi_awid(core_axi_awid), + .m_axi_awaddr(core_axi_awaddr), + .m_axi_awlen(core_axi_awlen), + .m_axi_awsize(core_axi_awsize), + .m_axi_awburst(core_axi_awburst), + .m_axi_awlock(core_axi_awlock), + .m_axi_awcache(core_axi_awcache), + .m_axi_awprot(core_axi_awprot), + .m_axi_awqos(core_axi_awqos), + .m_axi_awregion(core_axi_awregion), + .m_axi_awuser(core_axi_awuser), + .m_axi_awvalid(core_axi_awvalid), + .m_axi_awready(core_axi_awready), + + .m_axi_wid(core_axi_wid), + .m_axi_wdata(core_axi_wdata), + .m_axi_wstrb(core_axi_wstrb), + .m_axi_wlast(core_axi_wlast), + .m_axi_wuser(core_axi_wuser), + .m_axi_wvalid(core_axi_wvalid), + .m_axi_wready(core_axi_wready), + + .m_axi_bid(core_axi_bid), + .m_axi_bresp(core_axi_bresp), + .m_axi_buser(core_axi_buser), + .m_axi_bvalid(core_axi_bvalid), + .m_axi_bready(core_axi_bready), + + .m_axi_arid(core_axi_arid), + .m_axi_araddr(core_axi_araddr), + .m_axi_arlen(core_axi_arlen), + .m_axi_arsize(core_axi_arsize), + .m_axi_arburst(core_axi_arburst), + .m_axi_arlock(core_axi_arlock), + .m_axi_arcache(core_axi_arcache), + .m_axi_arprot(core_axi_arprot), + .m_axi_arqos(core_axi_arqos), + .m_axi_arregion(core_axi_arregion), + .m_axi_aruser(core_axi_aruser), + .m_axi_arvalid(core_axi_arvalid), + .m_axi_arready(core_axi_arready), + + .m_axi_rid(core_axi_rid), + .m_axi_rdata(core_axi_rdata), + .m_axi_rresp(core_axi_rresp), + .m_axi_rlast(core_axi_rlast), + .m_axi_ruser(core_axi_ruser), + .m_axi_rvalid(core_axi_rvalid), + .m_axi_rready(core_axi_rready) +); +`endif + +generate +genvar idx; +for(idx=0; idx to <0>. + +set run_remote_bd_flow 1 +if { $run_remote_bd_flow == 1 } { + # Set the reference directory for source file relative paths (by default + # the value is script directory path) + set origin_dir ./bd + + # Use origin directory path location variable, if specified in the tcl shell + if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc + } + + set str_bd_folder [file normalize ${origin_dir}] + set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd + + # Check if remote design exists on disk + if { [file exists $str_bd_filepath ] == 1 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2030 -severity "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"} + common::send_gid_msg -ssname BD::TCL -id 2031 -severity "INFO" "To create a non-remote BD, change the variable to <0>." + common::send_gid_msg -ssname BD::TCL -id 2032 -severity "INFO" "Also make sure there is no design <$design_name> existing in your current project." + + return 1 + } + + # Check if design exists in memory + set list_existing_designs [get_bd_designs -quiet $design_name] + if { $list_existing_designs ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2033 -severity "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."} + + common::send_gid_msg -ssname BD::TCL -id 2034 -severity "INFO" "To create a non-remote BD, change the variable to <0> or please set a different value to variable ." + + return 1 + } + + # Check if design exists on disk within project + set list_existing_designs [get_files -quiet */${design_name}.bd] + if { $list_existing_designs ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2035 -severity "ERROR" "The design <$design_name> already exists in this project at location: + $list_existing_designs"} + catch {common::send_gid_msg -ssname BD::TCL -id 2036 -severity "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."} + + common::send_gid_msg -ssname BD::TCL -id 2037 -severity "INFO" "To create a non-remote BD, change the variable to <0> or please set a different value to variable ." + + return 1 + } + + # Now can create the remote BD + # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd> + create_bd_design -dir $str_bd_folder $design_name +} else { + + # Create regular design + if { [catch {create_bd_design $design_name} errmsg] } { + common::send_gid_msg -ssname BD::TCL -id 2038 -severity "INFO" "Please set a different value to variable ." + + return 1 + } +} + +current_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:debug_bridge:3.0\ + xilinx.com:ip:bscan_jtag:1.0\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + set bscan_prim [ create_bd_cell -type ip -vlnv xilinx.com:ip:debug_bridge:3.0 bscan_prim ] + set_property -dict [ list \ + CONFIG.C_DEBUG_MODE {7} \ + CONFIG.C_NUM_BS_MASTER {2} \ + ] $bscan_prim + set debug_hub [ create_bd_cell -type ip -vlnv xilinx.com:ip:debug_bridge:3.0 debug_hub ] + set bscan2jtag [ create_bd_cell -type ip -vlnv xilinx.com:ip:bscan_jtag:1.0 bscan2jtag ] + + connect_bd_intf_net [get_bd_intf_pins bscan_prim/m1_bscan] [get_bd_intf_pins debug_hub/S_BSCAN ] + connect_bd_intf_net [get_bd_intf_pins bscan_prim/m0_bscan] [get_bd_intf_pins bscan2jtag/S_BSCAN] + + make_bd_intf_pins_external [get_bd_intf_pins bscan2jtag/M_JTAG] + set_property name "dbg_jtag" [get_bd_intf_ports M_JTAG_0] + make_bd_pins_external [get_bd_pins debug_hub/clk] + set_property name "dbghub_clk" [get_bd_ports clk_0] + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_jtag_shell() + +cr_bd_jtag_shell "" diff --git a/piton/design/chipset/meep/meep_shell.tcl b/piton/design/chipset/meep/meep_shell.tcl new file mode 100644 index 000000000..f01d0b29a --- /dev/null +++ b/piton/design/chipset/meep/meep_shell.tcl @@ -0,0 +1,889 @@ +# Copyright 2022 Barcelona Supercomputing Center-Centro Nacional de Supercomputación + +# Licensed under the Solderpad Hardware License v 2.1 (the "License"); +# you may not use this file except in compliance with the License, or, at your option, the Apache License version 2.0. +# You may obtain a copy of the License at +# +# http://www.solderpad.org/licenses/SHL-2.1 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Author: Alexander Kropotov, BSC-CNS +# Date: 10.12.2023 +# Description: + +# Proc to create BD meep_shell +proc cr_bd_meep_shell { parentCell } { + + # CHANGE DESIGN NAME HERE + set design_name meep_shell + +# This script was generated for a remote BD. To create a non-remote design, +# change the variable to <0>. + +set run_remote_bd_flow 1 +if { $run_remote_bd_flow == 1 } { + # Set the reference directory for source file relative paths (by default + # the value is script directory path) + set origin_dir ./bd + + # Use origin directory path location variable, if specified in the tcl shell + if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc + } + + set str_bd_folder [file normalize ${origin_dir}] + set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd + + # Check if remote design exists on disk + if { [file exists $str_bd_filepath ] == 1 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2030 -severity "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"} + common::send_gid_msg -ssname BD::TCL -id 2031 -severity "INFO" "To create a non-remote BD, change the variable to <0>." + common::send_gid_msg -ssname BD::TCL -id 2032 -severity "INFO" "Also make sure there is no design <$design_name> existing in your current project." + + return 1 + } + + # Check if design exists in memory + set list_existing_designs [get_bd_designs -quiet $design_name] + if { $list_existing_designs ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2033 -severity "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."} + + common::send_gid_msg -ssname BD::TCL -id 2034 -severity "INFO" "To create a non-remote BD, change the variable to <0> or please set a different value to variable ." + + return 1 + } + + # Check if design exists on disk within project + set list_existing_designs [get_files -quiet */${design_name}.bd] + if { $list_existing_designs ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2035 -severity "ERROR" "The design <$design_name> already exists in this project at location: + $list_existing_designs"} + catch {common::send_gid_msg -ssname BD::TCL -id 2036 -severity "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."} + + common::send_gid_msg -ssname BD::TCL -id 2037 -severity "INFO" "To create a non-remote BD, change the variable to <0> or please set a different value to variable ." + + return 1 + } + + # Now can create the remote BD + # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd> + create_bd_design -dir $str_bd_folder $design_name +} else { + + # Create regular design + if { [catch {create_bd_design $design_name} errmsg] } { + common::send_gid_msg -ssname BD::TCL -id 2038 -severity "INFO" "Please set a different value to variable ." + + return 1 + } +} + +current_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:axi_gpio:2.0\ + xilinx.com:ip:ddr4:2.2\ + xilinx.com:ip:util_vector_logic:2.0\ + xilinx.com:ip:axi_bram_ctrl:4.1\ + xilinx.com:ip:xlconstant:1.1\ + xilinx.com:ip:hbm:1.0\ + xilinx.com:ip:proc_sys_reset:5.0\ + xilinx.com:ip:qdma:5.0\ + xilinx.com:ip:smartconnect:1.0\ + xilinx.com:ip:util_ds_buf:2.2\ + xilinx.com:ip:blk_mem_gen:8.4\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set mem_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mem_refclk ] + if {[info exists ::env(PROTOSYN_RUNTIME_BOARD)] && + $::env(PROTOSYN_RUNTIME_BOARD)=="alveou250"} { + set_property -dict [ list CONFIG.FREQ_HZ 300000000] $mem_refclk + } else { + set_property -dict [ list CONFIG.FREQ_HZ 100000000] $mem_refclk + } + + if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE" && + [info exists ::env(PROTOSYN_RUNTIME_BOARD)] && + $::env(PROTOSYN_RUNTIME_BOARD)=="alveou280"} { + set DRAM_addr_width 33 + } else { + set DRAM_addr_width 34 + } + + set m_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH $DRAM_addr_width \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {256} \ + CONFIG.NUM_READ_THREADS {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {256} \ + CONFIG.NUM_WRITE_THREADS {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $m_axi +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + set_property CONFIG.PROTOCOL {AXI3} [get_bd_intf_ports m_axi] + set_property CONFIG.DATA_WIDTH {256} [get_bd_intf_ports m_axi] + set_property CONFIG.MAX_BURST_LENGTH {16} [get_bd_intf_ports m_axi] +} + +if {[info exists ::env(PROTOSYN_RUNTIME_ETH)] && + $::env(PROTOSYN_RUNTIME_ETH)=="TRUE"} { + set eth_sg_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 eth_sg_dma ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH $DRAM_addr_width \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {256} \ + CONFIG.NUM_READ_THREADS {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {256} \ + CONFIG.NUM_WRITE_THREADS {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $eth_sg_dma +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + set_property CONFIG.PROTOCOL {AXI3} [get_bd_intf_ports eth_sg_dma] + set_property CONFIG.DATA_WIDTH {256} [get_bd_intf_ports eth_sg_dma] + set_property CONFIG.MAX_BURST_LENGTH {16} [get_bd_intf_ports eth_sg_dma] +} + + set eth_tx_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 eth_tx_dma ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH $DRAM_addr_width \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {256} \ + CONFIG.NUM_READ_THREADS {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {256} \ + CONFIG.NUM_WRITE_THREADS {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $eth_tx_dma +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + set_property CONFIG.PROTOCOL {AXI3} [get_bd_intf_ports eth_tx_dma] + set_property CONFIG.DATA_WIDTH {256} [get_bd_intf_ports eth_tx_dma] + set_property CONFIG.MAX_BURST_LENGTH {16} [get_bd_intf_ports eth_tx_dma] +} + + set eth_tx_dma_clk [ create_bd_port -dir I -type clk eth_tx_dma_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {eth_tx_dma} \ + ] $eth_tx_dma_clk + set eth_tx_dma_rstn [ create_bd_port -dir I -type rst eth_tx_dma_rstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $eth_tx_dma_rstn + + set eth_rx_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 eth_rx_dma ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH $DRAM_addr_width \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {256} \ + CONFIG.NUM_READ_THREADS {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {256} \ + CONFIG.NUM_WRITE_THREADS {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $eth_rx_dma +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + set_property CONFIG.PROTOCOL {AXI3} [get_bd_intf_ports eth_rx_dma] + set_property CONFIG.DATA_WIDTH {256} [get_bd_intf_ports eth_rx_dma] + set_property CONFIG.MAX_BURST_LENGTH {16} [get_bd_intf_ports eth_rx_dma] +} + + set eth_rx_dma_clk [ create_bd_port -dir I -type clk eth_rx_dma_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {eth_rx_dma} \ + ] $eth_rx_dma_clk + set eth_rx_dma_rstn [ create_bd_port -dir I -type rst eth_rx_dma_rstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $eth_rx_dma_rstn +} + +set PITON_EXTRA_MEMS 0 +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE" && + [info exists ::env(PITON_EXTRA_MEMS)]} { + set PITON_EXTRA_MEMS $::env(PITON_EXTRA_MEMS) +} +for {set idx 0} {$idx < $PITON_EXTRA_MEMS} {incr idx} { + set mcx_axi$idx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 mcx_axi$idx ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH $DRAM_addr_width \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {256} \ + CONFIG.NUM_READ_THREADS {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {256} \ + CONFIG.NUM_WRITE_THREADS {16} \ + CONFIG.PROTOCOL {AXI3} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] [get_bd_intf_ports mcx_axi$idx] +} + +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + set pci2hbm_maxi [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 pci2hbm_maxi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH $DRAM_addr_width \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {250000000} \ + CONFIG.CLK_DOMAIN {meep_shell_qdma_0_0_axi_aclk} \ + CONFIG.HAS_REGION {0} \ + CONFIG.NUM_READ_OUTSTANDING {256} \ + CONFIG.NUM_WRITE_OUTSTANDING {256} \ + CONFIG.PROTOCOL {AXI3} \ + ] $pci2hbm_maxi + + set pci2hbm_saxi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 pci2hbm_saxi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH $DRAM_addr_width \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {250000000} \ + CONFIG.CLK_DOMAIN {meep_shell_qdma_0_0_axi_aclk} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {256} \ + CONFIG.NUM_READ_THREADS {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {256} \ + CONFIG.NUM_WRITE_THREADS {16} \ + CONFIG.PROTOCOL {AXI3} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $pci2hbm_saxi + + set hbm_cattrip [ create_bd_port -dir O -from 0 -to 0 hbm_cattrip ] +} else { + set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ] +} + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $pcie_refclk + + + # Create ports + set mem_calib_complete [ create_bd_port -dir O -from 0 -to 0 -type rst mem_calib_complete ] + set pcie_gpio [ create_bd_port -dir O -from 4 -to 0 pcie_gpio ] + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $pcie_perstn + + set sysck_axi_ports "" + if {[info exists ::env(PROTOSYN_RUNTIME_ETH)] && + $::env(PROTOSYN_RUNTIME_ETH)=="TRUE"} { + if {$sysck_axi_ports != ""} {append sysck_axi_ports ":"} + append sysck_axi_ports "eth_sg_dma" + } + for {set idx 0} {$idx < $PITON_EXTRA_MEMS} {incr idx} { + if {$sysck_axi_ports != ""} {append sysck_axi_ports ":"} + append sysck_axi_ports "mcx_axi" $idx + } + set sys_clk [ create_bd_port -dir I -type clk sys_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF $sysck_axi_ports \ + ] $sys_clk + set sys_rst [ create_bd_port -dir I -type rst sys_rst ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $sys_rst + + set mem_clk [ create_bd_port -dir O -type clk mem_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axi} \ + ] $mem_clk + set mem_rst [ create_bd_port -dir O -type rst mem_rst ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $mem_rst + + +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + # Create instance: hbm_0, and set properties + if {[info exists ::env(PROTOSYN_RUNTIME_BOARD)] && $::env(PROTOSYN_RUNTIME_BOARD)=="alveou280"} { + set hbm_density "8GB" + set hbm_axi_sfx "" + } + if {[info exists ::env(PROTOSYN_RUNTIME_BOARD)] && $::env(PROTOSYN_RUNTIME_BOARD)=="alveou55c"} { + set hbm_density "16GB" + set hbm_axi_sfx "_8HI" + } + set hbm_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:hbm:1.0 hbm_0 ] + set_property -dict [ list \ + CONFIG.USER_APB_EN {false} \ + CONFIG.USER_CLK_SEL_LIST0 {AXI_00_ACLK} \ + CONFIG.USER_CLK_SEL_LIST1 {AXI_16_ACLK} \ + CONFIG.USER_HBM_CP_1 {6} \ + CONFIG.USER_HBM_DENSITY $hbm_density \ + CONFIG.USER_HBM_FBDIV_1 {36} \ + CONFIG.USER_HBM_HEX_CP_RES_1 {0x0000A600} \ + CONFIG.USER_HBM_HEX_FBDIV_CLKOUTDIV_1 {0x00000902} \ + CONFIG.USER_HBM_HEX_LOCK_FB_REF_DLY_1 {0x00001f1f} \ + CONFIG.USER_HBM_LOCK_FB_DLY_1 {31} \ + CONFIG.USER_HBM_LOCK_REF_DLY_1 {31} \ + CONFIG.USER_HBM_RES_1 {10} \ + CONFIG.USER_HBM_STACK {2} \ + CONFIG.USER_MC_ENABLE_00 {TRUE} \ + CONFIG.USER_MC_ENABLE_01 {TRUE} \ + CONFIG.USER_MC_ENABLE_02 {TRUE} \ + CONFIG.USER_MC_ENABLE_03 {TRUE} \ + CONFIG.USER_MC_ENABLE_04 {TRUE} \ + CONFIG.USER_MC_ENABLE_05 {TRUE} \ + CONFIG.USER_MC_ENABLE_06 {TRUE} \ + CONFIG.USER_MC_ENABLE_07 {TRUE} \ + CONFIG.USER_MC_ENABLE_08 {TRUE} \ + CONFIG.USER_MC_ENABLE_09 {TRUE} \ + CONFIG.USER_MC_ENABLE_10 {TRUE} \ + CONFIG.USER_MC_ENABLE_11 {TRUE} \ + CONFIG.USER_MC_ENABLE_12 {TRUE} \ + CONFIG.USER_MC_ENABLE_13 {TRUE} \ + CONFIG.USER_MC_ENABLE_14 {TRUE} \ + CONFIG.USER_MC_ENABLE_15 {TRUE} \ + CONFIG.USER_MC_ENABLE_APB_01 {TRUE} \ + CONFIG.USER_PHY_ENABLE_08 {TRUE} \ + CONFIG.USER_PHY_ENABLE_09 {TRUE} \ + CONFIG.USER_PHY_ENABLE_10 {TRUE} \ + CONFIG.USER_PHY_ENABLE_11 {TRUE} \ + CONFIG.USER_PHY_ENABLE_12 {TRUE} \ + CONFIG.USER_PHY_ENABLE_13 {TRUE} \ + CONFIG.USER_PHY_ENABLE_14 {TRUE} \ + CONFIG.USER_PHY_ENABLE_15 {TRUE} \ + CONFIG.USER_SAXI_00 {true} \ + CONFIG.USER_SAXI_01 {true} \ + CONFIG.USER_SAXI_02 {false} \ + CONFIG.USER_SAXI_03 {false} \ + CONFIG.USER_SAXI_04 {false} \ + CONFIG.USER_SAXI_05 {false} \ + CONFIG.USER_SAXI_06 {false} \ + CONFIG.USER_SAXI_07 {false} \ + CONFIG.USER_SAXI_08 {false} \ + CONFIG.USER_SAXI_09 {false} \ + CONFIG.USER_SAXI_10 {false} \ + CONFIG.USER_SAXI_11 {false} \ + CONFIG.USER_SAXI_12 {false} \ + CONFIG.USER_SAXI_13 {false} \ + CONFIG.USER_SAXI_14 {false} \ + CONFIG.USER_SAXI_15 {false} \ + CONFIG.USER_SAXI_16 {false} \ + CONFIG.USER_SAXI_17 {false} \ + CONFIG.USER_SAXI_18 {false} \ + CONFIG.USER_SAXI_19 {false} \ + CONFIG.USER_SAXI_20 {false} \ + CONFIG.USER_SAXI_21 {false} \ + CONFIG.USER_SAXI_22 {false} \ + CONFIG.USER_SAXI_23 {false} \ + CONFIG.USER_SAXI_24 {false} \ + CONFIG.USER_SAXI_25 {false} \ + CONFIG.USER_SAXI_26 {false} \ + CONFIG.USER_SAXI_27 {false} \ + CONFIG.USER_SAXI_28 {false} \ + CONFIG.USER_SAXI_29 {false} \ + CONFIG.USER_SAXI_30 {false} \ + CONFIG.USER_SAXI_31 {false} \ + CONFIG.USER_SWITCH_ENABLE_01 {TRUE} \ + ] $hbm_0 + + # Extending setting for PCIe channel + set_property -dict [ list \ + CONFIG.NUM_READ_THREADS {16} \ + CONFIG.NUM_WRITE_THREADS {16} \ + ] [get_bd_intf_pins /hbm_0/SAXI_01$hbm_axi_sfx] + + if {[info exists ::env(PROTOSYN_RUNTIME_ETH)] && + $::env(PROTOSYN_RUNTIME_ETH)=="TRUE"} { + set_property CONFIG.USER_SAXI_29 {true} [get_bd_cells hbm_0] + set_property CONFIG.USER_SAXI_30 {true} [get_bd_cells hbm_0] + set_property CONFIG.USER_SAXI_31 {true} [get_bd_cells hbm_0] + } + + # A function distributing extra HBM channels + # here linearly + set distHBMchan {3 + $idx} + # here evenly around center channel of the switch + # set distHBMchan {16 + ($idx%2 ? $idx/2+1 : -$idx/2-1)} + for {set idx 0} {$idx < $PITON_EXTRA_MEMS} {incr idx} { + set_property CONFIG.USER_SAXI_[format {%02d} [expr $distHBMchan]] {true} [get_bd_cells hbm_0] + } + + # Create instance: mem_refclk_buf, and set properties + set mem_refclk_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 mem_refclk_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDS} \ + ] $mem_refclk_buf + + # Create instance: hbm_cattrip_comb, and set properties + set hbm_cattrip_comb [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 hbm_cattrip_comb ] + set_property -dict [ list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + CONFIG.LOGO_FILE {data/sym_orgate.png} \ + ] $hbm_cattrip_comb + +} else { + + # Create instance: ddr4_0, and set properties + if {[info exists ::env(PROTOSYN_RUNTIME_BOARD)] && $::env(PROTOSYN_RUNTIME_BOARD)=="alveou280"} { + set DDR4_InClk "9996" + } + if {[info exists ::env(PROTOSYN_RUNTIME_BOARD)] && $::env(PROTOSYN_RUNTIME_BOARD)=="alveou250"} { + set DDR4_InClk "3332" + } + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_AxiAddressWidth $DRAM_addr_width \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_CLKFBOUT_MULT {15} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_DataMask {NONE} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_Ecc {true} \ + CONFIG.C0.DDR4_InputClockPeriod $DDR4_InClk \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {Custom} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + ] $ddr4_0 + + # Create instance: gndx1, and set properties + set gndx1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gndx1 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $gndx1 +} + + # Create instance: gndx32, and set properties + set gndx32 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gndx32 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {32} \ + ] $gndx32 + + # Create instance: rst_inv, and set properties + set rst_inv [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rst_inv ] + set_property -dict [ list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + CONFIG.LOGO_FILE {data/sym_notgate.png} \ + ] $rst_inv + + # Create instance: mem_calib_sync, and set properties + set mem_calib_sync [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 mem_calib_sync ] + set_property -dict [ list \ + CONFIG.C_AUX_RESET_HIGH {0} \ + ] $mem_calib_sync + + # Create instance: pcie_refclk_buf, and set properties + set pcie_refclk_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 pcie_refclk_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDSGTE} \ + ] $pcie_refclk_buf + + # Create instance: qdma_0, and set properties + if {[info exists ::env(PROTOSYN_RUNTIME_BOARD)] && + $::env(PROTOSYN_RUNTIME_BOARD)=="alveou250"} { + set pcie_blk_locn "X0Y1" + } else { + set pcie_blk_locn "PCIE4C_X1Y0" + } + set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:5.0 qdma_0 ] + set_property -dict [ list \ + CONFIG.MAILBOX_ENABLE {true} \ + CONFIG.PF0_SRIOV_CAP_INITIAL_VF {4} \ + CONFIG.PF1_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF1_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.PF2_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF2_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.PF3_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF3_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.SRIOV_CAP_ENABLE {true} \ + CONFIG.SRIOV_FIRST_VF_OFFSET {4} \ + CONFIG.barlite_mb_pf0 {1} \ + CONFIG.barlite_mb_pf1 {0} \ + CONFIG.barlite_mb_pf2 {0} \ + CONFIG.barlite_mb_pf3 {0} \ + CONFIG.dma_intf_sel_qdma {AXI_MM} \ + CONFIG.en_axi_st_qdma {false} \ + CONFIG.flr_enable {true} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.pcie_blk_locn $pcie_blk_locn \ + CONFIG.pf0_ari_enabled {true} \ + CONFIG.pf0_bar0_prefetchable_qdma {true} \ + CONFIG.pf0_bar2_prefetchable_qdma {true} \ + CONFIG.pf1_bar0_prefetchable_qdma {true} \ + CONFIG.pf1_bar2_prefetchable_qdma {true} \ + CONFIG.pf1_msix_enabled_qdma {false} \ + CONFIG.pf2_bar0_prefetchable_qdma {true} \ + CONFIG.pf2_bar2_prefetchable_qdma {true} \ + CONFIG.pf2_msix_enabled_qdma {false} \ + CONFIG.pf3_bar0_prefetchable_qdma {true} \ + CONFIG.pf3_bar2_prefetchable_qdma {true} \ + CONFIG.pf3_msix_enabled_qdma {false} \ + CONFIG.pl_link_cap_max_link_speed {8.0_GT/s} \ + CONFIG.pl_link_cap_max_link_width {X16} \ + CONFIG.testname {mm} \ + CONFIG.tl_pf_enable_reg {1} \ + ] $qdma_0 +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + set_property CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} [get_bd_cells qdma_0] +} + + # Create instance: vccx1, and set properties + set vccx1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vccx1 ] + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {5} \ + ] $axi_gpio_0 + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {2} \ + CONFIG.NUM_MI {1} \ + ] $smartconnect_0 +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + set_property CONFIG.NUM_SI {1} [get_bd_cells smartconnect_0] + set_property CONFIG.NUM_CLKS {1} [get_bd_cells smartconnect_0] +} else { + if {[info exists ::env(PROTOSYN_RUNTIME_ETH)] && + $::env(PROTOSYN_RUNTIME_ETH)=="TRUE"} { + set_property CONFIG.NUM_SI {5} [get_bd_cells smartconnect_0] + set_property CONFIG.NUM_CLKS {5} [get_bd_cells smartconnect_0] + connect_bd_intf_net [get_bd_intf_ports eth_sg_dma] [get_bd_intf_pins smartconnect_0/S02_AXI] + connect_bd_intf_net [get_bd_intf_ports eth_tx_dma] [get_bd_intf_pins smartconnect_0/S03_AXI] + connect_bd_intf_net [get_bd_intf_ports eth_rx_dma] [get_bd_intf_pins smartconnect_0/S04_AXI] + connect_bd_net [get_bd_ports sys_clk] [get_bd_pins smartconnect_0/aclk2] + connect_bd_net [get_bd_ports eth_tx_dma_clk] [get_bd_pins smartconnect_0/aclk3] + connect_bd_net [get_bd_ports eth_rx_dma_clk] [get_bd_pins smartconnect_0/aclk4] + } +} + + # Create interface connections + connect_bd_intf_net [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins pcie_refclk_buf/CLK_IN_D] + connect_bd_intf_net [get_bd_intf_pins qdma_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net [get_bd_intf_pins qdma_0/M_AXI_LITE] [get_bd_intf_pins axi_gpio_0/S_AXI] + connect_bd_intf_net [get_bd_intf_pins qdma_0/pcie_mgt] [get_bd_intf_ports pci_express_x16] + +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + connect_bd_intf_net [get_bd_intf_ports mem_refclk] [get_bd_intf_pins mem_refclk_buf/CLK_IN_D] + connect_bd_intf_net [get_bd_intf_ports m_axi] [get_bd_intf_pins hbm_0/SAXI_00$hbm_axi_sfx] + connect_bd_intf_net [get_bd_intf_ports pci2hbm_saxi] [get_bd_intf_pins hbm_0/SAXI_01$hbm_axi_sfx] + connect_bd_intf_net [get_bd_intf_ports pci2hbm_maxi] [get_bd_intf_pins smartconnect_0/M00_AXI] + for {set idx 0} {$idx < $PITON_EXTRA_MEMS} {incr idx} { + connect_bd_intf_net [get_bd_intf_ports mcx_axi$idx] [get_bd_intf_pins hbm_0/SAXI_[format {%02d} [expr $distHBMchan]]$hbm_axi_sfx] + } + if {[info exists ::env(PROTOSYN_RUNTIME_ETH)] && + $::env(PROTOSYN_RUNTIME_ETH)=="TRUE"} { + connect_bd_intf_net [get_bd_intf_ports eth_sg_dma] [get_bd_intf_pins hbm_0/SAXI_29$hbm_axi_sfx] + connect_bd_intf_net [get_bd_intf_ports eth_tx_dma] [get_bd_intf_pins hbm_0/SAXI_30$hbm_axi_sfx] + connect_bd_intf_net [get_bd_intf_ports eth_rx_dma] [get_bd_intf_pins hbm_0/SAXI_31$hbm_axi_sfx] + } +} else { + connect_bd_intf_net [get_bd_intf_ports mem_refclk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net [get_bd_intf_ports m_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] + connect_bd_intf_net [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] +} + + # Create port connections + connect_bd_net [get_bd_ports pcie_perstn] [get_bd_pins qdma_0/soft_reset_n] [get_bd_pins qdma_0/sys_rst_n] + connect_bd_net [get_bd_pins qdma_0/sys_clk] [get_bd_pins pcie_refclk_buf/IBUF_DS_ODIV2] + connect_bd_net [get_bd_pins qdma_0/sys_clk_gt] [get_bd_pins pcie_refclk_buf/IBUF_OUT] + connect_bd_net [get_bd_pins qdma_0/qsts_out_rdy] [get_bd_pins qdma_0/tm_dsc_sts_rdy] [get_bd_pins vccx1/dout] + connect_bd_net [get_bd_pins qdma_0/axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] + connect_bd_net [get_bd_pins qdma_0/axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] + connect_bd_net [get_bd_ports pcie_gpio] [get_bd_pins axi_gpio_0/gpio_io_o] + connect_bd_net [get_bd_pins mem_calib_sync/slowest_sync_clk] [get_bd_ports mem_clk] + connect_bd_net [get_bd_pins mem_calib_sync/mb_debug_sys_rst] [get_bd_pins rst_inv/Op1] + connect_bd_net [get_bd_pins mem_calib_sync/dcm_locked] [get_bd_pins rst_inv/Res] + connect_bd_net [get_bd_pins mem_calib_sync/peripheral_aresetn] [get_bd_ports mem_calib_complete] + +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + connect_bd_net [get_bd_pins mem_refclk_buf/IBUF_OUT] [get_bd_pins hbm_0/HBM_REF_CLK_0] [get_bd_pins hbm_0/HBM_REF_CLK_1] [get_bd_pins hbm_0/APB_0_PCLK] [get_bd_pins hbm_0/APB_1_PCLK] + connect_bd_net [get_bd_pins hbm_0/DRAM_0_STAT_CATTRIP] [get_bd_pins hbm_cattrip_comb/Op1] + connect_bd_net [get_bd_pins hbm_0/DRAM_1_STAT_CATTRIP] [get_bd_pins hbm_cattrip_comb/Op2] + connect_bd_net [get_bd_ports hbm_cattrip] [get_bd_pins hbm_cattrip_comb/Res] + connect_bd_net [get_bd_pins hbm_0/apb_complete_0] [get_bd_pins mem_calib_sync/ext_reset_in] + connect_bd_net [get_bd_pins hbm_0/apb_complete_1] [get_bd_pins mem_calib_sync/aux_reset_in] + connect_bd_net [get_bd_pins qdma_0/axi_aclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins hbm_0/AXI_01_ACLK] + connect_bd_net [get_bd_pins qdma_0/axi_aresetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins hbm_0/AXI_01_ARESET_N] + connect_bd_net [get_bd_pins gndx32/dout] [get_bd_pins hbm_0/AXI_00_WDATA_PARITY] [get_bd_pins hbm_0/AXI_01_WDATA_PARITY] + connect_bd_net [get_bd_ports sys_clk] [get_bd_ports mem_clk] [get_bd_pins hbm_0/AXI_00_ACLK] + connect_bd_net [get_bd_ports sys_rst] [get_bd_ports mem_rst] [get_bd_pins rst_inv/Op1] + connect_bd_net [get_bd_pins rst_inv/Res] [get_bd_pins hbm_0/APB_0_PRESET_N] [get_bd_pins hbm_0/APB_1_PRESET_N] [get_bd_pins hbm_0/AXI_00_ARESET_N] + for {set idx 0} {$idx < $PITON_EXTRA_MEMS} {incr idx} { + set hbm_port [format {%02d} [expr $distHBMchan]] + connect_bd_net [get_bd_pins gndx32/dout] [get_bd_pins hbm_0/AXI_${hbm_port}_WDATA_PARITY] + connect_bd_net [get_bd_ports sys_clk] [get_bd_pins hbm_0/AXI_${hbm_port}_ACLK] + connect_bd_net [get_bd_pins rst_inv/Res] [get_bd_pins hbm_0/AXI_${hbm_port}_ARESET_N] + } + # After all connections set PCIe clock to drive HBM cross-switch-0 + set_property CONFIG.USER_CLK_SEL_LIST0 AXI_01_ACLK [get_bd_cells hbm_0] + if {[info exists ::env(PROTOSYN_RUNTIME_ETH)] && + $::env(PROTOSYN_RUNTIME_ETH)=="TRUE"} { + connect_bd_net [get_bd_pins gndx32/dout] [get_bd_pins hbm_0/AXI_29_WDATA_PARITY] + connect_bd_net [get_bd_pins gndx32/dout] [get_bd_pins hbm_0/AXI_30_WDATA_PARITY] + connect_bd_net [get_bd_pins gndx32/dout] [get_bd_pins hbm_0/AXI_31_WDATA_PARITY] + connect_bd_net [get_bd_ports sys_clk] [get_bd_pins hbm_0/AXI_29_ACLK] + connect_bd_net [get_bd_ports eth_tx_dma_clk] [get_bd_pins hbm_0/AXI_30_ACLK] + connect_bd_net [get_bd_ports eth_rx_dma_clk] [get_bd_pins hbm_0/AXI_31_ACLK] + connect_bd_net [get_bd_pins rst_inv/Res] [get_bd_pins hbm_0/AXI_29_ARESET_N] + connect_bd_net [get_bd_ports eth_tx_dma_rstn] [get_bd_pins hbm_0/AXI_30_ARESET_N] + connect_bd_net [get_bd_ports eth_rx_dma_rstn] [get_bd_pins hbm_0/AXI_31_ARESET_N] + # set Eth Tx clock to drive HBM cross-switch-1 + set_property CONFIG.USER_CLK_SEL_LIST1 AXI_30_ACLK [get_bd_cells hbm_0] + } +} else { + connect_bd_net [get_bd_pins gndx32/dout] [get_bd_pins ddr4_0/c0_ddr4_s_axi_ctrl_araddr] [get_bd_pins ddr4_0/c0_ddr4_s_axi_ctrl_awaddr] [get_bd_pins ddr4_0/c0_ddr4_s_axi_ctrl_wdata] + connect_bd_net [get_bd_pins gndx1/dout] [get_bd_pins ddr4_0/c0_ddr4_s_axi_ctrl_arvalid] [get_bd_pins ddr4_0/c0_ddr4_s_axi_ctrl_awvalid] [get_bd_pins ddr4_0/c0_ddr4_s_axi_ctrl_bready] [get_bd_pins ddr4_0/c0_ddr4_s_axi_ctrl_rready] [get_bd_pins ddr4_0/c0_ddr4_s_axi_ctrl_wvalid] + connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_ports mem_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] [get_bd_ports mem_rst] [get_bd_pins rst_inv/Op1] + connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins rst_inv/Res] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net [get_bd_pins ddr4_0/c0_init_calib_complete] [get_bd_pins mem_calib_sync/ext_reset_in] [get_bd_pins mem_calib_sync/aux_reset_in] + connect_bd_net [get_bd_pins qdma_0/axi_aclk] [get_bd_pins smartconnect_0/aclk1] + connect_bd_net [get_bd_ports sys_rst] [get_bd_pins ddr4_0/sys_rst] +} + + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI_LITE] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force +if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + set hbm_mems 32 + set hbm_range [expr ((1 << $DRAM_addr_width)/$hbm_mems)] + assign_bd_address -offset 0x0 -range [expr ($hbm_mems * $hbm_range)] -target_address_space [get_bd_addr_spaces qdma_0/M_AXI] [get_bd_addr_segs pci2hbm_maxi/Reg] -force + for {set hbm_mem 0} {$hbm_mem < $hbm_mems} {incr hbm_mem} { + assign_bd_address -offset [expr ($hbm_mem * $hbm_range)] -range $hbm_range -target_address_space [get_bd_addr_spaces m_axi] [get_bd_addr_segs hbm_0/SAXI_00$hbm_axi_sfx/HBM_MEM[format {%02d} $hbm_mem]] -force + assign_bd_address -offset [expr ($hbm_mem * $hbm_range)] -range $hbm_range -target_address_space [get_bd_addr_spaces pci2hbm_saxi] [get_bd_addr_segs hbm_0/SAXI_01$hbm_axi_sfx/HBM_MEM[format {%02d} $hbm_mem]] -force + for {set idx 0} {$idx < $PITON_EXTRA_MEMS} {incr idx} { + set hbm_port [format {%02d} [expr $distHBMchan]] + assign_bd_address -offset [expr ($hbm_mem * $hbm_range)] -range $hbm_range -target_address_space [get_bd_addr_spaces mcx_axi$idx] [get_bd_addr_segs hbm_0/SAXI_$hbm_port$hbm_axi_sfx/HBM_MEM[format {%02d} $hbm_mem]] -force + } + if {[info exists ::env(PROTOSYN_RUNTIME_ETH)] && + $::env(PROTOSYN_RUNTIME_ETH)=="TRUE"} { + assign_bd_address -offset [expr ($hbm_mem * $hbm_range)] -range $hbm_range -target_address_space [get_bd_addr_spaces eth_sg_dma] [get_bd_addr_segs hbm_0/SAXI_29$hbm_axi_sfx/HBM_MEM[format {%02d} $hbm_mem]] -force + assign_bd_address -offset [expr ($hbm_mem * $hbm_range)] -range $hbm_range -target_address_space [get_bd_addr_spaces eth_tx_dma] [get_bd_addr_segs hbm_0/SAXI_30$hbm_axi_sfx/HBM_MEM[format {%02d} $hbm_mem]] -force + assign_bd_address -offset [expr ($hbm_mem * $hbm_range)] -range $hbm_range -target_address_space [get_bd_addr_spaces eth_rx_dma] [get_bd_addr_segs hbm_0/SAXI_31$hbm_axi_sfx/HBM_MEM[format {%02d} $hbm_mem]] -force + } + } +} else { + set ddr_range [expr (1 << $DRAM_addr_width)] + assign_bd_address -offset 0x00000000 -range $ddr_range -target_address_space [get_bd_addr_spaces qdma_0/M_AXI] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x00000000 -range $ddr_range -target_address_space [get_bd_addr_spaces m_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + if {[info exists ::env(PROTOSYN_RUNTIME_ETH)] && + $::env(PROTOSYN_RUNTIME_ETH)=="TRUE"} { + assign_bd_address -offset 0x00000000 -range $ddr_range -target_address_space [get_bd_addr_spaces eth_sg_dma] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x00000000 -range $ddr_range -target_address_space [get_bd_addr_spaces eth_tx_dma] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x00000000 -range $ddr_range -target_address_space [get_bd_addr_spaces eth_rx_dma] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + } +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_meep_shell() + +cr_bd_meep_shell "" diff --git a/piton/design/chipset/noc_axi4_bridge/noc_ax4_bridge_ila.xdc b/piton/design/chipset/noc_axi4_bridge/noc_ax4_bridge_ila.xdc new file mode 100644 index 000000000..5ecd6fba2 --- /dev/null +++ b/piton/design/chipset/noc_axi4_bridge/noc_ax4_bridge_ila.xdc @@ -0,0 +1,463 @@ +# ------------------------------------------------------------------------ +# The current probe widths are for noc_axi4_bridge case of RDWR_INORDER = 1 and +# (NUM_REQ_MSHRID_BITS=2 or NUM_REQ_YTHREADS x NUM_REQ_XTHREADS = 2x2). +# Commented width is for default noc_axi4_bridge parameters NUM_REQ_MSHRID_BITS/NUM_REQ_YTHREADS/NUM_REQ_XTHREADS +# +# Debug property should be added accordingly to Verilog sources for each of probed below signals: +# (* keep="TRUE" *) (* mark_debug="TRUE" *) input deser_val, +# + +create_debug_core u_ila_0 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property port_width 1 [get_debug_ports u_ila_0/clk] +connect_debug_port u_ila_0/clk [get_nets [list chipset/clk_mmcm/inst/chipset_clk]] + +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +set_property port_width 1 [get_debug_ports u_ila_0/probe0] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +set_property port_width 1 [get_debug_ports u_ila_0/probe1] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +set_property port_width 1 [get_debug_ports u_ila_0/probe2] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +set_property port_width 1 [get_debug_ports u_ila_0/probe3] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +set_property port_width 1 [get_debug_ports u_ila_0/probe4] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +set_property port_width 1 [get_debug_ports u_ila_0/probe5] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +set_property port_width 1 [get_debug_ports u_ila_0/probe6] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +set_property port_width 1 [get_debug_ports u_ila_0/probe7] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +set_property port_width 1 [get_debug_ports u_ila_0/probe9] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +set_property port_width 1 [get_debug_ports u_ila_0/probe11] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +set_property port_width 6 [get_debug_ports u_ila_0/probe12] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +set_property port_width 1 [get_debug_ports u_ila_0/probe13] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +set_property port_width 6 [get_debug_ports u_ila_0/probe15] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +set_property port_width 6 [get_debug_ports u_ila_0/probe18] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +set_property port_width 1 [get_debug_ports u_ila_0/probe19] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +set_property port_width 1 [get_debug_ports u_ila_0/probe20] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +set_property port_width 6 [get_debug_ports u_ila_0/probe21] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +set_property port_width 1 [get_debug_ports u_ila_0/probe22] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +set_property port_width 1 [get_debug_ports u_ila_0/probe23] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +set_property port_width 1 [get_debug_ports u_ila_0/probe24] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] +set_property port_width 1 [get_debug_ports u_ila_0/probe25] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] +set_property port_width 1 [get_debug_ports u_ila_0/probe26] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] +set_property port_width 1 [get_debug_ports u_ila_0/probe27] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] +set_property port_width 1 [get_debug_ports u_ila_0/probe28] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] +set_property port_width 1 [get_debug_ports u_ila_0/probe29] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] +set_property port_width 1 [get_debug_ports u_ila_0/probe30] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] +set_property port_width 1 [get_debug_ports u_ila_0/probe31] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] +set_property port_width 1 [get_debug_ports u_ila_0/probe32] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] +set_property port_width 8 [get_debug_ports u_ila_0/probe33] +# set_property port_width 2 [get_debug_ports u_ila_0/probe33] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] +set_property port_width 8 [get_debug_ports u_ila_0/probe34] +# set_property port_width 2 [get_debug_ports u_ila_0/probe34] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] +set_property port_width 3 [get_debug_ports u_ila_0/probe35] +# set_property port_width 1 [get_debug_ports u_ila_0/probe35] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] +set_property port_width 3 [get_debug_ports u_ila_0/probe36] +# set_property port_width 1 [get_debug_ports u_ila_0/probe36] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] +set_property port_width 3 [get_debug_ports u_ila_0/probe37] +# set_property port_width 1 [get_debug_ports u_ila_0/probe37] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] +set_property port_width 4 [get_debug_ports u_ila_0/probe38] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] +set_property port_width 4 [get_debug_ports u_ila_0/probe39] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] +set_property port_width 4 [get_debug_ports u_ila_0/probe40] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] +set_property port_width 4 [get_debug_ports u_ila_0/probe41] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] +set_property port_width 4 [get_debug_ports u_ila_0/probe42] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] +set_property port_width 4 [get_debug_ports u_ila_0/probe43] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] +set_property port_width 202 [get_debug_ports u_ila_0/probe44] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] +set_property port_width 202 [get_debug_ports u_ila_0/probe45] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] +set_property port_width 1 [get_debug_ports u_ila_0/probe46] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47] +set_property port_width 1 [get_debug_ports u_ila_0/probe47] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48] +set_property port_width 1 [get_debug_ports u_ila_0/probe48] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49] +set_property port_width 1 [get_debug_ports u_ila_0/probe49] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50] +set_property port_width 1 [get_debug_ports u_ila_0/probe50] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51] +set_property port_width 1 [get_debug_ports u_ila_0/probe51] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52] +set_property port_width 1 [get_debug_ports u_ila_0/probe52] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53] +set_property port_width 1 [get_debug_ports u_ila_0/probe53] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] +set_property port_width 1 [get_debug_ports u_ila_0/probe54] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55] +set_property port_width 6 [get_debug_ports u_ila_0/probe55] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56] +set_property port_width 7 [get_debug_ports u_ila_0/probe56] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57] +set_property port_width 6 [get_debug_ports u_ila_0/probe57] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58] +set_property port_width 7 [get_debug_ports u_ila_0/probe58] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59] +set_property port_width 8 [get_debug_ports u_ila_0/probe59] +# set_property port_width 2 [get_debug_ports u_ila_0/probe59] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60] +set_property port_width 1 [get_debug_ports u_ila_0/probe60] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61] +set_property port_width 1 [get_debug_ports u_ila_0/probe61] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62] +set_property port_width 1 [get_debug_ports u_ila_0/probe62] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63] +set_property port_width 1 [get_debug_ports u_ila_0/probe63] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64] +set_property port_width 1 [get_debug_ports u_ila_0/probe64] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65] +set_property port_width 1 [get_debug_ports u_ila_0/probe65] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66] +set_property port_width 64 [get_debug_ports u_ila_0/probe66] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67] +set_property port_width 64 [get_debug_ports u_ila_0/probe67] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68] +set_property port_width 64 [get_debug_ports u_ila_0/probe68] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69] +set_property port_width 64 [get_debug_ports u_ila_0/probe69] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70] +set_property port_width 64 [get_debug_ports u_ila_0/probe70] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71] +set_property port_width 64 [get_debug_ports u_ila_0/probe71] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72] +set_property port_width 6 [get_debug_ports u_ila_0/probe72] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73] +set_property port_width 6 [get_debug_ports u_ila_0/probe73] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74] +set_property port_width 6 [get_debug_ports u_ila_0/probe74] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75] +set_property port_width 6 [get_debug_ports u_ila_0/probe75] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76] +set_property port_width 6 [get_debug_ports u_ila_0/probe76] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77] +set_property port_width 256 [get_debug_ports u_ila_0/probe77] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78] +set_property port_width 512 [get_debug_ports u_ila_0/probe78] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79] +set_property port_width 512 [get_debug_ports u_ila_0/probe79] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80] +set_property port_width 512 [get_debug_ports u_ila_0/probe80] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81] +set_property port_width 8 [get_debug_ports u_ila_0/probe81] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82] +set_property port_width 6 [get_debug_ports u_ila_0/probe82] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83] +set_property port_width 10 [get_debug_ports u_ila_0/probe83] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84] +set_property port_width 8 [get_debug_ports u_ila_0/probe84] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85] +set_property port_width 8 [get_debug_ports u_ila_0/probe85] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86] +set_property port_width 8 [get_debug_ports u_ila_0/probe86] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87] +set_property port_width 8 [get_debug_ports u_ila_0/probe87] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88] +set_property port_width 8 [get_debug_ports u_ila_0/probe88] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89] +set_property port_width 8 [get_debug_ports u_ila_0/probe89] + +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90] +set_property port_width 5 [get_debug_ports u_ila_0/probe90] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91] +set_property port_width 5 [get_debug_ports u_ila_0/probe91] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92] +set_property port_width 5 [get_debug_ports u_ila_0/probe92] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93] +set_property port_width 5 [get_debug_ports u_ila_0/probe93] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94] +set_property port_width 5 [get_debug_ports u_ila_0/probe94] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95] +set_property port_width 5 [get_debug_ports u_ila_0/probe95] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96] +set_property port_width 1 [get_debug_ports u_ila_0/probe96] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97] +set_property port_width 1 [get_debug_ports u_ila_0/probe97] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98] +set_property port_width 5 [get_debug_ports u_ila_0/probe98] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99] +set_property port_width 5 [get_debug_ports u_ila_0/probe99] + + +connect_debug_port u_ila_0/probe0 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_read/m_axi_arvalid +connect_debug_port u_ila_0/probe1 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_read/m_axi_arready +connect_debug_port u_ila_0/probe2 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_read/m_axi_rvalid +connect_debug_port u_ila_0/probe3 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_read/m_axi_rready +connect_debug_port u_ila_0/probe64 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_read/m_axi_rlast + +connect_debug_port u_ila_0/probe66 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_read/m_axi_araddr +connect_debug_port u_ila_0/probe72 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_read/m_axi_arid +connect_debug_port u_ila_0/probe73 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_read/m_axi_rid +connect_debug_port u_ila_0/probe77 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_read/m_axi_rdata +connect_debug_port u_ila_0/probe78 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_read/resp_data + + +connect_debug_port u_ila_0/probe4 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_awvalid +connect_debug_port u_ila_0/probe5 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_awready +connect_debug_port u_ila_0/probe6 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_wvalid +connect_debug_port u_ila_0/probe7 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_wready +connect_debug_port u_ila_0/probe8 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_bvalid +connect_debug_port u_ila_0/probe9 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_bready +connect_debug_port u_ila_0/probe65 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_wlast + +connect_debug_port u_ila_0/probe67 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_awaddr +connect_debug_port u_ila_0/probe68 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_wstrb +connect_debug_port u_ila_0/probe74 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_awid +connect_debug_port u_ila_0/probe75 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_wid +connect_debug_port u_ila_0/probe76 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_bid +connect_debug_port u_ila_0/probe79 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/m_axi_wdata +connect_debug_port u_ila_0/probe80 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_write/req_data + +connect_debug_port u_ila_0/probe81 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/mshrid +connect_debug_port u_ila_0/probe82 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/lsid +connect_debug_port u_ila_0/probe83 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/sdid + +connect_debug_port u_ila_0/probe84 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/src_x +connect_debug_port u_ila_0/probe85 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/src_y +connect_debug_port u_ila_0/probe86 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/dst_x +connect_debug_port u_ila_0/probe87 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/dst_y +connect_debug_port u_ila_0/probe88 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/ini_x +connect_debug_port u_ila_0/probe89 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/ini_y + +connect_debug_port u_ila_0/probe69 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/read_req_addr +connect_debug_port u_ila_0/probe70 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/write_req_addr +connect_debug_port u_ila_0/probe71 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/write_req_strb + +connect_debug_port u_ila_0/probe10 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/deser_val +connect_debug_port u_ila_0/probe11 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/deser_rdy +connect_debug_port u_ila_0/probe12 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/read_req_id +connect_debug_port u_ila_0/probe13 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/read_req_val +connect_debug_port u_ila_0/probe14 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/read_req_rdy +connect_debug_port u_ila_0/probe15 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/read_resp_id +connect_debug_port u_ila_0/probe16 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/read_resp_val +connect_debug_port u_ila_0/probe17 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/read_resp_rdy +connect_debug_port u_ila_0/probe18 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/write_req_id +connect_debug_port u_ila_0/probe19 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/write_req_val +connect_debug_port u_ila_0/probe20 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/write_req_rdy +connect_debug_port u_ila_0/probe21 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/write_resp_id +connect_debug_port u_ila_0/probe22 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/write_resp_val +connect_debug_port u_ila_0/probe23 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/write_resp_rdy +connect_debug_port u_ila_0/probe24 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/ser_val +connect_debug_port u_ila_0/probe25 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/ser_rdy +connect_debug_port u_ila_0/probe26 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/fifo_in +connect_debug_port u_ila_0/probe27 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/fifo_out + +connect_debug_port u_ila_0/probe28 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/deser_go +connect_debug_port u_ila_0/probe29 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/read_req_go +connect_debug_port u_ila_0/probe30 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/write_req_go +connect_debug_port u_ila_0/probe31 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/req_go +connect_debug_port u_ila_0/probe32 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/ser_go + +connect_debug_port u_ila_0/probe33 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_vrt_empts +connect_debug_port u_ila_0/probe34 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_abs_rdptrs_val +connect_debug_port u_ila_0/probe35 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/full_resp_id +connect_debug_port u_ila_0/probe36 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/full_req_id +connect_debug_port u_ila_0/probe37 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/full_stor_id +connect_debug_port u_ila_0/probe38 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_abs_rdptr +connect_debug_port u_ila_0/probe39 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_abs_wrptr +connect_debug_port u_ila_0/probe40 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_abs_wrptr_mem +connect_debug_port u_ila_0/probe41 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_vrt_rdptr +connect_debug_port u_ila_0/probe42 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_abs_rdptr_mem +connect_debug_port u_ila_0/probe43 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_vrt_wrptr +connect_debug_port u_ila_0/probe44 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/clean_header +connect_debug_port u_ila_0/probe45 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/stor_header +connect_debug_port u_ila_0/probe46 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/init_outstnd_mem +connect_debug_port u_ila_0/probe47 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_abs_rdptr_val +connect_debug_port u_ila_0/probe48 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_vrt_empt +connect_debug_port u_ila_0/probe49 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_vrt_rdptr_val +connect_debug_port u_ila_0/probe50 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/req_occup +connect_debug_port u_ila_0/probe51 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/resp_val +connect_debug_port u_ila_0/probe52 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_abs_rdptr_val_act +connect_debug_port u_ila_0/probe53 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/stor_hdr_val +connect_debug_port u_ila_0/probe54 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/stor_hdr_en +connect_debug_port u_ila_0/probe55 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/rd_offset +connect_debug_port u_ila_0/probe56 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/rd_size +connect_debug_port u_ila_0/probe57 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/wr_offset +connect_debug_port u_ila_0/probe58 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/wr_size + +connect_debug_port u_ila_0/probe59 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_command +connect_debug_port u_ila_0/probe60 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/read_resp_val_act +connect_debug_port u_ila_0/probe61 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/write_resp_val_act +connect_debug_port u_ila_0/probe62 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/req_val +connect_debug_port u_ila_0/probe63 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/axi_id_deadlock + +connect_debug_port u_ila_0/probe90 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_wrreq_cnt +connect_debug_port u_ila_0/probe91 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_rdreq_cnt +connect_debug_port u_ila_0/probe92 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_req_cnt +connect_debug_port u_ila_0/probe93 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_wrrsp_cnt +connect_debug_port u_ila_0/probe94 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_rdrsp_cnt +connect_debug_port u_ila_0/probe95 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/outstnd_rsp_cnt +connect_debug_port u_ila_0/probe96 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/dbg_wr_reorder +connect_debug_port u_ila_0/probe97 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/dbg_rd_reorder +connect_debug_port u_ila_0/probe98 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/rd_reorder_cnt +connect_debug_port u_ila_0/probe99 chipset/chipset_impl/mc_top/noc_axi4_bridge/noc_axi4_bridge_buffer/wr_reorder_cnt + +set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +connect_debug_port dbg_hub/clk [get_nets clk] diff --git a/piton/design/chipset/noc_axi4_bridge/noc_axi4+id_buffer.png b/piton/design/chipset/noc_axi4_bridge/noc_axi4+id_buffer.png new file mode 100644 index 000000000..e9d0395ed Binary files /dev/null and b/piton/design/chipset/noc_axi4_bridge/noc_axi4+id_buffer.png differ diff --git a/piton/design/chipset/noc_axi4_bridge/rtl/Flist.noc_axi4_bridge b/piton/design/chipset/noc_axi4_bridge/rtl/Flist.noc_axi4_bridge index ab6703a03..946968a42 100644 --- a/piton/design/chipset/noc_axi4_bridge/rtl/Flist.noc_axi4_bridge +++ b/piton/design/chipset/noc_axi4_bridge/rtl/Flist.noc_axi4_bridge @@ -1,4 +1,5 @@ -9// ========== Copyright Header Begin ============================================ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 +// ========== Copyright Header Begin ============================================ // Copyright (c) 2019 Princeton University // All rights reserved. // @@ -26,9 +27,11 @@ // ========== Copyright Header End ============================================ noc_axi4_bridge.v -noc_axi4_bridge_buffer.v -noc_axi4_bridge_ser.v -noc_axi4_bridge_deser.v -noc_axi4_bridge_read.v -noc_axi4_bridge_write.v +noc_axi4_bridge_buffer.sv +noc_axi4_bridge_ser.sv +noc_axi4_bridge_deser.sv +noc_axi4_bridge_read.sv +noc_axi4_bridge_write.sv +// noc_axi4_bridge_sram_data.tmp.v +// noc_axi4_bridge_sram_req.tmp.v diff --git a/piton/design/chipset/noc_axi4_bridge/rtl/axi4_zeroer.v b/piton/design/chipset/noc_axi4_bridge/rtl/axi4_zeroer.v index 53aab4f6e..10532fcbb 100644 --- a/piton/design/chipset/noc_axi4_bridge/rtl/axi4_zeroer.v +++ b/piton/design/chipset/noc_axi4_bridge/rtl/axi4_zeroer.v @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // Copyright (c) 2019 Princeton University // All rights reserved. // @@ -30,7 +31,7 @@ module axi4_zeroer ( input rst_n, input init_calib_complete_in, - output init_calib_complete_out, + output reg init_calib_complete_out, // AXI interface in input wire [`AXI4_ID_WIDTH -1:0] s_axi_awid, @@ -140,29 +141,41 @@ localparam reg [`AXI4_ADDR_WIDTH-1:0] MAX_MEM_ADDR = (BOARD_MEM_SIZE_MB * 2 localparam REQUESTS_NEEDED = MAX_MEM_ADDR / `AXI4_STRB_WIDTH; // basically max addr divided by size of one request localparam MAX_OUTSTANDING = 16; -wire zeroer_req_val; -wire zeroer_resp_rdy; -wire req_go; -wire resp_go; +wire zeroer_awval; +wire zeroer_awrdy; +wire zeroer_wval; +wire zeroer_wrdy; +reg req_go; +reg resp_go; reg [`AXI4_ADDR_WIDTH-1:0] req_sent; reg [`AXI4_ADDR_WIDTH-1:0] resp_got; reg [3:0] outstanding; wire [`AXI4_ADDR_WIDTH-1:0] zeroer_addr; wire zeroer_wlast; +wire init_calib_complete_out_i; +wire init_calib_complete_out_r; -assign zeroer_req_val = init_calib_complete_in +assign zeroer_awval = init_calib_complete_in + & ~init_calib_complete_out_i & (req_sent < REQUESTS_NEEDED) & (outstanding != MAX_OUTSTANDING-1) - & m_axi_awready - & m_axi_wready & rst_n; -assign zeroer_resp_rdy = init_calib_complete_in - & (resp_got < REQUESTS_NEEDED) - & rst_n; +assign zeroer_awrdy = m_axi_awready; +assign zeroer_wrdy = m_axi_wready; -assign req_go = zeroer_req_val; -assign resp_go = zeroer_resp_rdy & m_axi_bvalid; +assign zeroer_wval = 1'b1; + +always @(posedge clk) begin + if(~rst_n) begin + req_go <= 0; + resp_go <= 0; + end + else begin + req_go <= zeroer_awval & zeroer_awrdy; + resp_go <= zeroer_wval & zeroer_wrdy; + end +end always @(posedge clk) begin @@ -171,7 +184,7 @@ always @(posedge clk) begin resp_got <= 0; outstanding <= 0; end - else begin + else if (~init_calib_complete_out_i) begin req_sent <= req_sent + req_go; resp_got <= resp_got + resp_go; outstanding <= req_go & resp_go ? outstanding @@ -179,16 +192,16 @@ always @(posedge clk) begin : resp_go ? outstanding - 1 : outstanding; end + init_calib_complete_out <= init_calib_complete_out_i; end -assign init_calib_complete_out = (req_sent == REQUESTS_NEEDED) & +assign init_calib_complete_out_i = (req_sent == REQUESTS_NEEDED) & (resp_got == REQUESTS_NEEDED); assign zeroer_addr = req_sent * `AXI4_STRB_WIDTH; -assign zeroer_wlast = zeroer_req_val; always @(*) begin - if (~init_calib_complete_out) begin + if (~init_calib_complete_out_i) begin m_axi_awid = `AXI4_ID_WIDTH'b0; m_axi_awaddr = zeroer_addr; m_axi_awlen = `AXI4_LEN_WIDTH'b0; @@ -200,14 +213,14 @@ always @(*) begin m_axi_awqos = `AXI4_QOS_WIDTH'b0; m_axi_awregion = `AXI4_REGION_WIDTH'b0; m_axi_awuser = `AXI4_USER_WIDTH'b0; - m_axi_awvalid = zeroer_req_val; + m_axi_awvalid = zeroer_awval; m_axi_wid = `AXI4_ID_WIDTH'b0; m_axi_wdata = {`AXI4_DATA_WIDTH{1'b0}}; m_axi_wstrb = {`AXI4_STRB_WIDTH{1'b1}}; - m_axi_wlast = zeroer_wlast; + m_axi_wlast = 1'b1; m_axi_wuser = `AXI4_USER_WIDTH'b0; - m_axi_wvalid = zeroer_req_val; + m_axi_wvalid = zeroer_wval; m_axi_arid = `AXI4_ID_WIDTH'b0; m_axi_araddr = `AXI4_ADDR_WIDTH'b0; @@ -223,7 +236,7 @@ always @(*) begin m_axi_arvalid = 1'b0; m_axi_rready = 1'b0; - m_axi_bready = zeroer_resp_rdy; + m_axi_bready = 1'b1; s_axi_awready = 1'b0; s_axi_wready = 1'b0; diff --git a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge.v b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge.v index 149067f24..5ff3f65c4 100644 --- a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge.v +++ b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge.v @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // ========== Copyright Header Begin ============================================ // Copyright (c) 2019 Princeton University // All rights reserved. @@ -29,12 +30,29 @@ `include "define.tmp.h" `include "noc_axi4_bridge_define.vh" -module noc_axi4_bridge ( +module noc_axi4_bridge #( + parameter AXI4_DAT_WIDTH_USED = `AXI4_DATA_WIDTH, // actually used AXI Data width (down converted if needed) + parameter SWAP_ENDIANESS = 0, // swap endianess, needed when used in conjunction with a little endian core like Ariane + parameter ADDR_OFFSET = `AXI4_ADDR_WIDTH'h0, + parameter ADDR_SWAP_LBITS = 0, // number of moved low bits in AXI address for memory interleaving + parameter ADDR_SWAP_MSB = `AXI4_ADDR_WIDTH-1, // high position to put moved bits in AXI address + parameter ADDR_SWAP_LSB = 6, // low position of moved bits in AXI address + parameter RDWR_INORDER = 0, // control of Rd/Wr responses order + // "Outstanding requests" queue parameters + parameter NUM_REQ_OUTSTANDING_LOG2 = 2, + parameter OUTSTAND_QUEUE_BRAM = 0, + parameter NUM_REQ_MSHRID_LBIT = 0, + parameter NUM_REQ_MSHRID_BITS = 0, + parameter NUM_REQ_YTHREADS = 1, + parameter NUM_REQ_XTHREADS = 1, + parameter SRCXY_AS_AXIID = 0 +) ( // Clock + Reset input wire clk, input wire rst_n, input wire uart_boot_en, input wire phy_init_done, + output axi_id_deadlock, // Noc interface input wire src_bridge_vr_noc2_val, @@ -60,8 +78,8 @@ module noc_axi4_bridge ( input wire m_axi_awready, output wire [`AXI4_ID_WIDTH -1:0] m_axi_wid, - output wire [`AXI4_DATA_WIDTH -1:0] m_axi_wdata, - output wire [`AXI4_STRB_WIDTH -1:0] m_axi_wstrb, + output wire [AXI4_DAT_WIDTH_USED-1:0] m_axi_wdata, + output wire [AXI4_DAT_WIDTH_USED/8-1:0] m_axi_wstrb, output wire m_axi_wlast, output wire [`AXI4_USER_WIDTH -1:0] m_axi_wuser, output wire m_axi_wvalid, @@ -82,7 +100,7 @@ module noc_axi4_bridge ( input wire m_axi_arready, input wire [`AXI4_ID_WIDTH -1:0] m_axi_rid, - input wire [`AXI4_DATA_WIDTH -1:0] m_axi_rdata, + input wire [AXI4_DAT_WIDTH_USED-1:0] m_axi_rdata, input wire [`AXI4_RESP_WIDTH -1:0] m_axi_rresp, input wire m_axi_rlast, input wire [`AXI4_USER_WIDTH -1:0] m_axi_ruser, @@ -101,21 +119,24 @@ wire [`AXI4_DATA_WIDTH-1:0] deser_data; wire deser_val; wire deser_rdy; -wire [`MSG_HEADER_WIDTH-1:0] read_req_header; -wire [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] read_req_id; +wire [`AXI4_ADDR_WIDTH -1:0] read_req_addr; +wire [`MSG_DATA_SIZE_WIDTH-1:0] read_req_size_log; +wire [`AXI4_ID_WIDTH -1:0] read_req_id; wire read_req_val; wire read_req_rdy; wire [`AXI4_DATA_WIDTH-1:0] read_resp_data; -wire [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] read_resp_id; +wire [`AXI4_ID_WIDTH -1:0] read_resp_id; wire read_resp_val; wire read_resp_rdy; wire write_req_val; -wire [`MSG_HEADER_WIDTH-1:0] write_req_header; -wire [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] write_req_id; +wire [`AXI4_ADDR_WIDTH -1:0] write_req_addr; +wire [`MSG_DATA_SIZE_WIDTH-1:0] write_req_size_log; +wire [`AXI4_ID_WIDTH -1:0] write_req_id; wire [`AXI4_DATA_WIDTH-1:0] write_req_data; +wire [`AXI4_STRB_WIDTH-1:0] write_req_strb; wire write_req_rdy; -wire [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] write_resp_id; +wire [`AXI4_ID_WIDTH-1:0] write_resp_id; wire write_resp_val; wire write_resp_rdy; @@ -125,16 +146,33 @@ wire ser_val; wire ser_rdy; -noc_axi4_bridge_buffer noc_axi4_bridge_buffer( +noc_axi4_bridge_buffer #( + .AXI4_DAT_WIDTH_USED (AXI4_DAT_WIDTH_USED), + .ADDR_OFFSET (ADDR_OFFSET), + .ADDR_SWAP_LBITS(ADDR_SWAP_LBITS), + .ADDR_SWAP_MSB (ADDR_SWAP_MSB), + .ADDR_SWAP_LSB (ADDR_SWAP_LSB), + .RDWR_INORDER (RDWR_INORDER), + .NUM_REQ_OUTSTANDING_LOG2 (NUM_REQ_OUTSTANDING_LOG2), + .OUTSTAND_QUEUE_BRAM (OUTSTAND_QUEUE_BRAM), + .NUM_REQ_MSHRID_LBIT (NUM_REQ_MSHRID_LBIT), + .NUM_REQ_MSHRID_BITS (NUM_REQ_MSHRID_BITS), + .NUM_REQ_YTHREADS (NUM_REQ_YTHREADS), + .NUM_REQ_XTHREADS (NUM_REQ_XTHREADS), + .SRCXY_AS_AXIID (SRCXY_AS_AXIID ) +) noc_axi4_bridge_buffer ( .clk(clk), .rst_n(rst_n), + .uart_boot_en(uart_boot_en), + .axi_id_deadlock(axi_id_deadlock), .deser_header(deser_header), .deser_data(deser_data), .deser_val(deser_val), .deser_rdy(deser_rdy), - .read_req_header(read_req_header), + .read_req_addr(read_req_addr), + .read_req_size_log(read_req_size_log), .read_req_id(read_req_id), .read_req_val(read_req_val), .read_req_rdy(read_req_rdy), @@ -144,9 +182,11 @@ noc_axi4_bridge_buffer noc_axi4_bridge_buffer( .read_resp_val(read_resp_val), .read_resp_rdy(read_resp_rdy), - .write_req_header(write_req_header), + .write_req_addr(write_req_addr), + .write_req_size_log(write_req_size_log), .write_req_id(write_req_id), .write_req_data(write_req_data), + .write_req_strb(write_req_strb), .write_req_val(write_req_val), .write_req_rdy(write_req_rdy), @@ -160,7 +200,9 @@ noc_axi4_bridge_buffer noc_axi4_bridge_buffer( .ser_rdy(ser_rdy) ); -noc_axi4_bridge_deser noc_axi4_bridge_deser( +noc_axi4_bridge_deser #( + .SWAP_ENDIANESS (SWAP_ENDIANESS) +) noc_axi4_bridge_deser ( .clk(clk), .rst_n(rst_n), @@ -175,14 +217,16 @@ noc_axi4_bridge_deser noc_axi4_bridge_deser( .out_rdy(deser_rdy) ); -noc_axi4_bridge_read noc_axi4_bridge_read ( +noc_axi4_bridge_read #( + .AXI4_DAT_WIDTH_USED (AXI4_DAT_WIDTH_USED) +) noc_axi4_bridge_read ( .clk(clk), .rst_n(rst_n), - .uart_boot_en(uart_boot_en), // NOC interface .req_val(read_req_val), - .req_header(read_req_header), + .req_addr(read_req_addr), + .req_size_log(read_req_size_log), .req_id(read_req_id), .req_rdy(read_req_rdy), @@ -215,17 +259,20 @@ noc_axi4_bridge_read noc_axi4_bridge_read ( .m_axi_rready(m_axi_rready) ); -noc_axi4_bridge_write noc_axi4_bridge_write ( +noc_axi4_bridge_write #( + .AXI4_DAT_WIDTH_USED (AXI4_DAT_WIDTH_USED) +) noc_axi4_bridge_write ( // Clock + Reset .clk(clk), .rst_n(rst_n), - .uart_boot_en(uart_boot_en), // NOC interface .req_val(write_req_val), - .req_header(write_req_header), + .req_addr(write_req_addr), + .req_size_log(write_req_size_log), .req_id(write_req_id), .req_data(write_req_data), + .req_strb(write_req_strb), .req_rdy(write_req_rdy), .resp_val(write_resp_val), @@ -262,7 +309,9 @@ noc_axi4_bridge_write noc_axi4_bridge_write ( .m_axi_bready(m_axi_bready) ); -noc_axi4_bridge_ser noc_axi4_bridge_ser( +noc_axi4_bridge_ser #( + .SWAP_ENDIANESS (SWAP_ENDIANESS) +) noc_axi4_bridge_ser ( .clk(clk), .rst_n(rst_n), diff --git a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_buffer.sv b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_buffer.sv new file mode 100644 index 000000000..238da9475 --- /dev/null +++ b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_buffer.sv @@ -0,0 +1,663 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 +// ========== Copyright Header Begin ============================================ +// Copyright (c) 2019 Princeton University +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * Neither the name of Princeton University nor the +// names of its contributors may be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ========== Copyright Header End ============================================ + +`include "mc_define.h" +`include "define.tmp.h" +`include "noc_axi4_bridge_define.vh" + + +package noc_axi4_bridge_pkg; +function automatic integer clip2zer; + input integer val; + clip2zer = val < 0 ? 0 : val; +endfunction + +function automatic [`NOC_DATA_WIDTH -1:0] swapData; + input [ `NOC_DATA_WIDTH -1:0] data; + input [`MSG_DATA_SIZE_WIDTH -1:0] size_log; + reg [ `MSG_DATA_SIZE_WIDTH -1:0] swap_granlty_log; + reg [$clog2(`NOC_DATA_WIDTH/8) -1:0] swap_granlty; + reg [$clog2(`NOC_DATA_WIDTH/8) :0] itr_swp; + reg [$clog2(`NOC_DATA_WIDTH/8) -1:0] swap_granlties; + reg [$clog2(`NOC_DATA_WIDTH/8) :0] itr_grn; + reg [$clog2(`NOC_DATA_WIDTH/8) -1:0] lo_swap_idx; + reg [$clog2(`NOC_DATA_WIDTH/8) -1:0] hi_swap_idx; + begin + // limiting swapping granularity to data width + swap_granlty_log = size_log < $clog2(`NOC_DATA_WIDTH/8) ? size_log : $clog2(`NOC_DATA_WIDTH/8); + + swap_granlties = ((`NOC_DATA_WIDTH/8) >> swap_granlty_log) - 1; + swap_granlty = ( 1 << swap_granlty_log) - 1; + + for (itr_grn = 0; itr_grn <= swap_granlties; itr_grn = itr_grn+1) + for (itr_swp = 0; itr_swp <= swap_granlty ; itr_swp = itr_swp+1) begin + lo_swap_idx = (itr_grn << swap_granlty_log) + itr_swp; + hi_swap_idx = (itr_grn << swap_granlty_log) + swap_granlty - itr_swp; + swapData[lo_swap_idx*8 +: 8] = data[hi_swap_idx*8 +: 8]; + end + end +endfunction +endpackage + +import noc_axi4_bridge_pkg::*; + +module noc_axi4_bridge_buffer #( + parameter AXI4_DAT_WIDTH_USED = `AXI4_DATA_WIDTH, // actually used AXI Data width (down converted if needed) + parameter ADDR_OFFSET = `AXI4_ADDR_WIDTH'h0, + parameter ADDR_SWAP_LBITS = 0, // number of moved low bits in AXI address for memory interleaving + parameter ADDR_SWAP_MSB = `AXI4_ADDR_WIDTH-1, // high position to put moved bits in AXI address + parameter ADDR_SWAP_LSB = 6, // low position of moved bits in AXI address + // Control of Rd/Wr responses order. Being enabled, enforces Rd/Wr response order to the NOC the same as Rd/Wr requests came from the NOC. + // The feature was implemented because of bug not yet discovered in noc_axi4_brodge_ser. It made looking OP as not tolerant to Rd/Wr reordering, + // what became not true after bug fix. Anyway the feature is left as fully tested and functionable but assumes the possibility of + // "Rd/Wr AXI ID thread deadlock" if multiple IDs are used. A detection of such event is implemented, but was never met from connected + // HBM/DDR/BRAM/URAM memories before the above bug fix and after. + parameter RDWR_INORDER = 0, + // "Outstanding requests" queue parameters + parameter NUM_REQ_OUTSTANDING_LOG2 = 2, // "Outstanding requests" queue size + parameter OUTSTAND_QUEUE_BRAM = 0, // "Outstanding requests" queue is implemented on BRAM (using Xilinx true 2-port BRAM synth template) + parameter NUM_REQ_MSHRID_LBIT = 0, // particular NOC fields to participate in AXI ID + parameter NUM_REQ_MSHRID_BITS = 0, + parameter NUM_REQ_YTHREADS = 1, // high component of number of "Outstanding requests" threads + parameter NUM_REQ_XTHREADS = 1, // low component of number of "Outstanding requests" threads + parameter SRCXY_AS_AXIID = 0 // defines NOC tile x/y field to use for forming AXI ID (INI_X/Y by default) +) ( + // ======== Buffer simplified structure ======== + // + // Input request queue + // (depth = `NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT) + // _________ ____________ + // | | | | |Address/Data| + // NOC deser in ------> | | | | ------------------------> | Conversion | ------> AXI read/write requests + // ___|_|_|_| | |____________| + // | + // | + // | Outstanding request queue + // | (depth = 1< | | | | ------> | | + // ___|_|_|_| | Data | + // |Conversion| ------> NOC ser out + // AXI read/write responses -----------------------------> |__________| + // + // ============================================= + + input clk, + input rst_n, + input uart_boot_en, + output reg axi_id_deadlock, + + // from deserializer + input [`MSG_HEADER_WIDTH-1:0] deser_header, + input [`AXI4_DATA_WIDTH-1:0] deser_data, + input deser_val, + output deser_rdy, + + // read request out + output [`AXI4_ADDR_WIDTH-1:0] read_req_addr, + output [`MSG_DATA_SIZE_WIDTH-1:0] read_req_size_log, + output [`AXI4_ID_WIDTH -1:0] read_req_id, + output read_req_val, + input read_req_rdy, + + // read response in + input [`AXI4_DATA_WIDTH-1:0] read_resp_data, + input [`AXI4_ID_WIDTH -1:0] read_resp_id, + input read_resp_val, + output read_resp_rdy, + + // write request out + output [`AXI4_ADDR_WIDTH-1:0] write_req_addr, + output [`MSG_DATA_SIZE_WIDTH-1:0] write_req_size_log, + output [`AXI4_ID_WIDTH -1:0] write_req_id, + output [`AXI4_DATA_WIDTH-1:0] write_req_data, + output [`AXI4_STRB_WIDTH-1:0] write_req_strb, + output write_req_val, + input write_req_rdy, + + // write response in + input [`AXI4_ID_WIDTH-1:0] write_resp_id, + input write_resp_val, + output write_resp_rdy, + + // in serializer + output [`MSG_HEADER_WIDTH-1:0] ser_header, + output [`AXI4_DATA_WIDTH-1:0] ser_data, + output ser_val, + input ser_rdy +); + +localparam INVALID = 1'd0; +localparam WAITING = 1'd1; + +localparam READ = 1'd0; +localparam WRITE = 1'd1; + + +reg [`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0] pkt_state_buf ; +reg [`MSG_HEADER_WIDTH-1:0] pkt_header[`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0]; +reg [`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0] pkt_command; + +reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] fifo_in; +reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] fifo_out; + +wire deser_go = (deser_rdy & deser_val); +wire read_req_go = (read_req_val & read_req_rdy); +// wire read_resp_go = (read_resp_val & read_resp_rdy); +wire write_req_go = (write_req_val & write_req_rdy); +// wire write_resp_go = (write_resp_val & write_resp_rdy); +wire req_go = read_req_go || write_req_go; +wire ser_go = ser_val & ser_rdy; + +// +// SEND REQUESTS +// + +always @(posedge clk) begin + if(~rst_n) begin + fifo_in <= {`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE{1'b0}}; + fifo_out <= {`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE{1'b0}}; + end + else begin + fifo_in <= deser_go ? fifo_in + 1 : fifo_in; + fifo_out <= req_go ? fifo_out + 1 : fifo_out; + end +end + + +genvar i; +generate + for (i = 0; i < `NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT; i = i + 1) begin + always @(posedge clk) begin + if(~rst_n) begin + pkt_state_buf[i] <= INVALID; + pkt_header[i] <= `MSG_HEADER_WIDTH'b0; + pkt_command[i] <= 1'b0; + end + else begin + if ((i == fifo_in) & deser_go) begin + pkt_state_buf[i] <= WAITING; + pkt_header[i] <= deser_header; + pkt_command[i] <= (deser_header[`MSG_TYPE] == `MSG_TYPE_STORE_MEM) + || (deser_header[`MSG_TYPE] == `MSG_TYPE_NC_STORE_REQ); + end + else if ((i == fifo_out) & req_go) + pkt_state_buf[i] <= INVALID; + end + end + end +endgenerate + +reg req_val; +always @(posedge clk) + if(~rst_n) req_val <= 1'b0; + else req_val <= (pkt_state_buf[fifo_out] == WAITING && !req_go); + +assign deser_rdy = (pkt_state_buf[fifo_in] == INVALID); +wire [`AXI4_DATA_WIDTH-1:0] wdata; + +// Xilinx-synthesizable Simple Dual Port Single Clock RAM +bram_sdp_1ck #( + .RAM_WIDTH(`AXI4_DATA_WIDTH), // Specify RAM data width + .RAM_DEPTH(`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT), // Specify RAM depth (number of entries) + .RAM_PERFORMANCE("LOW_LATENCY") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" +) noc_axi4_bridge_sram_data ( + .addra(fifo_in), // Write address bus, width determined from RAM_DEPTH + .addrb(fifo_out), // Read address bus, width determined from RAM_DEPTH + .dina(deser_data), // RAM input data, width determined from RAM_WIDTH + .clka(clk), // Clock + .wea(deser_go), // Write enable + .enb(1'b1), // Read Enable, for additional power savings, disable when not in use + .rstb(~rst_n), // Output reset (does not affect memory contents) + .regceb(1'b1), // Output register enable + .doutb(wdata) // RAM output data, width determined from RAM_WIDTH +); + +wire [`MSG_HEADER_WIDTH-1 :0] req_header = pkt_header[fifo_out]; + +wire [`MSG_SRC_CHIPID_WIDTH-1:0] src_chipid = req_header[`MSG_SRC_CHIPID]; +wire [`MSG_SRC_X_WIDTH -1:0] src_x = req_header[`MSG_SRC_X]; +wire [`MSG_SRC_Y_WIDTH -1:0] src_y = req_header[`MSG_SRC_Y]; +wire [`MSG_SRC_FBITS_WIDTH -1:0] src_fbits = req_header[`MSG_SRC_FBITS]; +wire [`MSG_SRC_X_WIDTH -1:0] ini_x = req_header[`MSG_INI_X]; +wire [`MSG_SRC_Y_WIDTH -1:0] ini_y = req_header[`MSG_INI_Y]; + +wire [`MSG_DST_CHIPID_WIDTH-1:0] dst_chipid = req_header[`MSG_DST_CHIPID]; +wire [`MSG_DST_X_WIDTH -1:0] dst_x = req_header[`MSG_DST_X]; +wire [`MSG_DST_Y_WIDTH -1:0] dst_y = req_header[`MSG_DST_Y]; +wire [`MSG_DST_FBITS_WIDTH -1:0] dst_fbits = req_header[`MSG_DST_FBITS]; + +wire [`MSG_MSHRID_WIDTH -1:0] mshrid = req_header[`MSG_MSHRID]; +wire [`MSG_LSID_WIDTH -1:0] lsid = req_header[`MSG_LSID]; +wire [`MSG_SDID_WIDTH -1:0] sdid = req_header[`MSG_SDID]; +wire [`MSG_TYPE_WIDTH -1:0] msg_type = req_header[`MSG_TYPE]; +wire [`MSG_DATA_SIZE_WIDTH -1:0] data_size = req_header[`MSG_DATA_SIZE]; +wire [`MSG_LENGTH_WIDTH -1:0] msg_length = req_header[`MSG_LENGTH]; + + +// Transformation of write data according to queueed request +wire [$clog2(`AXI4_DATA_WIDTH/8)-1:0] req_offset; +wire [`MSG_DATA_SIZE_WIDTH -1:0] req_size_log; +noc_extractSize req_extractSize( + .header (req_header), + .size_log(req_size_log), + .offset (req_offset)); + +assign read_req_size_log = req_size_log; +assign write_req_size_log = req_size_log; + +wire [$clog2(`AXI4_DATA_WIDTH/8) :0] req_size = 1 << req_size_log; +wire [`AXI4_STRB_WIDTH-1:0] wstrb = ({`AXI4_STRB_WIDTH'h0,1'b1} << req_size) -`AXI4_STRB_WIDTH'h1; +assign write_req_data = wdata << (8*req_offset[$clog2(AXI4_DAT_WIDTH_USED/8)-1:0]); +assign write_req_strb = wstrb << req_offset[$clog2(AXI4_DAT_WIDTH_USED/8)-1:0]; + + +wire [`PHY_ADDR_WIDTH -1:0] virt_addr = req_header[`MSG_ADDR]; +wire [`AXI4_ADDR_WIDTH-1:0] phys_addr; + +// If running uart tests - we need to do address translation +`ifdef PITONSYS_UART_BOOT +storage_addr_trans_unified #( +`else +storage_addr_trans #( +`endif +.STORAGE_ADDR_WIDTH(`AXI4_ADDR_WIDTH) +) cpu_mig_addr_translator ( + .va_byte_addr (virt_addr ), + .storage_addr_out (phys_addr ) +); + +wire [`AXI4_ADDR_WIDTH-1:0] addr = uart_boot_en ? {phys_addr[`AXI4_ADDR_WIDTH-4:0], 3'b0} : virt_addr - ADDR_OFFSET; +wire [`AXI4_ADDR_WIDTH-1:0] req_addr; +generate + if (ADDR_SWAP_LBITS) + assign req_addr = {addr[`AXI4_ADDR_WIDTH-1 : ADDR_SWAP_MSB ], + addr[ADDR_SWAP_LSB +: ADDR_SWAP_LBITS ], // Low address part moved up + addr[ADDR_SWAP_MSB-1 : ADDR_SWAP_LSB + ADDR_SWAP_LBITS], // High address part shifted down + addr[ADDR_SWAP_LSB-1 : 0]} & ({`AXI4_ADDR_WIDTH{1'b1}} << req_size_log); + else + assign req_addr = addr & ({`AXI4_ADDR_WIDTH{1'b1}} << req_size_log); +endgenerate + +assign read_req_addr = req_addr; +assign write_req_addr = req_addr; + + +// +// GET_RESPONSE +// + +localparam NUM_REQ_YTHREADS_LOG2 = $clog2(NUM_REQ_YTHREADS); +localparam NUM_REQ_XTHREADS_LOG2 = $clog2(NUM_REQ_XTHREADS); +localparam NUM_REQ_THREADS_LOG2 = NUM_REQ_YTHREADS_LOG2 + NUM_REQ_XTHREADS_LOG2 + NUM_REQ_MSHRID_BITS; +localparam FULL_NUM_REQ_THREADS_LOG2 = NUM_REQ_THREADS_LOG2 + (RDWR_INORDER ? 0:1); // read/write request type goes as an extension to thread ID if RDWR_INORDER=0 +localparam NUM_REQ_THREADS = 1 << FULL_NUM_REQ_THREADS_LOG2; + +reg [NUM_REQ_OUTSTANDING_LOG2 : 0] outstnd_vrt_wrptrs[NUM_REQ_THREADS-1 : 0]; +reg [NUM_REQ_OUTSTANDING_LOG2 : 0] outstnd_vrt_rdptrs[NUM_REQ_THREADS-1 : 0]; + +reg [NUM_REQ_THREADS-1 : 0] outstnd_vrt_empts; +reg [FULL_NUM_REQ_THREADS_LOG2 : 0] itr_empt; +always @(*) + for (itr_empt = 0; itr_empt < NUM_REQ_THREADS; itr_empt = itr_empt+1) + outstnd_vrt_empts[itr_empt] = (outstnd_vrt_rdptrs[itr_empt] == outstnd_vrt_wrptrs[itr_empt]); + + +reg [clip2zer(FULL_NUM_REQ_THREADS_LOG2-1) : 0] full_resp_id; +reg [NUM_REQ_OUTSTANDING_LOG2-1 : 0] outstnd_abs_rdptrs[NUM_REQ_THREADS-1 : 0]; +wire [NUM_REQ_OUTSTANDING_LOG2-1 : 0] outstnd_abs_rdptr = outstnd_abs_rdptrs[full_resp_id]; + +reg init_outstnd_mem; +always @(posedge clk) + if(~rst_n) init_outstnd_mem <= 1'b1; + else if (outstnd_abs_rdptr == {NUM_REQ_OUTSTANDING_LOG2{1'b1}}) init_outstnd_mem <= 1'b0; + + +reg [NUM_REQ_THREADS-1 : 0] outstnd_abs_rdptrs_val; +wire outstnd_abs_rdptr_val = outstnd_abs_rdptrs_val[full_resp_id]; +wire outstnd_vrt_empt = outstnd_vrt_empts [full_resp_id]; +reg [NUM_REQ_THREADS-1 : 0] outstnd_command; // the vector stores the latest command type for particular ID, needed and effective only in RDWR_INORDER mode +wire [clip2zer(FULL_NUM_REQ_THREADS_LOG2-1) : 0] full_rd_resp_id = ({1'b0,{FULL_NUM_REQ_THREADS_LOG2{READ }}} << NUM_REQ_THREADS_LOG2) | (read_resp_id & ((1<< NUM_REQ_THREADS_LOG2)-1)); +wire [clip2zer(FULL_NUM_REQ_THREADS_LOG2-1) : 0] full_wr_resp_id = ({1'b0,{FULL_NUM_REQ_THREADS_LOG2{WRITE}}} << NUM_REQ_THREADS_LOG2) | (write_resp_id & ((1<< NUM_REQ_THREADS_LOG2)-1)); +// masking outstnd_command by RDWR_INORDER just to reduce extra-logic (outstnd_command is not effective if RDWR_INORDER=0 anyway) +wire read_resp_val_act = read_resp_val && (!RDWR_INORDER || (!outstnd_command[full_rd_resp_id] && outstnd_abs_rdptrs_val[full_rd_resp_id])); +wire write_resp_val_act = write_resp_val && (!RDWR_INORDER || ( outstnd_command[full_wr_resp_id] && outstnd_abs_rdptrs_val[full_wr_resp_id])); +reg resp_val; +always @(posedge clk) + if(~rst_n || init_outstnd_mem) begin + full_resp_id <= {1'b0,{FULL_NUM_REQ_THREADS_LOG2{1'b0}}}; + resp_val <= 1'b0; + axi_id_deadlock <= 1'b0; + end + else begin + if (outstnd_vrt_empt || outstnd_abs_rdptr_val) begin + // Higher priority for Read response in case we have not already started working with the Write response ID some earlier, + // In order to change priority two following strings should be exchanged (the condition is symmetrical) + if (write_resp_val_act && !(read_resp_val_act && (full_resp_id == full_rd_resp_id))) full_resp_id <= full_wr_resp_id; + if (read_resp_val_act && !(write_resp_val_act && (full_resp_id == full_wr_resp_id))) full_resp_id <= full_rd_resp_id; + + if (write_resp_val_act || + read_resp_val_act) resp_val <= 1'b1; + + // Catching "Rd/Wr AXI ID thread deadlock" possible in RDWR_INORDER mode with multiple IDs: + // both Rd and Wr responses simultaneously don't correspond to expected inorder ones. + // Masking the condition by RDWR_INORDER just to reduce extra-logic (outstnd_command is not effective if RDWR_INORDER=0 anyway) + if (read_resp_val && outstnd_command[full_rd_resp_id] && outstnd_abs_rdptrs_val[full_rd_resp_id] && + write_resp_val && !outstnd_command[full_wr_resp_id] && outstnd_abs_rdptrs_val[full_wr_resp_id] && RDWR_INORDER) + axi_id_deadlock <= 1'b1; + end + if (ser_go) resp_val <= 1'b0; + end + + +localparam OUTSTND_HDR_WIDTH = (NUM_REQ_OUTSTANDING_LOG2+1) + NUM_REQ_OUTSTANDING_LOG2 + 1 + `MSG_HEADER_WIDTH; +wire [OUTSTND_HDR_WIDTH-1 : 0] clean_header; +wire req_occup = clean_header[`MSG_HEADER_WIDTH]; + +reg [NUM_REQ_OUTSTANDING_LOG2-1 : 0] outstnd_abs_wrptr; +wire [NUM_REQ_OUTSTANDING_LOG2-1 : 0] outstnd_abs_wrptr_mem = outstnd_abs_wrptr + {{(NUM_REQ_OUTSTANDING_LOG2-1){1'b0}}, + (~init_outstnd_mem & req_occup)}; +always @(posedge clk) + if(~rst_n) outstnd_abs_wrptr <= {NUM_REQ_OUTSTANDING_LOG2{1'b0}}; + else outstnd_abs_wrptr <= outstnd_abs_wrptr_mem; // searching for first free request location + + +wire req_command = pkt_command[fifo_out]; +wire [`MSG_SRC_X_WIDTH -1:0] req_tile_x = SRCXY_AS_AXIID ? req_header[`MSG_SRC_X] : req_header[`MSG_INI_X]; +wire [`MSG_SRC_Y_WIDTH -1:0] req_tile_y = SRCXY_AS_AXIID ? req_header[`MSG_SRC_Y] : req_header[`MSG_INI_Y]; +wire [`MSG_MSHRID_WIDTH-1:0] req_mshrid = req_header[`MSG_MSHRID]; +wire [clip2zer(NUM_REQ_THREADS_LOG2-1):0] req_id = (((req_mshrid >> NUM_REQ_MSHRID_LBIT) + & ((1<< NUM_REQ_MSHRID_BITS )-1)) << (NUM_REQ_YTHREADS_LOG2+ + NUM_REQ_XTHREADS_LOG2)) | + ((req_tile_y & ((1<< NUM_REQ_YTHREADS_LOG2)-1)) << NUM_REQ_XTHREADS_LOG2) | + ( req_tile_x & ((1<< NUM_REQ_XTHREADS_LOG2)-1)); +wire [clip2zer(FULL_NUM_REQ_THREADS_LOG2-1) : 0] full_req_id = ({1'b0,{FULL_NUM_REQ_THREADS_LOG2{req_command}}} << NUM_REQ_THREADS_LOG2) | req_id; + +wire [OUTSTND_HDR_WIDTH-1 : 0] stor_header; +wire stor_command = (stor_header[`MSG_TYPE] == `MSG_TYPE_STORE_MEM) || + (stor_header[`MSG_TYPE] == `MSG_TYPE_NC_STORE_REQ); +wire [`MSG_SRC_X_WIDTH -1:0] stor_tile_x = SRCXY_AS_AXIID ? stor_header[`MSG_SRC_X] : stor_header[`MSG_INI_X]; +wire [`MSG_SRC_Y_WIDTH -1:0] stor_tile_y = SRCXY_AS_AXIID ? stor_header[`MSG_SRC_Y] : stor_header[`MSG_INI_Y]; +wire [`MSG_MSHRID_WIDTH-1:0] stor_mshrid = stor_header[`MSG_MSHRID]; +wire [clip2zer(NUM_REQ_THREADS_LOG2-1):0] stor_id = (((stor_mshrid >> NUM_REQ_MSHRID_LBIT) + & ((1<< NUM_REQ_MSHRID_BITS )-1)) << (NUM_REQ_YTHREADS_LOG2+ + NUM_REQ_XTHREADS_LOG2)) | + ((stor_tile_y & ((1<< NUM_REQ_YTHREADS_LOG2)-1)) << NUM_REQ_XTHREADS_LOG2) | + ( stor_tile_x & ((1<< NUM_REQ_XTHREADS_LOG2)-1)); +wire [clip2zer(FULL_NUM_REQ_THREADS_LOG2-1) : 0] full_stor_id = ({1'b0,{FULL_NUM_REQ_THREADS_LOG2{stor_command}}} << NUM_REQ_THREADS_LOG2) | stor_id; + +wire [NUM_REQ_OUTSTANDING_LOG2-1 : 0] outstnd_vrt_rdptr = outstnd_vrt_rdptrs[full_resp_id]; +wire outstnd_vrt_rdptr_val = (outstnd_vrt_rdptr == stor_header[`MSG_HEADER_WIDTH+1 +: NUM_REQ_OUTSTANDING_LOG2] && + full_resp_id == full_stor_id && stor_header[`MSG_HEADER_WIDTH]); +wire [NUM_REQ_OUTSTANDING_LOG2-1 : 0] outstnd_abs_rdptr_mem = outstnd_abs_rdptr + {{(NUM_REQ_OUTSTANDING_LOG2-1){1'b0}}, + (~ outstnd_vrt_empt & + ~(outstnd_vrt_rdptr_val | + outstnd_abs_rdptr_val))}; +reg [NUM_REQ_OUTSTANDING_LOG2 : 0] outstnd_wrreq_cnt; +reg [NUM_REQ_OUTSTANDING_LOG2 : 0] outstnd_rdreq_cnt; +reg [NUM_REQ_OUTSTANDING_LOG2 : 0] outstnd_wrrsp_cnt; +reg [NUM_REQ_OUTSTANDING_LOG2 : 0] outstnd_rdrsp_cnt; +wire [NUM_REQ_OUTSTANDING_LOG2 : 0] outstnd_rsp_cnt = stor_header[NUM_REQ_OUTSTANDING_LOG2 + `MSG_HEADER_WIDTH+1 +: NUM_REQ_OUTSTANDING_LOG2+1]; +reg dbg_wr_reorder; +reg dbg_rd_reorder; +reg [FULL_NUM_REQ_THREADS_LOG2 : 0] itr_ptr; +always @(posedge clk) + if(~rst_n) begin + for (itr_ptr = 0; itr_ptr < NUM_REQ_THREADS; itr_ptr = itr_ptr+1) begin + outstnd_vrt_wrptrs[itr_ptr] <= {(NUM_REQ_OUTSTANDING_LOG2+1){1'b0}}; + outstnd_vrt_rdptrs[itr_ptr] <= {(NUM_REQ_OUTSTANDING_LOG2+1){1'b0}}; + outstnd_abs_rdptrs[itr_ptr] <= { NUM_REQ_OUTSTANDING_LOG2 {1'b0}}; + outstnd_abs_rdptrs_val[itr_ptr] <= 1'b0; + outstnd_wrreq_cnt <= {(NUM_REQ_OUTSTANDING_LOG2+1){1'b0}}; + outstnd_rdreq_cnt <= {(NUM_REQ_OUTSTANDING_LOG2+1){1'b0}}; + outstnd_wrrsp_cnt <= {(NUM_REQ_OUTSTANDING_LOG2+1){1'b0}}; + outstnd_rdrsp_cnt <= {(NUM_REQ_OUTSTANDING_LOG2+1){1'b0}}; + dbg_wr_reorder <= 1'b0; + dbg_rd_reorder <= 1'b0; + end + end + else begin + if (req_go) begin + outstnd_vrt_wrptrs[full_req_id] <= outstnd_vrt_wrptrs[full_req_id] + 1; + if (outstnd_vrt_empts[full_req_id]) begin + outstnd_abs_rdptrs [full_req_id] <= outstnd_abs_wrptr; + outstnd_abs_rdptrs_val[full_req_id] <= 1'b1; + outstnd_command [full_req_id] <= req_command; + end + if (req_command) outstnd_wrreq_cnt <= outstnd_wrreq_cnt + 1; + else outstnd_rdreq_cnt <= outstnd_rdreq_cnt + 1; + end + if (!outstnd_vrt_empt) begin + if (!outstnd_abs_rdptr_val && outstnd_vrt_rdptr_val) begin + outstnd_abs_rdptrs_val[full_resp_id] <= 1'b1; + outstnd_command [full_resp_id] <= stor_command; + end + // searching for the next valid request location for responded ID + outstnd_abs_rdptrs[full_resp_id] <= outstnd_abs_rdptr_mem; + end + if (ser_go) begin + outstnd_vrt_rdptrs [full_resp_id] <= outstnd_vrt_rdptrs[full_resp_id] + 1; + outstnd_abs_rdptrs_val[full_resp_id] <= 1'b0; + if (stor_command) begin + dbg_wr_reorder <= outstnd_wrrsp_cnt != outstnd_rsp_cnt; + outstnd_wrrsp_cnt <= outstnd_wrrsp_cnt + 1; + end + else begin + dbg_rd_reorder <= outstnd_rdrsp_cnt != outstnd_rsp_cnt; + outstnd_rdrsp_cnt <= outstnd_rdrsp_cnt + 1; + end + end + // Initialization of Outstanding requests memory + if (init_outstnd_mem) outstnd_abs_rdptrs[full_resp_id] <= outstnd_abs_rdptr + 1; + end + +reg dbg_rd_reorder_ff; +reg dbg_wr_reorder_ff; +localparam REORDER_NUM_LOG = 5; +reg [REORDER_NUM_LOG-1 : 0] rd_reorder_cnt; +reg [REORDER_NUM_LOG-1 : 0] wr_reorder_cnt; +always @(posedge clk) + if(~rst_n) begin + dbg_rd_reorder_ff <= 1'b0; + dbg_wr_reorder_ff <= 1'b0; + rd_reorder_cnt <= 0; + wr_reorder_cnt <= 0; + end + else begin + dbg_rd_reorder_ff <= dbg_rd_reorder; + dbg_wr_reorder_ff <= dbg_wr_reorder; + if (dbg_rd_reorder & ~dbg_rd_reorder_ff) rd_reorder_cnt <= rd_reorder_cnt+1; + if (dbg_wr_reorder & ~dbg_wr_reorder_ff) wr_reorder_cnt <= wr_reorder_cnt+1; + end + +assign read_req_val = req_val && !req_command && !req_occup && !init_outstnd_mem; +assign read_req_id = req_id; +assign write_req_val = req_val && req_command && !req_occup && !init_outstnd_mem; +assign write_req_id = req_id; + +wire [NUM_REQ_OUTSTANDING_LOG2-1 : 0] outstnd_vrt_wrptr = outstnd_vrt_wrptrs[full_req_id]; +wire [NUM_REQ_OUTSTANDING_LOG2 : 0] outstnd_req_cnt = req_command ? outstnd_wrreq_cnt : + outstnd_rdreq_cnt; +wire [OUTSTND_HDR_WIDTH-1 : 0] save_header = {outstnd_req_cnt,outstnd_vrt_wrptr,1'b1,req_header}; + +generate +if (OUTSTAND_QUEUE_BRAM) begin: outstand_queue_bram +// Xilinx-synthesizable True Dual Port RAM, Write_First, Single Clock +bram_tdp_1ck_wrfirst #( + .RAM_WIDTH(OUTSTND_HDR_WIDTH), // Specify RAM data width + .RAM_DEPTH(1 << NUM_REQ_OUTSTANDING_LOG2), // Specify RAM depth (number of entries) + .RAM_PERFORMANCE("LOW_LATENCY") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" +) outstnd_req_mem ( + .addra(outstnd_abs_rdptr_mem), // Port A address bus, width determined from RAM_DEPTH + .addrb(outstnd_abs_wrptr_mem), // Port B address bus, width determined from RAM_DEPTH + .dina({OUTSTND_HDR_WIDTH{1'b0}}), // Port A RAM input data, width determined from RAM_WIDTH + .dinb(save_header), // Port B RAM input data, width determined from RAM_WIDTH + .clka(clk), // Clock + .wea(ser_go | init_outstnd_mem), // Port A write enable + .web(req_go), // Port B write enable + .ena(1'b1), // Port A RAM Enable, for additional power savings, disable port when not in use + .enb(1'b1), // Port B RAM Enable, for additional power savings, disable port when not in use + .rsta(~rst_n), // Port A output reset (does not affect memory contents) + .rstb(~rst_n), // Port B output reset (does not affect memory contents) + .regcea(1'b1), // Port A output register enable + .regceb(1'b1), // Port B output register enable + .douta(stor_header), // Port A RAM output data, width determined from RAM_WIDTH + .doutb(clean_header) // Port B RAM output data, width determined from RAM_WIDTH +); +end + +else begin: outstand_queue_regs + reg [OUTSTND_HDR_WIDTH-1:0] outstnd_req_mem [(1<> (8*stor_offset[$clog2(AXI4_DAT_WIDTH_USED/8)-1:0]); + +wire [$clog2(`AXI4_DATA_WIDTH/8) :0] stor_size = 1 << stor_size_log; +wire [`AXI4_DATA_WIDTH -1:0] rdata = stor_size[0] ? {64 {rdata_offseted[0 +: `AXI4_DATA_WIDTH/64]}} : + stor_size[1] ? {32 {rdata_offseted[0 +: `AXI4_DATA_WIDTH/32]}} : + stor_size[2] ? {16 {rdata_offseted[0 +: `AXI4_DATA_WIDTH/16]}} : + stor_size[3] ? {8 {rdata_offseted[0 +: `AXI4_DATA_WIDTH/8 ]}} : + stor_size[4] ? {4 {rdata_offseted[0 +: `AXI4_DATA_WIDTH/4 ]}} : + stor_size[5] ? {2 {rdata_offseted[0 +: `AXI4_DATA_WIDTH/2 ]}} : + stor_size[6] ? rdata_offseted : `AXI4_DATA_WIDTH'h0; + +assign ser_val = stor_hdr_en; +assign ser_data = stor_command ? `AXI4_DATA_WIDTH'b0 : rdata; +assign ser_header = stor_header; + + +/* +ila_buffer ila_buffer ( + .clk(clk), // input wire clk + + + .probe0(deser_header), // input wire [191:0] probe0 + .probe1(deser_data), // input wire [511:0] probe1 + .probe2(deser_val), // input wire [0:0] probe2 + .probe3(deser_rdy), // input wire [0:0] probe3 + .probe4(ser_header), // input wire [191:0] probe4 + .probe5(ser_data), // input wire [511:0] probe5 + .probe6(ser_val), // input wire [0:0] probe6 + .probe7(ser_rdy), // input wire [0:0] probe7 + .probe8(req_header), // input wire [191:0] probe8 + .probe9(read_req_id), // input wire [1:0] probe9 + .probe10(read_req_val), // input wire [0:0] probe10 + .probe11(read_req_rdy), // input wire [0:0] probe11 + .probe12(read_resp_data), // input wire [511:0] probe12 + .probe13(read_resp_id), // input wire [1:0] probe13 + .probe14(read_resp_val), // input wire [0:0] probe14 + .probe15(read_resp_rdy), // input wire [0:0] probe15 + .probe16(req_header), // input wire [191:0] probe16 + .probe17(write_req_id), // input wire [1:0] probe17 + .probe18(write_req_data), // input wire [511:0] probe18 + .probe19(write_req_val), // input wire [0:0] probe19 + .probe20(write_req_rdy), // input wire [0:0] probe20 + .probe21(write_resp_id), // input wire [1:0] probe21 + .probe22(write_resp_val), // input wire [0:0] probe22 + .probe23(write_resp_rdy), // input wire [0:0] probe23 + .probe24(fifo_in), // input wire [1:0] probe24 + .probe25(fifo_out), // input wire [1:0] probe25 + .probe26(preser_arb), // input wire [0:0] probe26 + .probe27(bram_rdy), // input wire [3:0] probe27 + .probe28(ser_data_f), // input wire [511:0] probe28 + .probe29(ser_header_f), // input wire [191:0] probe29 + .probe30(ser_val_f), // input wire [0:0] probe30 + .probe31(ser_data_ff), // input wire [511:0] probe31 + .probe32(ser_header_ff), // input wire [191:0] probe32 + .probe33(ser_val_ff), // input wire [0:0] probe33 + .probe34(rst_n) // input wire [0:0] probe34 +); + +reg [159:0] reqresp_count; +always @(posedge clk) begin + if (~rst_n) begin + reqresp_count <= 0; + end + else begin + reqresp_count <= ser_go & deser_go ? reqresp_count : + deser_go ? reqresp_count + 1 : + ser_go ? reqresp_count - 1 : + reqresp_count; + + end +end + +ila_axi_protocol_checker ila_axi_protocol_checker ( + .clk(clk), // input wire clk + + .probe0(rst_n), // input wire [0:0] probe0 + .probe1(reqresp_count) // input wire [159:0] probe1 +); +*/ + +endmodule + +module noc_extractSize ( + input [`MSG_HEADER_WIDTH -1:0] header, + output [`MSG_DATA_SIZE_WIDTH -1:0] size_log, + output [$clog2(`AXI4_DATA_WIDTH/8)-1:0] offset +); + wire [`PHY_ADDR_WIDTH-1:0] virt_addr = header[`MSG_ADDR]; + wire uncacheable = (virt_addr[`PHY_ADDR_WIDTH-1]) || + (header[`MSG_TYPE] == `MSG_TYPE_NC_LOAD_REQ) || + (header[`MSG_TYPE] == `MSG_TYPE_NC_STORE_REQ); + assign size_log = uncacheable ? header[`MSG_DATA_SIZE] - 1 : $clog2(`AXI4_DATA_WIDTH/8); + assign offset = uncacheable ? virt_addr : 0; +endmodule diff --git a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_buffer.v b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_buffer.v deleted file mode 100644 index 278c4244a..000000000 --- a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_buffer.v +++ /dev/null @@ -1,329 +0,0 @@ -// ========== Copyright Header Begin ============================================ -// Copyright (c) 2019 Princeton University -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// * Neither the name of Princeton University nor the -// names of its contributors may be used to endorse or promote products -// derived from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY -// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ========== Copyright Header End ============================================ - -`include "mc_define.h" -`include "define.tmp.h" -`include "noc_axi4_bridge_define.vh" - - -module noc_axi4_bridge_buffer ( - input clk, - input rst_n, - - // from deserializer - input [`MSG_HEADER_WIDTH-1:0] deser_header, - input [`AXI4_DATA_WIDTH-1:0] deser_data, - input deser_val, - output deser_rdy, - - // read request out - output [`MSG_HEADER_WIDTH-1:0] read_req_header, - output [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] read_req_id, - output read_req_val, - input read_req_rdy, - - // read response in - input [`AXI4_DATA_WIDTH-1:0] read_resp_data, - input [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] read_resp_id, - input read_resp_val, - output read_resp_rdy, - - // read request out - output [`MSG_HEADER_WIDTH-1:0] write_req_header, - output [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] write_req_id, - output [`AXI4_DATA_WIDTH-1:0] write_req_data, - output write_req_val, - input write_req_rdy, - - // read response in - input [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] write_resp_id, - input write_resp_val, - output write_resp_rdy, - - // in serializer - output [`MSG_HEADER_WIDTH-1:0] ser_header, - output [`AXI4_DATA_WIDTH-1:0] ser_data, - output ser_val, - input ser_rdy -); - -localparam INVALID = 1'd0; -localparam WAITING = 1'd1; - -localparam READ = 1'd0; -localparam WRITE = 1'd1; - - -reg [`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0] pkt_state_buf ; -reg [`MSG_HEADER_WIDTH-1:0] pkt_header[`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0]; -reg [`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0] pkt_command; - -reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] fifo_in; -reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] fifo_out; -reg preser_arb; -reg [`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0] bram_rdy; -reg [`AXI4_DATA_WIDTH-1:0] ser_data_f; -wire [`MSG_HEADER_WIDTH-1:0] ser_header_f; -reg ser_val_f; -reg [`AXI4_DATA_WIDTH-1:0] ser_data_ff; -reg [`MSG_HEADER_WIDTH-1:0] ser_header_ff; -reg ser_val_ff; - - -wire deser_go = (deser_rdy & deser_val); -wire read_req_go = (read_req_val & read_req_rdy); -wire read_resp_go = (read_resp_val & read_resp_rdy); -wire write_req_go = (write_req_val & write_req_rdy); -wire write_resp_go = (write_resp_val & write_resp_rdy); -wire req_go = read_req_go || write_req_go; -wire preser_rdy = ~ser_val_ff || ser_rdy; -wire ser_go = ser_val & ser_rdy; - -// -// SEND REQUESTS -// - -always @(posedge clk) begin - if(~rst_n) begin - fifo_in <= {`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE{1'b0}}; - fifo_out <= {`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE{1'b0}}; - end - else begin - fifo_in <= deser_go ? fifo_in + 1 : fifo_in; - fifo_out <= req_go ? fifo_out + 1 : fifo_out; - end -end - - -genvar i; -generate - for (i = 0; i < `NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT; i = i + 1) begin - always @(posedge clk) begin - if(~rst_n) begin - pkt_state_buf[i] <= INVALID; - pkt_header[i] <= `MSG_HEADER_WIDTH'b0; - pkt_command[i] <= 1'b0; - end - else begin - if ((i == fifo_in) & deser_go) begin - pkt_state_buf[i] <= WAITING; - pkt_header[i] <= deser_header; - pkt_command[i] <= (deser_header[`MSG_TYPE] == `MSG_TYPE_STORE_MEM) - || (deser_header[`MSG_TYPE] == `MSG_TYPE_NC_STORE_REQ); - end - else if ((i == fifo_out) & req_go) begin - pkt_state_buf[i] <= INVALID; - pkt_header[i] <= `MSG_HEADER_WIDTH'b0; - pkt_command[i] <= 1'b0; - end - else begin - pkt_state_buf[i] <= pkt_state_buf[i]; - pkt_header[i] <= pkt_header[i]; - pkt_command[i] <= pkt_command[i]; - end - end - end - end -endgenerate - -noc_axi4_bridge_sram_data noc_axi4_bridge_sram_data -( - .MEMCLK(clk), - .RESET_N(rst_n), - .CEA(1), - .AA(write_req_id), - .RDWENA(1'b1), - .CEB(deser_go), - .AB(fifo_in), - .RDWENB(1'b0), - .DOUTA(write_req_data), - .BWB({`AXI4_DATA_WIDTH{1'b1}}), - .DINB(deser_data) -); - -assign read_req_val = (pkt_state_buf[fifo_out] == WAITING) && (pkt_command[fifo_out] == READ) && bram_rdy[fifo_out]; -assign read_req_header = pkt_header[fifo_out]; -assign read_req_id = fifo_out; - -assign write_req_val = (pkt_state_buf[fifo_out] == WAITING) && (pkt_command[fifo_out] == WRITE) && bram_rdy[fifo_out]; -assign write_req_header = pkt_header[fifo_out]; -assign write_req_id = fifo_out; - -assign deser_rdy = (pkt_state_buf[fifo_in] == INVALID); - - -// -// GET_RESPONSE -// - -always @(posedge clk) begin - if(~rst_n) begin - preser_arb <= 1'b0; - end - else begin - preser_arb <= preser_arb + 1'b1; - end -end - -noc_axi4_bridge_sram_req noc_axi4_bridge_sram_req -( - .MEMCLK(clk), - .RESET_N(rst_n), - .CEA(1), - .AA(preser_arb ? write_resp_id : read_resp_id), - .RDWENA(1'b1), - .CEB(req_go), - .AB(fifo_out), - .RDWENB(1'b0), - .DOUTA(ser_header_f), - .BWB({`MSG_HEADER_WIDTH{1'b1}}), - .DINB(pkt_header[fifo_out]) -); - - -generate - for (i = 0; i < `NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT; i = i + 1) begin - always @(posedge clk) begin - if(~rst_n) begin - bram_rdy[i] <= 1; - end - else begin - bram_rdy[i] <= (req_go & (i == fifo_out)) ? 0 - : (write_resp_go & (i == write_resp_id)) ? 1 - : (read_resp_go & (i == read_resp_id)) ? 1 - : bram_rdy[i]; - end - end - end -endgenerate - -assign read_resp_rdy = ~preser_arb & preser_rdy; -assign write_resp_rdy = preser_arb & preser_rdy; - - -always @(posedge clk) begin - if(~rst_n) begin - ser_data_f <= 0; - ser_val_f <= 0; - ser_header_ff <= 0; - ser_val_ff <= 0; - ser_data_ff <= 0; - end - else begin - if (preser_rdy) begin - if (preser_arb) begin - ser_val_f <= write_resp_val; - ser_data_f <= 0; - end - else begin - ser_val_f <= read_resp_val; - ser_data_f <= read_resp_data; - end - ser_val_ff <= ser_val_f; - ser_data_ff <= ser_data_f; - ser_header_ff <= ser_header_f; - end - else begin - ser_val_f <= ser_val_f; - ser_data_f <= ser_data_f; - ser_val_ff <= ser_val_ff; - ser_data_ff <= ser_data_ff; - ser_header_ff <= ser_header_ff; - end - end -end - -assign ser_data = ser_data_ff; -assign ser_val = ser_val_ff; -assign ser_header = ser_header_ff; - - -/* -ila_buffer ila_buffer ( - .clk(clk), // input wire clk - - - .probe0(deser_header), // input wire [191:0] probe0 - .probe1(deser_data), // input wire [511:0] probe1 - .probe2(deser_val), // input wire [0:0] probe2 - .probe3(deser_rdy), // input wire [0:0] probe3 - .probe4(ser_header), // input wire [191:0] probe4 - .probe5(ser_data), // input wire [511:0] probe5 - .probe6(ser_val), // input wire [0:0] probe6 - .probe7(ser_rdy), // input wire [0:0] probe7 - .probe8(read_req_header), // input wire [191:0] probe8 - .probe9(read_req_id), // input wire [1:0] probe9 - .probe10(read_req_val), // input wire [0:0] probe10 - .probe11(read_req_rdy), // input wire [0:0] probe11 - .probe12(read_resp_data), // input wire [511:0] probe12 - .probe13(read_resp_id), // input wire [1:0] probe13 - .probe14(read_resp_val), // input wire [0:0] probe14 - .probe15(read_resp_rdy), // input wire [0:0] probe15 - .probe16(write_req_header), // input wire [191:0] probe16 - .probe17(write_req_id), // input wire [1:0] probe17 - .probe18(write_req_data), // input wire [511:0] probe18 - .probe19(write_req_val), // input wire [0:0] probe19 - .probe20(write_req_rdy), // input wire [0:0] probe20 - .probe21(write_resp_id), // input wire [1:0] probe21 - .probe22(write_resp_val), // input wire [0:0] probe22 - .probe23(write_resp_rdy), // input wire [0:0] probe23 - .probe24(fifo_in), // input wire [1:0] probe24 - .probe25(fifo_out), // input wire [1:0] probe25 - .probe26(preser_arb), // input wire [0:0] probe26 - .probe27(bram_rdy), // input wire [3:0] probe27 - .probe28(ser_data_f), // input wire [511:0] probe28 - .probe29(ser_header_f), // input wire [191:0] probe29 - .probe30(ser_val_f), // input wire [0:0] probe30 - .probe31(ser_data_ff), // input wire [511:0] probe31 - .probe32(ser_header_ff), // input wire [191:0] probe32 - .probe33(ser_val_ff), // input wire [0:0] probe33 - .probe34(rst_n) // input wire [0:0] probe34 -); - -reg [159:0] reqresp_count; -always @(posedge clk) begin - if (~rst_n) begin - reqresp_count <= 0; - end - else begin - reqresp_count <= ser_go & deser_go ? reqresp_count : - deser_go ? reqresp_count + 1 : - ser_go ? reqresp_count - 1 : - reqresp_count; - - end -end - -ila_axi_protocol_checker ila_axi_protocol_checker ( - .clk(clk), // input wire clk - - .probe0(rst_n), // input wire [0:0] probe0 - .probe1(reqresp_count) // input wire [159:0] probe1 -); -*/ - -endmodule diff --git a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_deser.v b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_deser.sv similarity index 61% rename from piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_deser.v rename to piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_deser.sv index cefd2df57..7b1970304 100644 --- a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_deser.v +++ b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_deser.sv @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // ========== Copyright Header Begin ============================================ // Copyright (c) 2019 Princeton University // All rights reserved. @@ -28,9 +29,12 @@ `include "mc_define.h" `include "define.tmp.h" `include "noc_axi4_bridge_define.vh" +import noc_axi4_bridge_pkg::*; -module noc_axi4_bridge_deser ( +module noc_axi4_bridge_deser #( + parameter SWAP_ENDIANESS = 0 // swap endianess, needed when used in conjunction with a little endian core like Ariane +) ( input clk, input rst_n, @@ -40,7 +44,7 @@ module noc_axi4_bridge_deser ( input phy_init_done, output [`MSG_HEADER_WIDTH-1:0] header_out, - output [`AXI4_DATA_WIDTH-1:0] data_out, + output reg [`AXI4_DATA_WIDTH-1:0] data_out, output out_val, input out_rdy ); @@ -54,7 +58,6 @@ localparam SEND = 3'd4; reg [`NOC_DATA_WIDTH-1:0] pkt_w1; reg [`NOC_DATA_WIDTH-1:0] pkt_w2; reg [`NOC_DATA_WIDTH-1:0] pkt_w3; -reg [`NOC_DATA_WIDTH-1:0] in_data_buf[`PAYLOAD_LEN-1:0]; //buffer for incomming packets reg [`MSG_LENGTH_WIDTH-1:0] remaining_flits; //flits remaining in current packet reg [2:0] state; @@ -62,29 +65,26 @@ assign flit_in_rdy = (state != SEND) & phy_init_done; wire flit_in_go = flit_in_val & flit_in_rdy; assign out_val = (state == SEND); -always @(posedge clk) begin - if(~rst_n) begin - state <= ACCEPT_W1; - remaining_flits <= 0; - pkt_w1 <= 0; - pkt_w2 <= 0; - pkt_w3 <= 0; - end - else begin +wire [`MSG_DATA_SIZE_WIDTH -1:0] dat_size_log; +noc_extractSize deser_extractSize( + .header (header_out), + .size_log(dat_size_log)); + +wire [`NOC_DATA_WIDTH -1:0] data_swapped = SWAP_ENDIANESS ? swapData(flit_in, dat_size_log) : + flit_in; +reg [$clog2(`PAYLOAD_LEN)-1 :0] dat_flit; +always @(posedge clk) + if(~rst_n) state <= ACCEPT_W1; + else case (state) ACCEPT_W1: begin if (flit_in_go) begin state <= ACCEPT_W2; remaining_flits <= flit_in[`MSG_LENGTH]-1; pkt_w1 <= flit_in; + dat_flit <= 0; + data_out <= `AXI4_DATA_WIDTH'h0; end - else begin - state <= state; - remaining_flits <= remaining_flits; - pkt_w1 <= pkt_w1; - end - pkt_w2 <= pkt_w2; - pkt_w3 <= pkt_w3; end ACCEPT_W2: begin if (flit_in_go) begin @@ -92,92 +92,46 @@ always @(posedge clk) begin remaining_flits <= remaining_flits - 1; pkt_w2 <= flit_in; end - else begin - state <= state; - remaining_flits <= remaining_flits; - pkt_w2 <= pkt_w2; - end - pkt_w1 <= pkt_w1; - pkt_w3 <= pkt_w3; end ACCEPT_W3: begin if (flit_in_go) begin - if (remaining_flits == 0) begin + if (remaining_flits == 0) state <= SEND; - remaining_flits <= 0; - end else begin state <= ACCEPT_DATA; remaining_flits <= remaining_flits - 1; end pkt_w3 <= flit_in; end - else begin - state <= state; - remaining_flits <= remaining_flits; - pkt_w3 <= pkt_w3; - end - pkt_w1 <= pkt_w1; - pkt_w2 <= pkt_w2; end ACCEPT_DATA: begin if (flit_in_go) begin - if (remaining_flits == 0) begin + if (remaining_flits == 0) state <= SEND; - remaining_flits <= 0; - end else begin state <= ACCEPT_DATA; remaining_flits <= remaining_flits - 1; + dat_flit <= dat_flit + 1; end end - else begin - state <= state; - remaining_flits <= remaining_flits; + if (flit_in_val) begin + data_out[dat_flit * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH] <= data_swapped; end - pkt_w1 <= pkt_w1; - pkt_w2 <= pkt_w2; - pkt_w3 <= pkt_w3; end SEND: begin - if (out_rdy) begin + if (out_rdy) state <= ACCEPT_W1; - remaining_flits <= 0; - pkt_w1 <= 0; - pkt_w2 <= 0; - pkt_w3 <= 0; - end - else begin - state <= state; - remaining_flits <= remaining_flits; - pkt_w1 <= pkt_w1; - pkt_w2 <= pkt_w2; - pkt_w3 <= pkt_w3; - end end - endcase // state - end -end - -genvar i; -generate - for (i = 0; i < `PAYLOAD_LEN; i = i + 1) begin - always @(posedge clk) begin - if(~rst_n) begin - in_data_buf[i] <= 0; - end - else begin - in_data_buf[i] <= (i == remaining_flits) & flit_in_val & (state == ACCEPT_DATA) ? flit_in - : (state == SEND) & out_rdy ? 0 - : in_data_buf[i]; + default: begin + // should never end up here + state <= 3'bX; + remaining_flits <= `MSG_LENGTH_WIDTH'bX; + pkt_w1 <= `NOC_DATA_WIDTH'bX; + pkt_w2 <= `NOC_DATA_WIDTH'bX; + pkt_w3 <= `NOC_DATA_WIDTH'bX; end - end - end -endgenerate - - + endcase // state assign header_out = {pkt_w3, pkt_w2, pkt_w1}; -assign data_out = {in_data_buf[0], in_data_buf[1], in_data_buf[2], in_data_buf[3], in_data_buf[4], in_data_buf[5], in_data_buf[6], in_data_buf[7]}; endmodule diff --git a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_read.sv b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_read.sv new file mode 100644 index 000000000..94b7a9648 --- /dev/null +++ b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_read.sv @@ -0,0 +1,202 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 +// ========== Copyright Header Begin ============================================ +// Copyright (c) 2019 Princeton University +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * Neither the name of Princeton University nor the +// names of its contributors may be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ========== Copyright Header End ============================================ + +`include "mc_define.h" +`include "define.tmp.h" +`include "noc_axi4_bridge_define.vh" +import noc_axi4_bridge_pkg::*; + + +module noc_axi4_bridge_read #( + parameter AXI4_DAT_WIDTH_USED = `AXI4_DATA_WIDTH // actually used AXI Data width (down converted if needed) +) ( + // Clock + Reset + input wire clk, + input wire rst_n, + + // NOC interface + input wire req_val, + input wire [`AXI4_ADDR_WIDTH -1:0] req_addr, + input wire [`MSG_DATA_SIZE_WIDTH-1:0] req_size_log, + input wire [`AXI4_ID_WIDTH -1:0] req_id, + output wire req_rdy, + + output wire resp_val, + output wire [`AXI4_ID_WIDTH -1:0] resp_id, + output reg [`AXI4_DATA_WIDTH-1:0] resp_data, + input wire resp_rdy, + + // AXI Read Interface + output reg [`AXI4_ID_WIDTH -1:0] m_axi_arid, + output reg [`AXI4_ADDR_WIDTH -1:0] m_axi_araddr, + output reg [`AXI4_LEN_WIDTH -1:0] m_axi_arlen, + output reg [`AXI4_SIZE_WIDTH -1:0] m_axi_arsize, + output wire [`AXI4_BURST_WIDTH -1:0] m_axi_arburst, + output wire m_axi_arlock, + output wire [`AXI4_CACHE_WIDTH -1:0] m_axi_arcache, + output wire [`AXI4_PROT_WIDTH -1:0] m_axi_arprot, + output wire [`AXI4_QOS_WIDTH -1:0] m_axi_arqos, + output wire [`AXI4_REGION_WIDTH -1:0] m_axi_arregion, + output wire [`AXI4_USER_WIDTH -1:0] m_axi_aruser, + output wire m_axi_arvalid, + input wire m_axi_arready, + + input wire [`AXI4_ID_WIDTH -1:0] m_axi_rid, + input wire [AXI4_DAT_WIDTH_USED-1:0] m_axi_rdata, + input wire [`AXI4_RESP_WIDTH -1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire [`AXI4_USER_WIDTH -1:0] m_axi_ruser, + input wire m_axi_rvalid, + output wire m_axi_rready +); + + +localparam IDLE = 1'b0; +localparam GOT_REQ = 1'b1; +localparam GOT_RESP = 1'b1; + +wire [`AXI4_ADDR_WIDTH-1:0]addr_paddings = `AXI4_ADDR_WIDTH'b0; + +//============================================================================== +// Tie constant outputs in axi4 +//============================================================================== + + assign m_axi_arburst = `AXI4_BURST_WIDTH'b01; // INCR address in bursts + assign m_axi_arlock = 1'b0; // Do not use locks + assign m_axi_arcache = `AXI4_CACHE_WIDTH'b11; // Non-cacheable bufferable requests + assign m_axi_arprot = `AXI4_PROT_WIDTH'b0; // Data access, non-secure access, unpriveleged access + assign m_axi_arqos = `AXI4_QOS_WIDTH'b0; // Do not use qos + assign m_axi_arregion = `AXI4_REGION_WIDTH'b0; // Do not use regions + assign m_axi_aruser = `AXI4_USER_WIDTH'b0; // Do not use user field + +// outbound requests +wire m_axi_argo = m_axi_arvalid & m_axi_arready; +wire req_go = req_val & req_rdy; + +reg req_state; + +assign req_rdy = (req_state == IDLE); +assign m_axi_arvalid = (req_state == GOT_REQ); +wire signed [`MSG_DATA_SIZE_WIDTH:0] burst_len_log = $signed({1'b0, req_size_log}) - $clog2(AXI4_DAT_WIDTH_USED/8); + +always @(posedge clk) + if(~rst_n) begin + req_state <= IDLE; + end else + case (req_state) + IDLE: if (req_go) begin + req_state <= GOT_REQ; + m_axi_araddr <= req_addr; + m_axi_arlen <= (1 << clip2zer(burst_len_log)) - 1; + m_axi_arsize <= (burst_len_log < 0) ? req_size_log : $clog2(AXI4_DAT_WIDTH_USED/8); + m_axi_arid <= req_id; + end + GOT_REQ: if (m_axi_argo) + req_state <= IDLE; + default : begin + // should never end up here + req_state <= 1'bX; + m_axi_araddr <= `AXI4_ADDR_WIDTH'bX; + m_axi_arlen <= `AXI4_LEN_WIDTH'bX; + m_axi_arsize <= `AXI4_SIZE_WIDTH'bX; + m_axi_arid <= `AXI4_ID_WIDTH'bX; + end + endcase + +// inbound responses +reg [`AXI4_ID_WIDTH-1:0] resp_id_f; +wire resp_go = resp_val & resp_rdy; +wire m_axi_rgo = m_axi_rvalid & m_axi_rready; + +reg resp_state; + +assign resp_val = (resp_state == GOT_RESP); +assign m_axi_rready = (resp_state == IDLE); + +localparam MAX_BURST_LEN = `AXI4_DATA_WIDTH / AXI4_DAT_WIDTH_USED; +reg [clip2zer($clog2(MAX_BURST_LEN)-1) :0] burst_count; +always @(posedge clk) + if(~rst_n) begin + resp_id_f <= 0; + resp_state <= IDLE; + resp_data <= 0; + burst_count <= 0; + end else + case (resp_state) + IDLE: if (m_axi_rgo) begin + if (m_axi_rlast) begin + resp_state <= GOT_RESP; + burst_count <= 0; + end else if (MAX_BURST_LEN > 1) burst_count <= burst_count + 1; + resp_id_f <= m_axi_rid; + resp_data[{burst_count,{$clog2(AXI4_DAT_WIDTH_USED){1'b0}}} +: AXI4_DAT_WIDTH_USED] <= m_axi_rdata; + end + GOT_RESP: if (resp_go) + resp_state <= IDLE; + default : begin + // should never end up here + resp_id_f <= 0; + resp_state <= IDLE; + resp_data <= 0; + end + endcase + +// process data here +assign resp_id = resp_id_f; + +/* +ila_read ila_read( + .clk(clk), // input wire clk + + + .probe0(rst_n), // input wire [0:0] probe0 + .probe1(uart_boot_en), // input wire [0:0] probe1 + .probe2(req_val), // input wire [0:0] probe2 + .probe3(req_header), // input wire [191:0] probe3 + .probe4(req_id), // input wire [1:0] probe4 + .probe5(req_rdy), // input wire [0:0] probe5 + .probe6(resp_val), // input wire [0:0] probe6 + .probe7(resp_id), // input wire [1:0] probe7 + .probe8(resp_data), // input wire [511:0] probe8 + .probe9(resp_rdy), // input wire [0:0] probe9 + .probe10(m_axi_arid), // input wire [15:0] probe10 + .probe11(m_axi_araddr), // input wire [63:0] probe11 + .probe12(m_axi_arvalid), // input wire [0:0] probe12 + .probe13(m_axi_arready), // input wire [0:0] probe13 + .probe14(m_axi_rid), // input wire [15:0] probe14 + .probe15(m_axi_rdata), // input wire [511:0] probe15 + .probe16(m_axi_rvalid), // input wire [0:0] probe16 + .probe17(m_axi_rready), // input wire [0:0] probe17 + .probe18(req_state), // input wire [0:0] probe18 + .probe19(req_header_f), // input wire [191:0] probe19 + .probe20(req_id_f), // input wire [1:0] probe20 + .probe21(resp_id_f), // input wire [1:0] probe21 + .probe22(resp_state), // input wire [1:0] probe22 + .probe23(data_offseted) // input wire [511:0] probe23 +);*/ +endmodule diff --git a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_read.v b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_read.v deleted file mode 100644 index bc00e52ec..000000000 --- a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_read.v +++ /dev/null @@ -1,354 +0,0 @@ -// ========== Copyright Header Begin ============================================ -// Copyright (c) 2019 Princeton University -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// * Neither the name of Princeton University nor the -// names of its contributors may be used to endorse or promote products -// derived from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY -// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ========== Copyright Header End ============================================ - -`include "mc_define.h" -`include "define.tmp.h" -`include "noc_axi4_bridge_define.vh" - - -module noc_axi4_bridge_read ( - // Clock + Reset - input wire clk, - input wire rst_n, - input wire uart_boot_en, - - // NOC interface - input wire req_val, - input wire [`MSG_HEADER_WIDTH-1:0] req_header, - input wire [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] req_id, - output wire req_rdy, - - output wire resp_val, - output wire [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] resp_id, - output reg [`AXI4_DATA_WIDTH-1:0] resp_data, - input wire resp_rdy, - - // AXI Read Interface - output wire [`AXI4_ID_WIDTH -1:0] m_axi_arid, - output wire [`AXI4_ADDR_WIDTH -1:0] m_axi_araddr, - output wire [`AXI4_LEN_WIDTH -1:0] m_axi_arlen, - output wire [`AXI4_SIZE_WIDTH -1:0] m_axi_arsize, - output wire [`AXI4_BURST_WIDTH -1:0] m_axi_arburst, - output wire m_axi_arlock, - output wire [`AXI4_CACHE_WIDTH -1:0] m_axi_arcache, - output wire [`AXI4_PROT_WIDTH -1:0] m_axi_arprot, - output wire [`AXI4_QOS_WIDTH -1:0] m_axi_arqos, - output wire [`AXI4_REGION_WIDTH -1:0] m_axi_arregion, - output wire [`AXI4_USER_WIDTH -1:0] m_axi_aruser, - output wire m_axi_arvalid, - input wire m_axi_arready, - - input wire [`AXI4_ID_WIDTH -1:0] m_axi_rid, - input wire [`AXI4_DATA_WIDTH -1:0] m_axi_rdata, - input wire [`AXI4_RESP_WIDTH -1:0] m_axi_rresp, - input wire m_axi_rlast, - input wire [`AXI4_USER_WIDTH -1:0] m_axi_ruser, - input wire m_axi_rvalid, - output wire m_axi_rready -); - - -localparam IDLE = 2'd0; -localparam GOT_REQ = 2'd1; -localparam GOT_RESP = 2'd2; -localparam SEND_RESP = 2'd3; - -wire [`AXI4_ADDR_WIDTH-1:0]addr_paddings = `AXI4_ADDR_WIDTH'b0; - -//============================================================================== -// Tie constant outputs in axi4 -//============================================================================== - - assign m_axi_arlen = `AXI4_LEN_WIDTH'b0; // Use only length-1 bursts - assign m_axi_arsize = `AXI4_SIZE_WIDTH'b110; // Always transfer 64 bytes - assign m_axi_arburst = `AXI4_BURST_WIDTH'b01; // fixed address in bursts (doesn't matter cause we use length-1 bursts) - assign m_axi_arlock = 1'b0; // Do not use locks - assign m_axi_arcache = `AXI4_CACHE_WIDTH'b11; // Non-cacheable bufferable requests - assign m_axi_arprot = `AXI4_PROT_WIDTH'b0; // Data access, non-secure access, unpriveleged access - assign m_axi_arqos = `AXI4_QOS_WIDTH'b0; // Do not use qos - assign m_axi_arregion = `AXI4_REGION_WIDTH'b0; // Do not use regions - assign m_axi_aruser = `AXI4_USER_WIDTH'b0; // Do not use user field - -// outbound requests -wire m_axi_argo = m_axi_arvalid & m_axi_arready; -wire req_go = req_val & req_rdy; - -reg req_state; -reg [`MSG_HEADER_WIDTH-1:0] req_header_f; -reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] req_id_f; - -assign req_rdy = (req_state == IDLE); -assign m_axi_arvalid = (req_state == GOT_REQ); - -always @(posedge clk) begin - if(~rst_n) begin - req_header_f <= 0; - req_id_f <= 0; - req_state <= IDLE; - end else begin - case (req_state) - IDLE: begin - req_state <= req_go ? GOT_REQ : req_state; - req_header_f <= req_go ? req_header : req_header_f; - req_id_f <= req_go ? req_id : req_id_f; - end - GOT_REQ: begin - req_state <= m_axi_argo ? IDLE : req_state; - req_header_f <= m_axi_argo ? 0 : req_header_f; - req_id_f <= m_axi_argo ? 0 : req_id_f; - end - default : begin - // should never end up here - req_header_f <= 0; - req_id_f <= 0; - req_state <= IDLE; - end - endcase - end -end - - -// Process information here -assign m_axi_arid = {{`AXI4_ID_WIDTH-`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE{1'b0}}, req_id_f}; - -wire [`PHY_ADDR_WIDTH-1:0] virt_addr = req_header_f[`MSG_ADDR]; -wire [`AXI4_ADDR_WIDTH-1:0] phys_addr; - -// If running uart tests - we need to do address translation -`ifdef PITONSYS_UART_BOOT -storage_addr_trans_unified #( -`else -storage_addr_trans #( -`endif -.STORAGE_ADDR_WIDTH(`AXI4_ADDR_WIDTH) -) cpu_mig_waddr_translator ( - .va_byte_addr (virt_addr ), - .storage_addr_out (phys_addr ) -); - - -// Have to save request size and offset to process data later -reg [6:0] size[`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0]; -reg [5:0] offset[`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0]; -reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] resp_id_f; -wire resp_go; -wire uncacheable = (virt_addr[`PHY_ADDR_WIDTH-1]) - || (req_header_f[`MSG_TYPE] == `MSG_TYPE_NC_LOAD_REQ); - -generate begin - genvar i; - for (i = 0; i < `NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT; i = i + 1) begin - always @(posedge clk) begin - if(~rst_n) begin - size[i] <= 7'b0; - offset[i] <= 6'b0; - end - else begin - if ((i == req_id_f) && m_axi_argo) begin - if (uncacheable) begin - offset[i] <= virt_addr[5:0]; - case (req_header_f[`MSG_DATA_SIZE]) - `MSG_DATA_SIZE_0B: begin - size[i] <= 7'd0; - end - `MSG_DATA_SIZE_1B: begin - size[i] <= 7'd1; - end - `MSG_DATA_SIZE_2B: begin - size[i] <= 7'd2; - end - `MSG_DATA_SIZE_4B: begin - size[i] <= 7'd4; - end - `MSG_DATA_SIZE_8B: begin - size[i] <= 7'd8; - end - `MSG_DATA_SIZE_16B: begin - size[i] <= 7'd16; - end - `MSG_DATA_SIZE_32B: begin - size[i] <= 7'd32; - end - `MSG_DATA_SIZE_64B: begin - size[i] <= 7'd64; - end - default: begin - // should never end up here - size[i] <= 7'b0; - end - endcase - end - else begin - offset[i] <= 6'b0; - size[i] <= 7'd64; - end - end - else if ((i == resp_id_f) & resp_go) begin - size[i] <= 7'b0; - offset[i] <= 7'b0; - end - else begin - size[i] <= size[i]; - offset[i] <= offset[i]; - end - end - end - end -end -endgenerate - -wire [`AXI4_ADDR_WIDTH-1:0] addr = uart_boot_en ? {phys_addr[`AXI4_ADDR_WIDTH-4:0], 3'b0} : virt_addr; -assign m_axi_araddr = {addr[`AXI4_ADDR_WIDTH-1:6], 6'b0}; - - - -// inbound responses - -wire m_axi_rgo = m_axi_rvalid & m_axi_rready; -assign resp_go = resp_val & resp_rdy; - -reg [1:0] resp_state; - -assign resp_val = (resp_state == SEND_RESP); -assign m_axi_rready = (resp_state == IDLE); - -always @(posedge clk) begin - if(~rst_n) begin - resp_id_f <= 0; - resp_state <= IDLE; - end else begin - case (resp_state) - IDLE: begin - resp_state <= m_axi_rgo ? GOT_RESP : resp_state; - resp_id_f <= m_axi_rgo ? m_axi_rid : resp_id_f; - end - GOT_RESP: begin - resp_state <= SEND_RESP; - resp_id_f <= resp_id_f; - end - SEND_RESP: begin - resp_state <= resp_go ? IDLE : resp_state; - resp_id_f <= resp_go ? 0 : resp_id_f; - end - default : begin - // should never end up here - resp_id_f <= 0; - resp_state <= IDLE; - end - endcase - end -end - -// process data here -assign resp_id = resp_id_f; - - -reg [`AXI4_DATA_WIDTH-1:0] data_offseted; - -always @(posedge clk) begin - if(~rst_n) begin - data_offseted <= 0; - end - else begin - data_offseted <= m_axi_rgo ? (m_axi_rdata >> (8*offset[m_axi_rid])) : 0; - end -end - -always @(posedge clk) begin - if (~rst_n) begin - resp_data <= {`AXI4_DATA_WIDTH{1'b0}}; - end - else begin - case (resp_state) - GOT_RESP: begin - case (size[resp_id_f]) - 7'd0: begin - resp_data <= {`AXI4_DATA_WIDTH{1'b0}}; - end - 7'd1: begin - resp_data <= {`AXI4_DATA_WIDTH/8{data_offseted[7:0]}}; - end - 7'd2: begin - resp_data <= {`AXI4_DATA_WIDTH/16{data_offseted[15:0]}}; - end - 7'd4: begin - resp_data <= {`AXI4_DATA_WIDTH/32{data_offseted[31:0]}}; - end - 7'd8: begin - resp_data <= {`AXI4_DATA_WIDTH/64{data_offseted[63:0]}}; - end - 7'd16: begin - resp_data <= {`AXI4_DATA_WIDTH/128{data_offseted[127:0]}}; - end - 7'd32: begin - resp_data <= {`AXI4_DATA_WIDTH/256{data_offseted[255:0]}}; - end - default: begin - resp_data <= {`AXI4_DATA_WIDTH/512{data_offseted[511:0]}}; - end - endcase - end - SEND_RESP: begin - resp_data <= resp_go ? {`AXI4_DATA_WIDTH{1'b0}} : resp_data; - end - default: begin - resp_data <= {`AXI4_DATA_WIDTH{1'b0}}; - end - endcase // resp_state - end -end -/* -ila_read ila_read( - .clk(clk), // input wire clk - - - .probe0(rst_n), // input wire [0:0] probe0 - .probe1(uart_boot_en), // input wire [0:0] probe1 - .probe2(req_val), // input wire [0:0] probe2 - .probe3(req_header), // input wire [191:0] probe3 - .probe4(req_id), // input wire [1:0] probe4 - .probe5(req_rdy), // input wire [0:0] probe5 - .probe6(resp_val), // input wire [0:0] probe6 - .probe7(resp_id), // input wire [1:0] probe7 - .probe8(resp_data), // input wire [511:0] probe8 - .probe9(resp_rdy), // input wire [0:0] probe9 - .probe10(m_axi_arid), // input wire [15:0] probe10 - .probe11(m_axi_araddr), // input wire [63:0] probe11 - .probe12(m_axi_arvalid), // input wire [0:0] probe12 - .probe13(m_axi_arready), // input wire [0:0] probe13 - .probe14(m_axi_rid), // input wire [15:0] probe14 - .probe15(m_axi_rdata), // input wire [511:0] probe15 - .probe16(m_axi_rvalid), // input wire [0:0] probe16 - .probe17(m_axi_rready), // input wire [0:0] probe17 - .probe18(req_state), // input wire [0:0] probe18 - .probe19(req_header_f), // input wire [191:0] probe19 - .probe20(req_id_f), // input wire [1:0] probe20 - .probe21(resp_id_f), // input wire [1:0] probe21 - .probe22(resp_state), // input wire [1:0] probe22 - .probe23(data_offseted) // input wire [511:0] probe23 -);*/ -endmodule diff --git a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.v b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.sv similarity index 72% rename from piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.v rename to piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.sv index baa5a9dbb..188dc6ea9 100644 --- a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.v +++ b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.sv @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // ========== Copyright Header Begin ============================================ // Copyright (c) 2019 Princeton University // All rights reserved. @@ -28,9 +29,12 @@ `include "mc_define.h" `include "define.tmp.h" `include "noc_axi4_bridge_define.vh" +import noc_axi4_bridge_pkg::*; -module noc_axi4_bridge_ser( +module noc_axi4_bridge_ser #( + parameter SWAP_ENDIANESS = 0 // swap endianess, needed when used in conjunction with a little endian core like Ariane +) ( input clk, input rst_n, @@ -39,71 +43,50 @@ module noc_axi4_bridge_ser( input in_val, output in_rdy, - output reg [`NOC_DATA_WIDTH-1:0] flit_out, + output [`NOC_DATA_WIDTH-1:0] flit_out, output flit_out_val, input flit_out_rdy ); // states +reg [1:0] state; localparam ACCEPT = 2'd0; localparam SEND_HEADER = 2'd1; localparam SEND_DATA = 2'd2; reg [`AXI4_DATA_WIDTH-1:0] data_in_f; reg [`NOC_DATA_WIDTH-1:0] resp_header; +reg [`MSG_DATA_SIZE_WIDTH -1:0] dat_size_log_f; +reg [`NOC_DATA_WIDTH -1:0] data_swapped; wire in_go = in_val & in_rdy; wire flit_out_go = flit_out_val & flit_out_rdy; -always @(posedge clk) begin - if(~rst_n) begin - data_in_f <= {`AXI4_DATA_WIDTH{1'b0}}; - end - else if (in_go) begin - data_in_f <= data_in; - end - else begin - data_in_f <= data_in_f; - end -end - -reg [1:0] state; reg [`MSG_LENGTH_WIDTH-1:0] remaining_flits; assign flit_out_val = (state == SEND_HEADER) || (state == SEND_DATA); assign in_rdy = (state == ACCEPT); - -always @(posedge clk) begin - if(~rst_n) begin - state <= ACCEPT; - remaining_flits <= `MSG_LENGTH_WIDTH'b0; - end - else begin +always @(posedge clk) + if(~rst_n) state <= ACCEPT; + else case (state) ACCEPT: begin state <= in_val ? SEND_HEADER : ACCEPT; - remaining_flits <= `MSG_LENGTH_WIDTH'b0; end SEND_HEADER: begin if (flit_out_rdy) begin if (resp_header[`MSG_LENGTH] == 0) begin state <= ACCEPT; - remaining_flits <= 0; end else begin state <= SEND_DATA; remaining_flits <= resp_header[`MSG_LENGTH]; end end - else begin - state <= state; - remaining_flits <= remaining_flits; - end end SEND_DATA: begin if (remaining_flits == `MSG_LENGTH_WIDTH'b1) begin state <= flit_out_rdy ? ACCEPT : SEND_DATA; - remaining_flits <= 0; end else begin state <= SEND_DATA; @@ -112,20 +95,19 @@ always @(posedge clk) begin end default: begin // should never end up here - state <= ACCEPT; - remaining_flits <= `MSG_LENGTH_WIDTH'b0; + state <= 2'bX; + remaining_flits <= `MSG_LENGTH_WIDTH'bX; end endcase // state - end -end - -always @(posedge clk) begin - if (~rst_n) begin - resp_header <= `NOC_DATA_WIDTH'b0; - end - else begin - case (state) - ACCEPT: begin + +wire [`MSG_DATA_SIZE_WIDTH -1:0] dat_size_log; +noc_extractSize ser_extractSize( + .header (header_in), + .size_log(dat_size_log)); + +wire [`MSG_LENGTH_WIDTH-1:0] dat_payload_len = 1 << clip2zer($signed({1'b0,dat_size_log}) - $clog2(`NOC_DATA_WIDTH/8)); + +always @(posedge clk) if (in_go) begin resp_header[`MSG_DST_CHIPID ] <= header_in[`MSG_SRC_CHIPID]; resp_header[`MSG_DST_X ] <= header_in[`MSG_SRC_X ]; @@ -133,6 +115,8 @@ always @(posedge clk) begin resp_header[`MSG_DST_FBITS ] <= header_in[`MSG_SRC_FBITS ]; resp_header[`MSG_MSHRID ] <= header_in[`MSG_MSHRID ]; resp_header[`MSG_OPTIONS_1 ] <= {`MSG_OPTIONS_1_WIDTH{1'b0}}; + dat_size_log_f <= dat_size_log; + data_in_f <= data_in; case (header_in[`MSG_TYPE]) `MSG_TYPE_LOAD_MEM: begin resp_header[`MSG_TYPE ] <= `MSG_TYPE_LOAD_MEM_ACK; @@ -144,7 +128,7 @@ always @(posedge clk) begin end `MSG_TYPE_NC_LOAD_REQ: begin resp_header[`MSG_TYPE ] <= `MSG_TYPE_NC_LOAD_MEM_ACK; - resp_header[`MSG_LENGTH ] <= `PAYLOAD_LEN; + resp_header[`MSG_LENGTH ] <= dat_payload_len; // flexible data packet length, required for `define L2_SEND_NC_REQ end `MSG_TYPE_NC_STORE_REQ: begin resp_header[`MSG_TYPE ] <= `MSG_TYPE_NC_STORE_MEM_ACK; @@ -152,49 +136,22 @@ always @(posedge clk) begin end default: begin // shouldn't end up herere - resp_header[`MSG_TYPE ] <= `MSG_TYPE_WIDTH'b0; - resp_header[`MSG_LENGTH ] <= 0; + resp_header[`MSG_TYPE ] <= `MSG_TYPE_WIDTH'bX; + resp_header[`MSG_LENGTH ] <= `MSG_LENGTH_WIDTH'bX; end endcase // header_in[`MSG_TYPE] end - else begin - resp_header <= resp_header; + else if (flit_out_go) begin + data_in_f <= data_in_f >> `NOC_DATA_WIDTH; + data_swapped <= SWAP_ENDIANESS ? swapData(data_in_f, dat_size_log_f) : + data_in_f; end - end - SEND_HEADER: begin - if (flit_out_go) begin - resp_header <= `NOC_DATA_WIDTH'b0; - end - else begin - resp_header <= resp_header; - end - end - SEND_DATA: begin - resp_header <= resp_header; - end - default: begin - //shouldnt end up here - resp_header <= `NOC_DATA_WIDTH'b0; - end - endcase //state - end -end - -always @(*) begin - case (state) - ACCEPT: begin - flit_out = `NOC_DATA_WIDTH'b0; - end - SEND_HEADER: begin - flit_out = resp_header; - end - SEND_DATA: begin - flit_out = data_in_f >> (64 * (`PAYLOAD_LEN - remaining_flits)); - end - default: begin - flit_out = `NOC_DATA_WIDTH'b0; - end - endcase // state - -end + +wire [`MSG_DST_CHIPID_WIDTH-1:0] resp_dst_chipid = resp_header[`MSG_DST_CHIPID]; +wire [`MSG_DST_X_WIDTH -1:0] resp_dst_x = resp_header[`MSG_DST_X]; +wire [`MSG_DST_Y_WIDTH -1:0] resp_dst_y = resp_header[`MSG_DST_Y]; +wire [`MSG_DST_FBITS_WIDTH -1:0] resp_dst_fbits = resp_header[`MSG_DST_FBITS]; + +assign flit_out = (state == SEND_HEADER) ? resp_header : data_swapped; + endmodule diff --git a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_write.v b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_write.sv similarity index 53% rename from piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_write.v rename to piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_write.sv index 22c271bb5..bf9c33cb8 100644 --- a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_write.v +++ b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_write.sv @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // ========== Copyright Header Begin ============================================ // Copyright (c) 2019 Princeton University // All rights reserved. @@ -28,30 +29,34 @@ `include "mc_define.h" `include "define.tmp.h" `include "noc_axi4_bridge_define.vh" +import noc_axi4_bridge_pkg::*; -module noc_axi4_bridge_write ( +module noc_axi4_bridge_write #( + parameter AXI4_DAT_WIDTH_USED = `AXI4_DATA_WIDTH // actually used AXI Data width (down converted if needed) +) ( // Clock + Reset input wire clk, input wire rst_n, - input wire uart_boot_en, // NOC interface input wire req_val, - input wire [`MSG_HEADER_WIDTH-1:0] req_header, - input wire [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] req_id, + input wire [`AXI4_ADDR_WIDTH -1:0] req_addr, + input wire [`MSG_DATA_SIZE_WIDTH-1:0] req_size_log, + input wire [`AXI4_ID_WIDTH -1:0] req_id, input wire [`AXI4_DATA_WIDTH-1:0] req_data, + input wire [`AXI4_STRB_WIDTH-1:0] req_strb, output wire req_rdy, output wire resp_val, - output wire [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] resp_id, + output wire [`AXI4_ID_WIDTH -1:0] resp_id, input wire resp_rdy, // AXI write interface - output wire [`AXI4_ID_WIDTH -1:0] m_axi_awid, - output wire [`AXI4_ADDR_WIDTH -1:0] m_axi_awaddr, - output wire [`AXI4_LEN_WIDTH -1:0] m_axi_awlen, - output wire [`AXI4_SIZE_WIDTH -1:0] m_axi_awsize, + output reg [`AXI4_ID_WIDTH -1:0] m_axi_awid, + output reg [`AXI4_ADDR_WIDTH -1:0] m_axi_awaddr, + output reg [`AXI4_LEN_WIDTH -1:0] m_axi_awlen, + output reg [`AXI4_SIZE_WIDTH -1:0] m_axi_awsize, output wire [`AXI4_BURST_WIDTH -1:0] m_axi_awburst, output wire m_axi_awlock, output wire [`AXI4_CACHE_WIDTH -1:0] m_axi_awcache, @@ -63,8 +68,8 @@ module noc_axi4_bridge_write ( input wire m_axi_awready, output wire [`AXI4_ID_WIDTH -1:0] m_axi_wid, - output wire [`AXI4_DATA_WIDTH -1:0] m_axi_wdata, - output wire [`AXI4_STRB_WIDTH -1:0] m_axi_wstrb, + output wire [AXI4_DAT_WIDTH_USED-1:0] m_axi_wdata, + output wire [AXI4_DAT_WIDTH_USED/8-1:0] m_axi_wstrb, output wire m_axi_wlast, output wire [`AXI4_USER_WIDTH -1:0] m_axi_wuser, output wire m_axi_wvalid, @@ -78,20 +83,17 @@ module noc_axi4_bridge_write ( ); -localparam IDLE = 3'd0; -localparam GOT_REQ = 3'd1; -localparam PREP_REQ = 3'd2; -localparam SENT_AW = 3'd3; -localparam SENT_W = 3'd4; -localparam GOT_RESP = 3'd1; +localparam IDLE = 2'h0; +localparam GOT_REQ = 2'h1; +localparam SENT_AW = 2'h2; +localparam SENT_W = 2'h3; +localparam GOT_RESP = 2'b1; //============================================================================== // Tie constant outputs in axi4 //============================================================================== - assign m_axi_awlen = `AXI4_LEN_WIDTH'b0; // Use only length-1 bursts - assign m_axi_awsize = `AXI4_SIZE_WIDTH'b110; // Always transfer 64 bytes - assign m_axi_awburst = `AXI4_BURST_WIDTH'b01; // fixed address in bursts (doesn't matter cause we use length-1 bursts) + assign m_axi_awburst = `AXI4_BURST_WIDTH'b01; // INCR address in bursts assign m_axi_awlock = 1'b0; // Do not use locks assign m_axi_awcache = `AXI4_CACHE_WIDTH'b11; // Non-cacheable bufferable requests assign m_axi_awprot = `AXI4_PROT_WIDTH'b0; // Data access, non-secure access, unpriveleged access @@ -105,176 +107,106 @@ wire [`AXI4_ADDR_WIDTH-1:0] addr_paddings = `AXI4_ADDR_WIDTH'b0; // outbound requests wire m_axi_awgo = m_axi_awvalid & m_axi_awready; wire m_axi_wgo = m_axi_wvalid & m_axi_wready; +wire m_axi_lwgo = m_axi_wgo & m_axi_wlast; wire req_go = req_val & req_rdy; -assign m_axi_wlast = m_axi_wvalid; -reg [2:0] req_state; -reg [`MSG_HEADER_WIDTH-1:0] req_header_f; -reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] req_id_f; +reg [1:0] req_state; reg [`AXI4_DATA_WIDTH-1:0] req_data_f; assign req_rdy = (req_state == IDLE); -assign m_axi_awvalid = (req_state == PREP_REQ) || (req_state == SENT_W); -assign m_axi_wvalid = (req_state == PREP_REQ) || (req_state == SENT_AW); +assign m_axi_awvalid = (req_state == GOT_REQ) || (req_state == SENT_W); +assign m_axi_wvalid = (req_state == GOT_REQ) || (req_state == SENT_AW); +wire signed [`MSG_DATA_SIZE_WIDTH:0] burst_len_log = $signed({1'b0, req_size_log}) - $clog2(AXI4_DAT_WIDTH_USED/8); +wire [`AXI4_LEN_WIDTH -1:0] burst_len = (1 << clip2zer(burst_len_log)) - 1; -always @(posedge clk) begin +always @(posedge clk) if(~rst_n) begin - req_header_f <= 0; - req_id_f <= 0; req_state <= IDLE; - req_data_f <= 0; - end else begin + end else case (req_state) - IDLE: begin - req_state <= req_go ? GOT_REQ : req_state; - req_header_f <= req_go ? req_header : req_header_f; - req_id_f <= req_go ? req_id : req_id_f; - req_data_f <= req_data_f; + IDLE: if (req_go) begin + req_state <= GOT_REQ; + m_axi_awaddr <= req_addr; + m_axi_awlen <= burst_len; + m_axi_awsize <= (burst_len_log < 0) ? req_size_log : $clog2(AXI4_DAT_WIDTH_USED/8); + m_axi_awid <= req_id; end - GOT_REQ: begin - req_state <= PREP_REQ; - req_header_f <= req_header_f; - req_id_f <= req_id_f; - req_data_f <= req_data; // get data one cycle later because of bram in buffer - end - PREP_REQ: begin - req_state <= (m_axi_awgo & m_axi_wgo) ? IDLE : m_axi_awgo ? SENT_AW : m_axi_wgo ? SENT_W : req_state; - req_header_f <= (m_axi_awgo & m_axi_wgo) ? 0 : req_header_f; - req_id_f <= (m_axi_awgo & m_axi_wgo) ? 0 : req_id_f; - req_data_f <= (m_axi_awgo & m_axi_wgo) ? 0 : req_data_f; - end - SENT_AW: begin - req_state <= m_axi_wgo ? IDLE : req_state; - req_header_f <= m_axi_wgo ? 0 : req_header_f; - req_id_f <= m_axi_wgo ? 0 : req_id_f; - req_data_f <= m_axi_wgo ? 0 : req_data_f; - end - SENT_W: begin - req_state <= m_axi_awgo ? IDLE : req_state; - req_header_f <= m_axi_awgo ? 0 : req_header_f; - req_id_f <= m_axi_awgo ? 0 : req_id_f; - req_data_f <= m_axi_awgo ? 0 : req_data_f; - end - default : begin - req_header_f <= 0; - req_id_f <= 0; + GOT_REQ: + req_state <= (m_axi_awgo & m_axi_lwgo) ? IDLE : + m_axi_awgo ? SENT_AW : + m_axi_lwgo ? SENT_W : req_state; + SENT_AW: if (m_axi_lwgo) req_state <= IDLE; - req_data_f <= 0; + SENT_W: if (m_axi_awgo) + req_state <= IDLE; + default : begin + // should never end up here + req_state <= 2'bX; + m_axi_awaddr <= `AXI4_ADDR_WIDTH'bX; + m_axi_awlen <= `AXI4_LEN_WIDTH'bX; + m_axi_awsize <= `AXI4_SIZE_WIDTH'bX; + m_axi_awid <= `AXI4_ID_WIDTH'bX; end endcase - end -end - -// Process information here -assign m_axi_awid = {{`AXI4_ID_WIDTH-`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE{1'b0}}, req_id_f}; -assign m_axi_wid = {{`AXI4_ID_WIDTH-`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE{1'b0}}, req_id_f}; - - -wire [`PHY_ADDR_WIDTH-1:0] virt_addr = req_header_f[`MSG_ADDR]; -wire [`AXI4_ADDR_WIDTH-1:0] phys_addr; -wire uncacheable = (virt_addr[`PHY_ADDR_WIDTH-1]) - || (req_header_f[`MSG_TYPE] == `MSG_TYPE_NC_STORE_REQ); - -// If running uart tests - we need to do address translation -`ifdef PITONSYS_UART_BOOT -storage_addr_trans_unified #( -`else -storage_addr_trans #( -`endif -.STORAGE_ADDR_WIDTH(`AXI4_ADDR_WIDTH) -) cpu_mig_raddr_translator ( - .va_byte_addr (virt_addr ), - .storage_addr_out (phys_addr ) -); - -reg [`AXI4_STRB_WIDTH-1:0] strb_before_offset; -reg [5:0] offset; -reg [`AXI4_ADDR_WIDTH-1:0] addr; -always @(posedge clk) begin - if (~rst_n) begin - offset <= 6'b0; - strb_before_offset <= `AXI4_STRB_WIDTH'b0; - addr <= `AXI4_ADDR_WIDTH'b0; +// making a burst on data and strobe buses +localparam MAX_BURST_LEN = `AXI4_DATA_WIDTH / AXI4_DAT_WIDTH_USED; +reg [clip2zer($clog2(MAX_BURST_LEN)-1) :0] burst_count; +assign m_axi_wlast = !burst_count; +reg [`AXI4_STRB_WIDTH-1:0] req_strb_f; +always @(posedge clk) + if(~rst_n) begin + burst_count <= 0; + req_data_f <= 0; + req_strb_f <= 0; + end else begin + if (req_go) begin + burst_count <= burst_len; + req_data_f <= req_data; + req_strb_f <= req_strb; end - else begin - if (uncacheable) begin - case (req_header_f[`MSG_DATA_SIZE]) - `MSG_DATA_SIZE_0B: begin - strb_before_offset <= `AXI4_STRB_WIDTH'b0; - end - `MSG_DATA_SIZE_1B: begin - strb_before_offset <= `AXI4_STRB_WIDTH'b1; - end - `MSG_DATA_SIZE_2B: begin - strb_before_offset <= `AXI4_STRB_WIDTH'b11; - end - `MSG_DATA_SIZE_4B: begin - strb_before_offset <= `AXI4_STRB_WIDTH'hf; - end - `MSG_DATA_SIZE_8B: begin - strb_before_offset <= `AXI4_STRB_WIDTH'hff; - end - `MSG_DATA_SIZE_16B: begin - strb_before_offset <= `AXI4_STRB_WIDTH'hffff; - end - `MSG_DATA_SIZE_32B: begin - strb_before_offset <= `AXI4_STRB_WIDTH'hffffffff; - end - `MSG_DATA_SIZE_64B: begin - strb_before_offset <= `AXI4_STRB_WIDTH'hffffffffffffffff; - end - default: begin - // should never end up here - strb_before_offset <= `AXI4_STRB_WIDTH'b0; - end - endcase - end - else begin - strb_before_offset <= `AXI4_STRB_WIDTH'hffffffffffffffff; - end - - offset <= uncacheable ? virt_addr[5:0] : 6'b0; - addr <= uart_boot_en ? {phys_addr[`AXI4_ADDR_WIDTH-4:0], 3'b0} : virt_addr; + else if (MAX_BURST_LEN > 1 && m_axi_wgo && ~m_axi_wlast) begin + burst_count <= burst_count-1; + // down shifting data and strobe buses every burst cycle (high part is don't care, left unchanged for optimization) + req_data_f <= {req_data_f[`AXI4_DATA_WIDTH -1 : `AXI4_DATA_WIDTH - AXI4_DAT_WIDTH_USED], + req_data_f[`AXI4_DATA_WIDTH -1 : (MAX_BURST_LEN>1 ? AXI4_DAT_WIDTH_USED : 0)]}; + req_strb_f <= {req_strb_f[`AXI4_STRB_WIDTH -1 : `AXI4_STRB_WIDTH - AXI4_DAT_WIDTH_USED/8], + req_strb_f[`AXI4_STRB_WIDTH -1 : (MAX_BURST_LEN>1 ? AXI4_DAT_WIDTH_USED/8 : 0)]}; end end -assign m_axi_awaddr = {addr[`AXI4_ADDR_WIDTH-1:6], 6'b0}; -assign m_axi_wstrb = strb_before_offset << offset; -assign m_axi_wdata = req_data_f << (8*offset); +assign m_axi_wid = m_axi_awid; +assign m_axi_wstrb = req_strb_f; +assign m_axi_wdata = req_data_f; // inbound responses wire m_axi_bgo = m_axi_bvalid & m_axi_bready; wire resp_go = resp_val & resp_rdy; -reg [2:0] resp_state; -reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0]resp_id_f; +reg resp_state; +reg [`AXI4_ID_WIDTH-1:0] resp_id_f; assign resp_val = (resp_state == GOT_RESP); assign m_axi_bready = (resp_state == IDLE); -always @(posedge clk) begin +always @(posedge clk) if(~rst_n) begin resp_id_f <= 0; resp_state <= IDLE; - end else begin + end else case (resp_state) - IDLE: begin - resp_state <= m_axi_bgo ? GOT_RESP : resp_state; - resp_id_f <= m_axi_bgo ? m_axi_bid : resp_id_f; - end - GOT_RESP: begin - resp_state <= resp_go ? IDLE : resp_state; - resp_id_f <= resp_go ? 0 : resp_id_f; + IDLE: if (m_axi_bgo) begin + resp_state <= GOT_RESP; + resp_id_f <= m_axi_bid; end + GOT_RESP: if (resp_go) + resp_state <= IDLE; default : begin resp_state <= IDLE; resp_id_f <= 0; end endcase - end -end // process data here assign resp_id = resp_id_f; diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index fdbfddf60..d64901a36 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // Copyright (c) 2015 Princeton University // All rights reserved. // @@ -217,6 +218,16 @@ module chipset( output [2:0] chip_intf_credit_back, `endif // endif PITON_NO_CHIP_BRIDGE PITONSYS_INC_PASSTHRU + `ifdef PITON_EXTRA_MEMS + input [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] processor_mcx_noc2_data, + input [`PITON_EXTRA_MEMS-1:0] processor_mcx_noc2_valid, + output [`PITON_EXTRA_MEMS-1:0] processor_mcx_noc2_yummy, + + output [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] mcx_processor_noc3_data, + output [`PITON_EXTRA_MEMS-1:0] mcx_processor_noc3_valid, + input [`PITON_EXTRA_MEMS-1:0] mcx_processor_noc3_yummy, + `endif + // DRAM and I/O interfaces `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 @@ -244,8 +255,21 @@ module chipset( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 +`ifdef PITONSYS_PCIE + input [15:0] pci_express_x16_rxn, + input [15:0] pci_express_x16_rxp, + output [15:0] pci_express_x16_txn, + output [15:0] pci_express_x16_txp, + output [4:0] pcie_gpio, + input pcie_perstn, + input pcie_refclk_n, + input pcie_refclk_p, +`endif `ifdef XUPP3R_BOARD output ddr_parity, +`elsif ALVEO_BOARD + output ddr_parity, + output hbm_cattrip, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // XUPP3R_BOARD @@ -355,7 +379,15 @@ module chipset( inout net_phy_mdio_io, output net_phy_mdc, - `endif // PITON_FPGA_ETHERNETLITE + `elsif PITON_FPGA_ETH_CMAC // PITON_FPGA_ETHERNETLITE + // GTY quads connected to QSFP unit on Alveo board + input qsfp_ref_clk_n, + input qsfp_ref_clk_p, + input [3:0] qsfp_4x_grx_n, + input [3:0] qsfp_4x_grx_p, + output [3:0] qsfp_4x_gtx_n, + output [3:0] qsfp_4x_gtx_p, + `endif // PITON_FPGA_ETH_CMAC `else // ifndef PITONSYS_IOCTRL `endif // endif PITONSYS_IOCTRL @@ -464,6 +496,9 @@ module chipset( input [3:0] sw, `elsif XUPP3R_BOARD // no switches :( + `elsif ALVEO_BOARD + input [2:0] sw, + // virtual switches :) `else input [7:0] sw, `endif @@ -556,8 +591,14 @@ reg chipset_rst_n_ff; `endif // UART boot stuff +`ifndef ALVEO_BOARD wire uart_boot_en; wire uart_timeout_en; +`else +reg uart_boot_en; +reg uart_timeout_en; +reg uart_bootrom_linux_en; +`endif // NoC power test hop count from switches if enabled wire [3:0] noc_power_test_hop_count; @@ -758,6 +799,12 @@ end `elsif XUPP3R_BOARD assign uart_boot_en = 1'b1; assign uart_timeout_en = 1'b0; + `elsif ALVEO_BOARD + always @ (posedge chipset_clk) begin + uart_boot_en <= sw[0]; + uart_timeout_en <= sw[1]; + uart_bootrom_linux_en <= sw[2]; + end `else assign uart_boot_en = sw[7]; assign uart_timeout_en = sw[6]; @@ -770,6 +817,9 @@ end `ifdef VCU118_BOARD // only two switches available... assign noc_power_test_hop_count = {2'b0, sw[3:2]}; + `elsif ALVEO_BOARD + // only two switches available... + assign noc_power_test_hop_count = {2'b0, sw[3:2]}; `elsif XUPP3R_BOARD // no switches :( assign noc_power_test_hop_count = 4'b0; @@ -1209,6 +1259,49 @@ credit_to_valrdy processor_offchip_noc3_c2v( .ready_out(intf_chipset_rdy_noc3) ); + +`ifdef PITON_EXTRA_MEMS + wire [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] mcx_intf_data_noc3; + wire [`PITON_EXTRA_MEMS-1:0] mcx_intf_val_noc3; + wire [`PITON_EXTRA_MEMS-1:0] mcx_intf_rdy_noc3; + + wire [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] intf_mcx_data_noc2; + wire [`PITON_EXTRA_MEMS-1:0] intf_mcx_val_noc2; + wire [`PITON_EXTRA_MEMS-1:0] intf_mcx_rdy_noc2; + + genvar idx; + generate + for(idx=0; idx<`PITON_EXTRA_MEMS; idx=idx+1) begin: ifconv + valrdy_to_credit #(4, 3) mcx_processor_noc3_v2c( + .clk(chipset_clk), + .reset(~chipset_rst_n_ff), + + .data_in (mcx_intf_data_noc3[idx * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]), + .valid_in(mcx_intf_val_noc3 [idx]), + .ready_in(mcx_intf_rdy_noc3 [idx]), + + .data_out (mcx_processor_noc3_data [idx * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]), + .valid_out(mcx_processor_noc3_valid[idx]), + .yummy_out(mcx_processor_noc3_yummy[idx]) + ); + + credit_to_valrdy processor_mcx_noc2_c2v( + .clk(chipset_clk), + .reset(~chipset_rst_n_ff), + + .data_in (processor_mcx_noc2_data [idx * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]), + .valid_in(processor_mcx_noc2_valid[idx]), + .yummy_in(processor_mcx_noc2_yummy[idx]), + + .data_out (intf_mcx_data_noc2[idx * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]), + .valid_out(intf_mcx_val_noc2 [idx]), + .ready_out(intf_mcx_rdy_noc2 [idx]) + ); + end + endgenerate +`endif + + `ifdef PITON_BOARD // Bootup reset sequence chip_rst_seq rst_seq( @@ -1278,6 +1371,17 @@ chipset_impl_noc_power_test chipset_impl ( .intf_chipset_rdy_noc2(intf_chipset_rdy_noc2), .intf_chipset_rdy_noc3(intf_chipset_rdy_noc3) + `ifdef PITON_EXTRA_MEMS + , + .mcx_intf_data_noc3(mcx_intf_data_noc3), + .mcx_intf_val_noc3 (mcx_intf_val_noc3), + .mcx_intf_rdy_noc3 (mcx_intf_rdy_noc3 ), + + .intf_mcx_data_noc2(intf_mcx_data_noc2), + .intf_mcx_val_noc2 (intf_mcx_val_noc2), + .intf_mcx_rdy_noc2 (intf_mcx_rdy_noc2) + `endif + // DRAM and I/O interfaces `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 @@ -1285,6 +1389,16 @@ chipset_impl_noc_power_test chipset_impl ( .init_calib_complete(init_calib_complete), `ifndef F1_BOARD `ifdef PITONSYS_DDR4 + `ifdef PITONSYS_PCIE + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_gpio(pcie_gpio), + .pcie_perstn(pcie_perstn), + .pcie_refclk_n(pcie_refclk_n), + .pcie_refclk_p(pcie_refclk_p), + `endif .ddr_act_n(ddr_act_n), .ddr_bg(ddr_bg), `else // PITONSYS_DDR4 @@ -1309,6 +1423,9 @@ chipset_impl_noc_power_test chipset_impl ( `ifdef XUPP3R_BOARD .ddr_parity(ddr_parity), + `elsif ALVEO_BOARD + .ddr_parity(ddr_parity), + .hbm_cattrip(hbm_cattrip), `else .ddr_dm(ddr_dm), `endif // XUPP3R_BOARD @@ -1418,7 +1535,16 @@ chipset_impl_noc_power_test chipset_impl ( .net_phy_mdio_io (net_phy_mdio_io ), .net_phy_mdc (net_phy_mdc ) - `endif // PITON_FPGA_ETHERNETLITE + `elsif PITON_FPGA_ETH_CMAC // PITON_FPGA_ETHERNETLITE + , + .eth_init_clk (mc_clk), + .qsfp_ref_clk_n (qsfp_ref_clk_n), + .qsfp_ref_clk_p (qsfp_ref_clk_p), + .qsfp_4x_grx_n (qsfp_4x_grx_n), + .qsfp_4x_grx_p (qsfp_4x_grx_p), + .qsfp_4x_gtx_n (qsfp_4x_gtx_n), + .qsfp_4x_gtx_p (qsfp_4x_gtx_p) + `endif // PITON_FPGA_ETH_CMAC `endif // endif PITONSYS_IOCTRL `ifdef PITON_RV64_PLATFORM diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 76bfff05b..62daf5996 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // Copyright (c) 2015 Princeton University // All rights reserved. // @@ -121,6 +122,17 @@ module chipset_impl( output intf_chipset_rdy_noc2, output intf_chipset_rdy_noc3 + `ifdef PITON_EXTRA_MEMS + , + input [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] intf_mcx_data_noc2, + input [`PITON_EXTRA_MEMS-1:0] intf_mcx_val_noc2, + output [`PITON_EXTRA_MEMS-1:0] intf_mcx_rdy_noc2, + + output [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] mcx_intf_data_noc3, + output [`PITON_EXTRA_MEMS-1:0] mcx_intf_val_noc3, + input [`PITON_EXTRA_MEMS-1:0] mcx_intf_rdy_noc3 + `endif + // DRAM and I/O interfaces `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 @@ -152,8 +164,21 @@ module chipset_impl( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 + `ifdef PITONSYS_PCIE + input [15:0] pci_express_x16_rxn, + input [15:0] pci_express_x16_rxp, + output [15:0] pci_express_x16_txn, + output [15:0] pci_express_x16_txp, + output [4:0] pcie_gpio, + input pcie_perstn, + input pcie_refclk_n, + input pcie_refclk_p, + `endif `ifdef XUPP3R_BOARD output ddr_parity, +`elsif ALVEO_BOARD + output ddr_parity, + output hbm_cattrip, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // XUPP3R_BOARD @@ -261,7 +286,16 @@ module chipset_impl( inout net_phy_mdio_io, output net_phy_mdc -`endif // PITON_FPGA_ETHERNETLITE +`elsif PITON_FPGA_ETH_CMAC // PITON_FPGA_ETHERNETLITE + , + input eth_init_clk, + input qsfp_ref_clk_n, + input qsfp_ref_clk_p, + input [3:0] qsfp_4x_grx_n, + input [3:0] qsfp_4x_grx_p, + output [3:0] qsfp_4x_gtx_n, + output [3:0] qsfp_4x_gtx_p +`endif // PITON_FPGA_ETH_CMAC `endif // endif PITONSYS_IO_CTRL `ifdef PITON_RV64_PLATFORM `ifdef PITON_RV64_DEBUGUNIT @@ -779,6 +813,171 @@ credit_to_valrdy noc3_xbar_to_%s( .ddr_ready(ddr_ready) ); `else + + `ifdef ALVEO_BOARD + `ifdef PITON_FPGA_ETH_CMAC + // Eth DMA master channels + wire [`AXI4_ID_WIDTH -1:0] eth_sg_dma_awid; + wire [`AXI4_ADDR_WIDTH -1:0] eth_sg_dma_awaddr; + wire [`AXI4_LEN_WIDTH -1:0] eth_sg_dma_awlen; + wire [`AXI4_SIZE_WIDTH -1:0] eth_sg_dma_awsize; + wire [`AXI4_BURST_WIDTH -1:0] eth_sg_dma_awburst; + wire eth_sg_dma_awlock; + wire [`AXI4_CACHE_WIDTH -1:0] eth_sg_dma_awcache; + wire [`AXI4_PROT_WIDTH -1:0] eth_sg_dma_awprot; + wire [`AXI4_QOS_WIDTH -1:0] eth_sg_dma_awqos; + wire [`AXI4_REGION_WIDTH -1:0] eth_sg_dma_awregion; + wire [`AXI4_USER_WIDTH -1:0] eth_sg_dma_awuser; + wire eth_sg_dma_awvalid; + wire eth_sg_dma_awready; + + wire [`AXI4_ID_WIDTH -1:0] eth_sg_dma_wid; + wire [`AXI4_DATA_WIDTH -1:0] eth_sg_dma_wdata; + wire [`AXI4_STRB_WIDTH -1:0] eth_sg_dma_wstrb; + wire eth_sg_dma_wlast; + wire [`AXI4_USER_WIDTH -1:0] eth_sg_dma_wuser; + wire eth_sg_dma_wvalid; + wire eth_sg_dma_wready; + + wire [`AXI4_ID_WIDTH -1:0] eth_sg_dma_arid; + wire [`AXI4_ADDR_WIDTH -1:0] eth_sg_dma_araddr; + wire [`AXI4_LEN_WIDTH -1:0] eth_sg_dma_arlen; + wire [`AXI4_SIZE_WIDTH -1:0] eth_sg_dma_arsize; + wire [`AXI4_BURST_WIDTH -1:0] eth_sg_dma_arburst; + wire eth_sg_dma_arlock; + wire [`AXI4_CACHE_WIDTH -1:0] eth_sg_dma_arcache; + wire [`AXI4_PROT_WIDTH -1:0] eth_sg_dma_arprot; + wire [`AXI4_QOS_WIDTH -1:0] eth_sg_dma_arqos; + wire [`AXI4_REGION_WIDTH -1:0] eth_sg_dma_arregion; + wire [`AXI4_USER_WIDTH -1:0] eth_sg_dma_aruser; + wire eth_sg_dma_arvalid; + wire eth_sg_dma_arready; + + wire [`AXI4_ID_WIDTH -1:0] eth_sg_dma_rid; + wire [`AXI4_DATA_WIDTH -1:0] eth_sg_dma_rdata; + wire [`AXI4_RESP_WIDTH -1:0] eth_sg_dma_rresp; + wire eth_sg_dma_rlast; + wire [`AXI4_USER_WIDTH -1:0] eth_sg_dma_ruser; + wire eth_sg_dma_rvalid; + wire eth_sg_dma_rready; + + wire [`AXI4_ID_WIDTH -1:0] eth_sg_dma_bid; + wire [`AXI4_RESP_WIDTH -1:0] eth_sg_dma_bresp; + wire [`AXI4_USER_WIDTH -1:0] eth_sg_dma_buser; + wire eth_sg_dma_bvalid; + wire eth_sg_dma_bready; + + + wire [`AXI4_ID_WIDTH -1:0] eth_tx_dma_awid; + wire [`AXI4_ADDR_WIDTH -1:0] eth_tx_dma_awaddr; + wire [`AXI4_LEN_WIDTH -1:0] eth_tx_dma_awlen; + wire [`AXI4_SIZE_WIDTH -1:0] eth_tx_dma_awsize; + wire [`AXI4_BURST_WIDTH -1:0] eth_tx_dma_awburst; + wire eth_tx_dma_awlock; + wire [`AXI4_CACHE_WIDTH -1:0] eth_tx_dma_awcache; + wire [`AXI4_PROT_WIDTH -1:0] eth_tx_dma_awprot; + wire [`AXI4_QOS_WIDTH -1:0] eth_tx_dma_awqos; + wire [`AXI4_REGION_WIDTH -1:0] eth_tx_dma_awregion; + wire [`AXI4_USER_WIDTH -1:0] eth_tx_dma_awuser; + wire eth_tx_dma_awvalid; + wire eth_tx_dma_awready; + + wire [`AXI4_ID_WIDTH -1:0] eth_tx_dma_wid; + wire [`AXI4_DATA_WIDTH -1:0] eth_tx_dma_wdata; + wire [`AXI4_STRB_WIDTH -1:0] eth_tx_dma_wstrb; + wire eth_tx_dma_wlast; + wire [`AXI4_USER_WIDTH -1:0] eth_tx_dma_wuser; + wire eth_tx_dma_wvalid; + wire eth_tx_dma_wready; + + wire [`AXI4_ID_WIDTH -1:0] eth_tx_dma_arid; + wire [`AXI4_ADDR_WIDTH -1:0] eth_tx_dma_araddr; + wire [`AXI4_LEN_WIDTH -1:0] eth_tx_dma_arlen; + wire [`AXI4_SIZE_WIDTH -1:0] eth_tx_dma_arsize; + wire [`AXI4_BURST_WIDTH -1:0] eth_tx_dma_arburst; + wire eth_tx_dma_arlock; + wire [`AXI4_CACHE_WIDTH -1:0] eth_tx_dma_arcache; + wire [`AXI4_PROT_WIDTH -1:0] eth_tx_dma_arprot; + wire [`AXI4_QOS_WIDTH -1:0] eth_tx_dma_arqos; + wire [`AXI4_REGION_WIDTH -1:0] eth_tx_dma_arregion; + wire [`AXI4_USER_WIDTH -1:0] eth_tx_dma_aruser; + wire eth_tx_dma_arvalid; + wire eth_tx_dma_arready; + + wire [`AXI4_ID_WIDTH -1:0] eth_tx_dma_rid; + wire [`AXI4_DATA_WIDTH -1:0] eth_tx_dma_rdata; + wire [`AXI4_RESP_WIDTH -1:0] eth_tx_dma_rresp; + wire eth_tx_dma_rlast; + wire [`AXI4_USER_WIDTH -1:0] eth_tx_dma_ruser; + wire eth_tx_dma_rvalid; + wire eth_tx_dma_rready; + + wire [`AXI4_ID_WIDTH -1:0] eth_tx_dma_bid; + wire [`AXI4_RESP_WIDTH -1:0] eth_tx_dma_bresp; + wire [`AXI4_USER_WIDTH -1:0] eth_tx_dma_buser; + wire eth_tx_dma_bvalid; + wire eth_tx_dma_bready; + + wire eth_tx_dma_clk; + wire eth_tx_dma_rstn; + + + wire [`AXI4_ID_WIDTH -1:0] eth_rx_dma_awid; + wire [`AXI4_ADDR_WIDTH -1:0] eth_rx_dma_awaddr; + wire [`AXI4_LEN_WIDTH -1:0] eth_rx_dma_awlen; + wire [`AXI4_SIZE_WIDTH -1:0] eth_rx_dma_awsize; + wire [`AXI4_BURST_WIDTH -1:0] eth_rx_dma_awburst; + wire eth_rx_dma_awlock; + wire [`AXI4_CACHE_WIDTH -1:0] eth_rx_dma_awcache; + wire [`AXI4_PROT_WIDTH -1:0] eth_rx_dma_awprot; + wire [`AXI4_QOS_WIDTH -1:0] eth_rx_dma_awqos; + wire [`AXI4_REGION_WIDTH -1:0] eth_rx_dma_awregion; + wire [`AXI4_USER_WIDTH -1:0] eth_rx_dma_awuser; + wire eth_rx_dma_awvalid; + wire eth_rx_dma_awready; + + wire [`AXI4_ID_WIDTH -1:0] eth_rx_dma_wid; + wire [`AXI4_DATA_WIDTH -1:0] eth_rx_dma_wdata; + wire [`AXI4_STRB_WIDTH -1:0] eth_rx_dma_wstrb; + wire eth_rx_dma_wlast; + wire [`AXI4_USER_WIDTH -1:0] eth_rx_dma_wuser; + wire eth_rx_dma_wvalid; + wire eth_rx_dma_wready; + + wire [`AXI4_ID_WIDTH -1:0] eth_rx_dma_arid; + wire [`AXI4_ADDR_WIDTH -1:0] eth_rx_dma_araddr; + wire [`AXI4_LEN_WIDTH -1:0] eth_rx_dma_arlen; + wire [`AXI4_SIZE_WIDTH -1:0] eth_rx_dma_arsize; + wire [`AXI4_BURST_WIDTH -1:0] eth_rx_dma_arburst; + wire eth_rx_dma_arlock; + wire [`AXI4_CACHE_WIDTH -1:0] eth_rx_dma_arcache; + wire [`AXI4_PROT_WIDTH -1:0] eth_rx_dma_arprot; + wire [`AXI4_QOS_WIDTH -1:0] eth_rx_dma_arqos; + wire [`AXI4_REGION_WIDTH -1:0] eth_rx_dma_arregion; + wire [`AXI4_USER_WIDTH -1:0] eth_rx_dma_aruser; + wire eth_rx_dma_arvalid; + wire eth_rx_dma_arready; + + wire [`AXI4_ID_WIDTH -1:0] eth_rx_dma_rid; + wire [`AXI4_DATA_WIDTH -1:0] eth_rx_dma_rdata; + wire [`AXI4_RESP_WIDTH -1:0] eth_rx_dma_rresp; + wire eth_rx_dma_rlast; + wire [`AXI4_USER_WIDTH -1:0] eth_rx_dma_ruser; + wire eth_rx_dma_rvalid; + wire eth_rx_dma_rready; + + wire [`AXI4_ID_WIDTH -1:0] eth_rx_dma_bid; + wire [`AXI4_RESP_WIDTH -1:0] eth_rx_dma_bresp; + wire [`AXI4_USER_WIDTH -1:0] eth_rx_dma_buser; + wire eth_rx_dma_bvalid; + wire eth_rx_dma_bready; + + wire eth_rx_dma_clk; + wire eth_rx_dma_rstn; + + `endif //`ifdef PITON_FPGA_ETH_CMAC + `endif //`ifdef ALVEO_BOARD + mc_top mc_top( .mc_ui_clk_sync_rst(mc_ui_clk_sync_rst), @@ -793,6 +992,16 @@ credit_to_valrdy noc3_xbar_to_%s( .mc_flit_out_data(mem_buf_noc3_data), .mc_flit_out_rdy(buf_mem_noc3_ready), + `ifdef PITON_EXTRA_MEMS + .mcx_flit_in_val (intf_mcx_val_noc2 ), + .mcx_flit_in_data(intf_mcx_data_noc2), + .mcx_flit_in_rdy (intf_mcx_rdy_noc2 ), + + .mcx_flit_out_val (mcx_intf_val_noc3 ), + .mcx_flit_out_data(mcx_intf_data_noc3), + .mcx_flit_out_rdy (mcx_intf_rdy_noc3 ), + `endif + .uart_boot_en(uart_boot_en), .init_calib_complete_out(init_calib_complete), @@ -801,6 +1010,16 @@ credit_to_valrdy noc3_xbar_to_%s( .sys_clk_n(mc_clk_n), .ddr_act_n(ddr_act_n), .ddr_bg(ddr_bg), + `ifdef PITONSYS_PCIE + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_gpio(pcie_gpio), + .pcie_perstn(pcie_perstn), + .pcie_refclk_n(pcie_refclk_n), + .pcie_refclk_p(pcie_refclk_p), + `endif `else // PITONSYS_DDR4 .sys_clk(mc_clk), .ddr_cas_n(ddr_cas_n), @@ -822,6 +1041,168 @@ credit_to_valrdy noc3_xbar_to_%s( `endif // endif NEXYSVIDEO_BOARD `ifdef XUPP3R_BOARD .ddr_parity(ddr_parity), + `elsif ALVEO_BOARD + `ifdef PITON_FPGA_ETH_CMAC + .eth_sg_dma_awid (eth_sg_dma_awid ), + .eth_sg_dma_awaddr (eth_sg_dma_awaddr ), + .eth_sg_dma_awlen (eth_sg_dma_awlen ), + .eth_sg_dma_awsize (eth_sg_dma_awsize ), + .eth_sg_dma_awburst (eth_sg_dma_awburst), + .eth_sg_dma_awlock (eth_sg_dma_awlock ), + .eth_sg_dma_awcache (eth_sg_dma_awcache), + .eth_sg_dma_awprot (eth_sg_dma_awprot ), + .eth_sg_dma_awqos (eth_sg_dma_awqos ), + .eth_sg_dma_awregion (eth_sg_dma_awregion), + .eth_sg_dma_awuser (eth_sg_dma_awuser ), + .eth_sg_dma_awvalid (eth_sg_dma_awvalid ), + .eth_sg_dma_awready (eth_sg_dma_awready ), + + .eth_sg_dma_wid (eth_sg_dma_wid ), + .eth_sg_dma_wdata (eth_sg_dma_wdata ), + .eth_sg_dma_wstrb (eth_sg_dma_wstrb ), + .eth_sg_dma_wlast (eth_sg_dma_wlast ), + .eth_sg_dma_wuser (eth_sg_dma_wuser ), + .eth_sg_dma_wvalid (eth_sg_dma_wvalid), + .eth_sg_dma_wready (eth_sg_dma_wready), + + .eth_sg_dma_arid (eth_sg_dma_arid ), + .eth_sg_dma_araddr (eth_sg_dma_araddr), + .eth_sg_dma_arlen (eth_sg_dma_arlen ), + .eth_sg_dma_arsize (eth_sg_dma_arsize), + .eth_sg_dma_arburst (eth_sg_dma_arburst ), + .eth_sg_dma_arlock (eth_sg_dma_arlock ), + .eth_sg_dma_arcache (eth_sg_dma_arcache ), + .eth_sg_dma_arprot (eth_sg_dma_arprot ), + .eth_sg_dma_arqos (eth_sg_dma_arqos ), + .eth_sg_dma_arregion (eth_sg_dma_arregion), + .eth_sg_dma_aruser (eth_sg_dma_aruser ), + .eth_sg_dma_arvalid (eth_sg_dma_arvalid ), + .eth_sg_dma_arready (eth_sg_dma_arready ), + + .eth_sg_dma_rid (eth_sg_dma_rid ), + .eth_sg_dma_rdata (eth_sg_dma_rdata ), + .eth_sg_dma_rresp (eth_sg_dma_rresp ), + .eth_sg_dma_rlast (eth_sg_dma_rlast ), + .eth_sg_dma_ruser (eth_sg_dma_ruser ), + .eth_sg_dma_rvalid (eth_sg_dma_rvalid ), + .eth_sg_dma_rready (eth_sg_dma_rready ), + + .eth_sg_dma_bid (eth_sg_dma_bid ), + .eth_sg_dma_bresp (eth_sg_dma_bresp ), + .eth_sg_dma_buser (eth_sg_dma_buser ), + .eth_sg_dma_bvalid (eth_sg_dma_bvalid ), + .eth_sg_dma_bready (eth_sg_dma_bready ), + + + .eth_tx_dma_awid (eth_tx_dma_awid ), + .eth_tx_dma_awaddr (eth_tx_dma_awaddr ), + .eth_tx_dma_awlen (eth_tx_dma_awlen ), + .eth_tx_dma_awsize (eth_tx_dma_awsize ), + .eth_tx_dma_awburst (eth_tx_dma_awburst), + .eth_tx_dma_awlock (eth_tx_dma_awlock ), + .eth_tx_dma_awcache (eth_tx_dma_awcache), + .eth_tx_dma_awprot (eth_tx_dma_awprot ), + .eth_tx_dma_awqos (eth_tx_dma_awqos ), + .eth_tx_dma_awregion (eth_tx_dma_awregion), + .eth_tx_dma_awuser (eth_tx_dma_awuser ), + .eth_tx_dma_awvalid (eth_tx_dma_awvalid ), + .eth_tx_dma_awready (eth_tx_dma_awready ), + + .eth_tx_dma_wid (eth_tx_dma_wid ), + .eth_tx_dma_wdata (eth_tx_dma_wdata ), + .eth_tx_dma_wstrb (eth_tx_dma_wstrb ), + .eth_tx_dma_wlast (eth_tx_dma_wlast ), + .eth_tx_dma_wuser (eth_tx_dma_wuser ), + .eth_tx_dma_wvalid (eth_tx_dma_wvalid), + .eth_tx_dma_wready (eth_tx_dma_wready), + + .eth_tx_dma_arid (eth_tx_dma_arid ), + .eth_tx_dma_araddr (eth_tx_dma_araddr), + .eth_tx_dma_arlen (eth_tx_dma_arlen ), + .eth_tx_dma_arsize (eth_tx_dma_arsize), + .eth_tx_dma_arburst (eth_tx_dma_arburst ), + .eth_tx_dma_arlock (eth_tx_dma_arlock ), + .eth_tx_dma_arcache (eth_tx_dma_arcache ), + .eth_tx_dma_arprot (eth_tx_dma_arprot ), + .eth_tx_dma_arqos (eth_tx_dma_arqos ), + .eth_tx_dma_arregion (eth_tx_dma_arregion), + .eth_tx_dma_aruser (eth_tx_dma_aruser ), + .eth_tx_dma_arvalid (eth_tx_dma_arvalid ), + .eth_tx_dma_arready (eth_tx_dma_arready ), + + .eth_tx_dma_rid (eth_tx_dma_rid ), + .eth_tx_dma_rdata (eth_tx_dma_rdata ), + .eth_tx_dma_rresp (eth_tx_dma_rresp ), + .eth_tx_dma_rlast (eth_tx_dma_rlast ), + .eth_tx_dma_ruser (eth_tx_dma_ruser ), + .eth_tx_dma_rvalid (eth_tx_dma_rvalid ), + .eth_tx_dma_rready (eth_tx_dma_rready ), + + .eth_tx_dma_bid (eth_tx_dma_bid ), + .eth_tx_dma_bresp (eth_tx_dma_bresp ), + .eth_tx_dma_buser (eth_tx_dma_buser ), + .eth_tx_dma_bvalid (eth_tx_dma_bvalid ), + .eth_tx_dma_bready (eth_tx_dma_bready ), + + .eth_tx_dma_clk (eth_tx_dma_clk ), + .eth_tx_dma_rstn (eth_tx_dma_rstn), + + + .eth_rx_dma_awid (eth_rx_dma_awid ), + .eth_rx_dma_awaddr (eth_rx_dma_awaddr ), + .eth_rx_dma_awlen (eth_rx_dma_awlen ), + .eth_rx_dma_awsize (eth_rx_dma_awsize ), + .eth_rx_dma_awburst (eth_rx_dma_awburst), + .eth_rx_dma_awlock (eth_rx_dma_awlock ), + .eth_rx_dma_awcache (eth_rx_dma_awcache), + .eth_rx_dma_awprot (eth_rx_dma_awprot ), + .eth_rx_dma_awqos (eth_rx_dma_awqos ), + .eth_rx_dma_awregion (eth_rx_dma_awregion), + .eth_rx_dma_awuser (eth_rx_dma_awuser ), + .eth_rx_dma_awvalid (eth_rx_dma_awvalid ), + .eth_rx_dma_awready (eth_rx_dma_awready ), + + .eth_rx_dma_wid (eth_rx_dma_wid ), + .eth_rx_dma_wdata (eth_rx_dma_wdata ), + .eth_rx_dma_wstrb (eth_rx_dma_wstrb ), + .eth_rx_dma_wlast (eth_rx_dma_wlast ), + .eth_rx_dma_wuser (eth_rx_dma_wuser ), + .eth_rx_dma_wvalid (eth_rx_dma_wvalid), + .eth_rx_dma_wready (eth_rx_dma_wready), + + .eth_rx_dma_arid (eth_rx_dma_arid ), + .eth_rx_dma_araddr (eth_rx_dma_araddr), + .eth_rx_dma_arlen (eth_rx_dma_arlen ), + .eth_rx_dma_arsize (eth_rx_dma_arsize), + .eth_rx_dma_arburst (eth_rx_dma_arburst ), + .eth_rx_dma_arlock (eth_rx_dma_arlock ), + .eth_rx_dma_arcache (eth_rx_dma_arcache ), + .eth_rx_dma_arprot (eth_rx_dma_arprot ), + .eth_rx_dma_arqos (eth_rx_dma_arqos ), + .eth_rx_dma_arregion (eth_rx_dma_arregion), + .eth_rx_dma_aruser (eth_rx_dma_aruser ), + .eth_rx_dma_arvalid (eth_rx_dma_arvalid ), + .eth_rx_dma_arready (eth_rx_dma_arready ), + + .eth_rx_dma_rid (eth_rx_dma_rid ), + .eth_rx_dma_rdata (eth_rx_dma_rdata ), + .eth_rx_dma_rresp (eth_rx_dma_rresp ), + .eth_rx_dma_rlast (eth_rx_dma_rlast ), + .eth_rx_dma_ruser (eth_rx_dma_ruser ), + .eth_rx_dma_rvalid (eth_rx_dma_rvalid ), + .eth_rx_dma_rready (eth_rx_dma_rready ), + + .eth_rx_dma_bid (eth_rx_dma_bid ), + .eth_rx_dma_bresp (eth_rx_dma_bresp ), + .eth_rx_dma_buser (eth_rx_dma_buser ), + .eth_rx_dma_bvalid (eth_rx_dma_bvalid ), + .eth_rx_dma_bready (eth_rx_dma_bready ), + + .eth_rx_dma_clk (eth_rx_dma_clk ), + .eth_rx_dma_rstn (eth_rx_dma_rstn), + `endif //`ifdef PITON_FPGA_ETH_CMAC + .ddr_parity(ddr_parity), + .hbm_cattrip(hbm_cattrip), `else .ddr_dm(ddr_dm), `endif // XUPP3R_BOARD @@ -845,6 +1226,26 @@ fake_mem_ctrl fake_mem_ctrl( .noc_ready_out ( buf_mem_noc3_ready ) ); +`ifdef PITON_EXTRA_MEMS +genvar i; +generate +for(i=0;i<`PITON_EXTRA_MEMS;i=i+1) begin: MT_ + fake_mem_ctrl #( + .HMB_CHAN_NUM(i) + ) fake_mt ( + .clk ( chipset_clk ), + .rst_n ( chipset_rst_n ), + .noc_valid_in ( intf_mcx_val_noc2 [i] ), + .noc_data_in ( intf_mcx_data_noc2[i * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH] ), + .noc_ready_in ( intf_mcx_rdy_noc2 [i] ), + .noc_valid_out ( mcx_intf_val_noc3 [i] ), + .noc_data_out ( mcx_intf_data_noc3[i * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH] ), + .noc_ready_out ( mcx_intf_rdy_noc3 [i] ) + ); +end +endgenerate +`endif + `endif // endif PITON_FPGA_MC_DDR3 `else @@ -883,8 +1284,16 @@ fake_mem_ctrl fake_mem_ctrl( `endif // endif PITONSYS_NO_MC + `ifdef PITON_FPGA_ETH_CMAC + localparam integer NUM_INTR_ETH = 2; + `else + localparam integer NUM_INTR_ETH = 1; + `endif -wire net_interrupt; +localparam integer NUM_INTR_UART = 1; +localparam integer NUM_INTR_RISCV = NUM_INTR_ETH + NUM_INTR_UART; + +wire [NUM_INTR_ETH-1:0] net_interrupt; wire uart_interrupt; `ifdef PITONSYS_IOCTRL @@ -941,7 +1350,11 @@ uart_top uart_top ( .uart_lb_sw ( 1'b0 ), `endif // endif PITONSYS_UART_LOOBACK +`ifdef PITONSYS_PCIE + .uart_boot_en ( pcie_gpio[2] ), //uart_boot_en +`else // PITONSYS_PCIE .uart_boot_en ( uart_boot_en ), +`endif // PITONSYS_PCIE `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 .init_calib_complete (init_calib_complete_ff ), @@ -953,8 +1366,8 @@ uart_top uart_top ( `endif // PITONSYS_NO_MC // Uncomment to connect to the switch - // .uart_timeout_en(uart_timeout_en), - .uart_timeout_en ( 1'b1 ), + .uart_timeout_en(uart_timeout_en), + //.uart_timeout_en ( 1'b1 ), .test_start ( test_start ), .test_good_end ( test_good_end ), @@ -1019,18 +1432,20 @@ uart_top uart_top ( `endif -`ifdef PITON_FPGA_ETHERNETLITE +`ifdef PITON_FPGA_ETH eth_top #( `ifdef PITON_RV64_PLATFORM - .SWAP_ENDIANESS(1) + .SWAP_ENDIANESS(1), `else - .SWAP_ENDIANESS(0) + .SWAP_ENDIANESS(0), `endif + .NUM_INTR(NUM_INTR_ETH) ) eth_top ( .chipset_clk ( chipset_clk ), .rst_n ( chipset_rst_n ), + // Interrupts are forwarded in the chipset_clk domain .net_interrupt ( net_interrupt ), .noc_in_val ( buf_net_noc2_valid ), @@ -1039,8 +1454,10 @@ uart_top uart_top ( .noc_out_val ( net_buf_noc3_valid ), .noc_out_data ( net_buf_noc3_data ), - .noc_out_rdy ( buf_net_noc3_ready ), + .noc_out_rdy ( buf_net_noc3_ready ) + `ifdef PITON_FPGA_ETHERNETLITE + , .net_axi_clk ( net_axi_clk ), .net_phy_rst_n ( net_phy_rst_n ), @@ -1055,8 +1472,176 @@ uart_top uart_top ( .net_phy_mdio_io ( net_phy_mdio_io ), .net_phy_mdc ( net_phy_mdc ) + `elsif PITON_FPGA_ETH_CMAC // PITON_FPGA_ETHERNETLITE + , + .eth_sg_dma_awid (eth_sg_dma_awid ), + .eth_sg_dma_awaddr (eth_sg_dma_awaddr ), + .eth_sg_dma_awlen (eth_sg_dma_awlen ), + .eth_sg_dma_awsize (eth_sg_dma_awsize ), + .eth_sg_dma_awburst (eth_sg_dma_awburst), + .eth_sg_dma_awlock (eth_sg_dma_awlock ), + .eth_sg_dma_awcache (eth_sg_dma_awcache), + .eth_sg_dma_awprot (eth_sg_dma_awprot ), + .eth_sg_dma_awqos (eth_sg_dma_awqos ), + .eth_sg_dma_awregion (eth_sg_dma_awregion), + .eth_sg_dma_awuser (eth_sg_dma_awuser ), + .eth_sg_dma_awvalid (eth_sg_dma_awvalid ), + .eth_sg_dma_awready (eth_sg_dma_awready ), + + .eth_sg_dma_wid (eth_sg_dma_wid ), + .eth_sg_dma_wdata (eth_sg_dma_wdata ), + .eth_sg_dma_wstrb (eth_sg_dma_wstrb ), + .eth_sg_dma_wlast (eth_sg_dma_wlast ), + .eth_sg_dma_wuser (eth_sg_dma_wuser ), + .eth_sg_dma_wvalid (eth_sg_dma_wvalid), + .eth_sg_dma_wready (eth_sg_dma_wready), + + .eth_sg_dma_arid (eth_sg_dma_arid ), + .eth_sg_dma_araddr (eth_sg_dma_araddr), + .eth_sg_dma_arlen (eth_sg_dma_arlen ), + .eth_sg_dma_arsize (eth_sg_dma_arsize), + .eth_sg_dma_arburst (eth_sg_dma_arburst ), + .eth_sg_dma_arlock (eth_sg_dma_arlock ), + .eth_sg_dma_arcache (eth_sg_dma_arcache ), + .eth_sg_dma_arprot (eth_sg_dma_arprot ), + .eth_sg_dma_arqos (eth_sg_dma_arqos ), + .eth_sg_dma_arregion (eth_sg_dma_arregion), + .eth_sg_dma_aruser (eth_sg_dma_aruser ), + .eth_sg_dma_arvalid (eth_sg_dma_arvalid ), + .eth_sg_dma_arready (eth_sg_dma_arready ), + + .eth_sg_dma_rid (eth_sg_dma_rid ), + .eth_sg_dma_rdata (eth_sg_dma_rdata ), + .eth_sg_dma_rresp (eth_sg_dma_rresp ), + .eth_sg_dma_rlast (eth_sg_dma_rlast ), + .eth_sg_dma_ruser (eth_sg_dma_ruser ), + .eth_sg_dma_rvalid (eth_sg_dma_rvalid ), + .eth_sg_dma_rready (eth_sg_dma_rready ), + + .eth_sg_dma_bid (eth_sg_dma_bid ), + .eth_sg_dma_bresp (eth_sg_dma_bresp ), + .eth_sg_dma_buser (eth_sg_dma_buser ), + .eth_sg_dma_bvalid (eth_sg_dma_bvalid ), + .eth_sg_dma_bready (eth_sg_dma_bready ), + + + .eth_tx_dma_awid (eth_tx_dma_awid ), + .eth_tx_dma_awaddr (eth_tx_dma_awaddr ), + .eth_tx_dma_awlen (eth_tx_dma_awlen ), + .eth_tx_dma_awsize (eth_tx_dma_awsize ), + .eth_tx_dma_awburst (eth_tx_dma_awburst), + .eth_tx_dma_awlock (eth_tx_dma_awlock ), + .eth_tx_dma_awcache (eth_tx_dma_awcache), + .eth_tx_dma_awprot (eth_tx_dma_awprot ), + .eth_tx_dma_awqos (eth_tx_dma_awqos ), + .eth_tx_dma_awregion (eth_tx_dma_awregion), + .eth_tx_dma_awuser (eth_tx_dma_awuser ), + .eth_tx_dma_awvalid (eth_tx_dma_awvalid ), + .eth_tx_dma_awready (eth_tx_dma_awready ), + + .eth_tx_dma_wid (eth_tx_dma_wid ), + .eth_tx_dma_wdata (eth_tx_dma_wdata ), + .eth_tx_dma_wstrb (eth_tx_dma_wstrb ), + .eth_tx_dma_wlast (eth_tx_dma_wlast ), + .eth_tx_dma_wuser (eth_tx_dma_wuser ), + .eth_tx_dma_wvalid (eth_tx_dma_wvalid), + .eth_tx_dma_wready (eth_tx_dma_wready), + + .eth_tx_dma_arid (eth_tx_dma_arid ), + .eth_tx_dma_araddr (eth_tx_dma_araddr), + .eth_tx_dma_arlen (eth_tx_dma_arlen ), + .eth_tx_dma_arsize (eth_tx_dma_arsize), + .eth_tx_dma_arburst (eth_tx_dma_arburst ), + .eth_tx_dma_arlock (eth_tx_dma_arlock ), + .eth_tx_dma_arcache (eth_tx_dma_arcache ), + .eth_tx_dma_arprot (eth_tx_dma_arprot ), + .eth_tx_dma_arqos (eth_tx_dma_arqos ), + .eth_tx_dma_arregion (eth_tx_dma_arregion), + .eth_tx_dma_aruser (eth_tx_dma_aruser ), + .eth_tx_dma_arvalid (eth_tx_dma_arvalid ), + .eth_tx_dma_arready (eth_tx_dma_arready ), + + .eth_tx_dma_rid (eth_tx_dma_rid ), + .eth_tx_dma_rdata (eth_tx_dma_rdata ), + .eth_tx_dma_rresp (eth_tx_dma_rresp ), + .eth_tx_dma_rlast (eth_tx_dma_rlast ), + .eth_tx_dma_ruser (eth_tx_dma_ruser ), + .eth_tx_dma_rvalid (eth_tx_dma_rvalid ), + .eth_tx_dma_rready (eth_tx_dma_rready ), + + .eth_tx_dma_bid (eth_tx_dma_bid ), + .eth_tx_dma_bresp (eth_tx_dma_bresp ), + .eth_tx_dma_buser (eth_tx_dma_buser ), + .eth_tx_dma_bvalid (eth_tx_dma_bvalid ), + .eth_tx_dma_bready (eth_tx_dma_bready ), + + .eth_tx_dma_clk (eth_tx_dma_clk ), + .eth_tx_dma_rstn (eth_tx_dma_rstn), + + + .eth_rx_dma_awid (eth_rx_dma_awid ), + .eth_rx_dma_awaddr (eth_rx_dma_awaddr ), + .eth_rx_dma_awlen (eth_rx_dma_awlen ), + .eth_rx_dma_awsize (eth_rx_dma_awsize ), + .eth_rx_dma_awburst (eth_rx_dma_awburst), + .eth_rx_dma_awlock (eth_rx_dma_awlock ), + .eth_rx_dma_awcache (eth_rx_dma_awcache), + .eth_rx_dma_awprot (eth_rx_dma_awprot ), + .eth_rx_dma_awqos (eth_rx_dma_awqos ), + .eth_rx_dma_awregion (eth_rx_dma_awregion), + .eth_rx_dma_awuser (eth_rx_dma_awuser ), + .eth_rx_dma_awvalid (eth_rx_dma_awvalid ), + .eth_rx_dma_awready (eth_rx_dma_awready ), + + .eth_rx_dma_wid (eth_rx_dma_wid ), + .eth_rx_dma_wdata (eth_rx_dma_wdata ), + .eth_rx_dma_wstrb (eth_rx_dma_wstrb ), + .eth_rx_dma_wlast (eth_rx_dma_wlast ), + .eth_rx_dma_wuser (eth_rx_dma_wuser ), + .eth_rx_dma_wvalid (eth_rx_dma_wvalid), + .eth_rx_dma_wready (eth_rx_dma_wready), + + .eth_rx_dma_arid (eth_rx_dma_arid ), + .eth_rx_dma_araddr (eth_rx_dma_araddr), + .eth_rx_dma_arlen (eth_rx_dma_arlen ), + .eth_rx_dma_arsize (eth_rx_dma_arsize), + .eth_rx_dma_arburst (eth_rx_dma_arburst ), + .eth_rx_dma_arlock (eth_rx_dma_arlock ), + .eth_rx_dma_arcache (eth_rx_dma_arcache ), + .eth_rx_dma_arprot (eth_rx_dma_arprot ), + .eth_rx_dma_arqos (eth_rx_dma_arqos ), + .eth_rx_dma_arregion (eth_rx_dma_arregion), + .eth_rx_dma_aruser (eth_rx_dma_aruser ), + .eth_rx_dma_arvalid (eth_rx_dma_arvalid ), + .eth_rx_dma_arready (eth_rx_dma_arready ), + + .eth_rx_dma_rid (eth_rx_dma_rid ), + .eth_rx_dma_rdata (eth_rx_dma_rdata ), + .eth_rx_dma_rresp (eth_rx_dma_rresp ), + .eth_rx_dma_rlast (eth_rx_dma_rlast ), + .eth_rx_dma_ruser (eth_rx_dma_ruser ), + .eth_rx_dma_rvalid (eth_rx_dma_rvalid ), + .eth_rx_dma_rready (eth_rx_dma_rready ), + + .eth_rx_dma_bid (eth_rx_dma_bid ), + .eth_rx_dma_bresp (eth_rx_dma_bresp ), + .eth_rx_dma_buser (eth_rx_dma_buser ), + .eth_rx_dma_bvalid (eth_rx_dma_bvalid ), + .eth_rx_dma_bready (eth_rx_dma_bready ), + + .eth_rx_dma_clk (eth_rx_dma_clk ), + .eth_rx_dma_rstn (eth_rx_dma_rstn), + + .eth_init_clk (eth_init_clk), + .qsfp_ref_clk_n (qsfp_ref_clk_n), + .qsfp_ref_clk_p (qsfp_ref_clk_p), + .qsfp_4x_grx_n (qsfp_4x_grx_n), + .qsfp_4x_grx_p (qsfp_4x_grx_p), + .qsfp_4x_gtx_n (qsfp_4x_gtx_n), + .qsfp_4x_gtx_p (qsfp_4x_gtx_p) + `endif // PITON_FPGA_ETH_CMAC ); -`endif // PITON_FPGA_ETHERNETLITE +`endif // PITON_FPGA_ETH `else // PITONSYS_IOCTRL @@ -1112,16 +1697,26 @@ fake_uart fake_uart ( `ifdef PITON_RV64_PLATFORM - wire [1:0] irq_sources, irq_le; + wire [NUM_INTR_RISCV-1:0] irq_sources, irq_le; // 0:level 1:edge // Eth is edge, Uart is level - assign irq_le = {1'b1, 1'b0}; + wire [NUM_INTR_ETH-1:0] irq_eth_le = 0; + + assign irq_le = {irq_eth_le, 1'b0}; assign irq_sources = {net_interrupt, uart_interrupt}; // this is for selecting the right bootrom (1: baremetal, 0: linux) wire ariane_boot_sel; `ifdef PITON_FPGA_SYNTH + `ifndef ALVEO_BOARD assign ariane_boot_sel = uart_boot_en; + `else + `ifdef PITONSYS_UART_BOOT + assign ariane_boot_sel = uart_boot_en; + `else + assign ariane_boot_sel = 1'b0; + `endif + `endif `else `ifdef ARIANE_SIM_LINUX_BOOT assign ariane_boot_sel = 1'b0; @@ -1148,7 +1743,7 @@ str = ''' riscv_peripherals #( .DataWidth ( `NOC_DATA_WIDTH ), .NumHarts ( `PITON_NUM_TILES), - .NumSources ( 2 ), + .NumSources ( NUM_INTR_RISCV ), .SwapEndianess ( 1 ), .DmBase ( 64'h%016x ), .RomBase ( 64'h%016x ), diff --git a/piton/design/chipset/rv64_platform/bootrom/linux/src/main.c b/piton/design/chipset/rv64_platform/bootrom/linux/src/main.c index 2e5a9dc4a..ef7e82de1 100644 --- a/piton/design/chipset/rv64_platform/bootrom/linux/src/main.c +++ b/piton/design/chipset/rv64_platform/bootrom/linux/src/main.c @@ -11,7 +11,7 @@ int main() print_uart("sd initialized!\r\n"); - int res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 32768); + // int res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 32768); return 0; } diff --git a/piton/design/chipset/rv64_platform/bootrom/linux/src/uart.c b/piton/design/chipset/rv64_platform/bootrom/linux/src/uart.c index c6243aafd..872d85b1d 100644 --- a/piton/design/chipset/rv64_platform/bootrom/linux/src/uart.c +++ b/piton/design/chipset/rv64_platform/bootrom/linux/src/uart.c @@ -25,7 +25,7 @@ void write_serial(char a) void init_uart(uint32_t freq, uint32_t baud) { - uint32_t divisor = freq / (baud << 4); + uint32_t divisor = (freq + (baud << 3))/ (baud << 4); write_reg_u8(UART_INTERRUPT_ENABLE, 0x00); // Disable all interrupts write_reg_u8(UART_LINE_CONTROL, 0x80); // Enable DLAB (set baud rate divisor) diff --git a/piton/design/chipset/rv64_platform/bootrom/linux/startup.S b/piton/design/chipset/rv64_platform/bootrom/linux/startup.S index 29dea4bfe..d04f06a0c 100644 --- a/piton/design/chipset/rv64_platform/bootrom/linux/startup.S +++ b/piton/design/chipset/rv64_platform/bootrom/linux/startup.S @@ -8,10 +8,10 @@ .option norvc .globl _prog_start _prog_start: - smp_pause(s1, s2) + //smp_pause(s1, s2) li sp, 0x84000000 call main - smp_resume(s1, s2) + //smp_resume(s1, s2) csrr a0, mhartid la a1, _dtb li s1, DRAM_BASE diff --git a/piton/design/common/rtl/Flist.common b/piton/design/common/rtl/Flist.common index b7c385c9b..c49ced6bb 100644 --- a/piton/design/common/rtl/Flist.common +++ b/piton/design/common/rtl/Flist.common @@ -10,3 +10,5 @@ noc_fbits_splitter.v noc_simple_merger.v noc_simple_splitter.v sync_fifo_vr.v +bram_sdp_1ck.v +bram_tdp_1ck_wrfirst.v diff --git a/piton/design/common/rtl/bram_sdp_1ck.v b/piton/design/common/rtl/bram_sdp_1ck.v new file mode 100644 index 000000000..153219a4b --- /dev/null +++ b/piton/design/common/rtl/bram_sdp_1ck.v @@ -0,0 +1,121 @@ +// Copyright 2022 Barcelona Supercomputing Center-Centro Nacional de Supercomputación + +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Alexander Kropotov, BSC-CNS +// Date: 22.02.2022 +// Description: +// Xilinx Simple Dual Port Single Clock RAM (taken from Xilinx Vivado synthesis templates) +// This code implements a parameterizable SDP single clock memory. +// If a reset or enable is not necessary, it may be tied off or removed from the code. + +module bram_sdp_1ck #( + parameter RAM_WIDTH = 64, // Specify RAM data width + parameter RAM_DEPTH = 512, // Specify RAM depth (number of entries) + parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" + parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not) +) ( + input [clogb2(RAM_DEPTH-1)-1:0] addra, // Write address bus, width determined from RAM_DEPTH + input [clogb2(RAM_DEPTH-1)-1:0] addrb, // Read address bus, width determined from RAM_DEPTH + input [RAM_WIDTH-1:0] dina, // RAM input data + input clka, // Clock + input wea, // Write enable + input enb, // Read Enable, for additional power savings, disable when not in use + input rstb, // Output reset (does not affect memory contents) + input regceb, // Output register enable + output [RAM_WIDTH-1:0] doutb // RAM output data +); + + reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0]; + reg [RAM_WIDTH-1:0] ram_data = {RAM_WIDTH{1'b0}}; + + // actual read pipeline for inter-port write-first policy + reg [clogb2(RAM_DEPTH-1)-1:0] addrb_rd; + + // The following code either initializes the memory values to a specified file or to all zeros to match Xilinx hardware + generate + if (INIT_FILE == "xilinx_default_zeroes") // Explicit initialization with zeroes (power-up zero filling is not applicable for ASIC) + begin: init_bram_to_zero + integer ram_index; + initial + for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1) + BRAM[ram_index] = {RAM_WIDTH{1'b0}}; + end + else if (INIT_FILE != "") begin: use_init_file + initial + $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH-1); + end + endgenerate + + always @(posedge clka) begin + if (wea) + BRAM[addra] <= dina; + if (enb) + addrb_rd <= addrb; + ram_data <= BRAM[addrb]; + end + // always @(*) ram_data = BRAM[addrb_rd]; + + // The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register) + generate + if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register + + // The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing + assign doutb = ram_data; + + end else begin: output_register + + // The following is a 2 clock cycle read latency with improve clock-to-out timing + + reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}}; + + always @(posedge clka) + if (rstb) + doutb_reg <= {RAM_WIDTH{1'b0}}; + else if (regceb) + doutb_reg <= ram_data; + + assign doutb = doutb_reg; + + end + endgenerate + + // The following function calculates the address width based on specified RAM depth + function integer clogb2; + input integer depth; + for (clogb2=0; depth>0; clogb2=clogb2+1) + depth = depth >> 1; + endfunction + +endmodule + +// The following is an instantiation template for bram_sdp_1ck +/* +// Xilinx Simple Dual Port Single Clock RAM + bram_sdp_1ck #( + .RAM_WIDTH(18), // Specify RAM data width + .RAM_DEPTH(1024), // Specify RAM depth (number of entries) + .RAM_PERFORMANCE("HIGH_PERFORMANCE"), // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" + .INIT_FILE("") // Specify name/location of RAM initialization file if using one (leave blank if not) + ) your_instance_name ( + .addra(addra), // Write address bus, width determined from RAM_DEPTH + .addrb(addrb), // Read address bus, width determined from RAM_DEPTH + .dina(dina), // RAM input data, width determined from RAM_WIDTH + .clka(clka), // Clock + .wea(wea), // Write enable + .enb(enb), // Read Enable, for additional power savings, disable when not in use + .rstb(rstb), // Output reset (does not affect memory contents) + .regceb(regceb), // Output register enable + .doutb(doutb) // RAM output data, width determined from RAM_WIDTH + ); +*/ diff --git a/piton/design/common/rtl/bram_tdp_1ck_wrfirst.v b/piton/design/common/rtl/bram_tdp_1ck_wrfirst.v new file mode 100644 index 000000000..c570136bd --- /dev/null +++ b/piton/design/common/rtl/bram_tdp_1ck_wrfirst.v @@ -0,0 +1,162 @@ +// Copyright 2022 Barcelona Supercomputing Center-Centro Nacional de Supercomputación + +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Alexander Kropotov, BSC-CNS +// Date: 22.02.2022 +// Description: +// Xilinx True Dual Port RAM, Write First with Single Clock (taken from Xilinx Vivado synthesis templates) +// This code implements a parameterizable true dual port memory (both ports can read and write). +// This implements write-first mode where the data being written to the RAM also resides on +// the output port. If the output data is not needed during writes or the last read value is +// desired to be retained, it is suggested to use no change as it is more power efficient. +// If a reset or enable is not necessary, it may be tied off or removed from the code. + +module bram_tdp_1ck_wrfirst #( + parameter RAM_WIDTH = 18, // Specify RAM data width + parameter RAM_DEPTH = 1024, // Specify RAM depth (number of entries) + parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" + parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not) +) ( + input [clogb2(RAM_DEPTH-1)-1:0] addra, // Port A address bus, width determined from RAM_DEPTH + input [clogb2(RAM_DEPTH-1)-1:0] addrb, // Port B address bus, width determined from RAM_DEPTH + input [RAM_WIDTH-1:0] dina, // Port A RAM input data + input [RAM_WIDTH-1:0] dinb, // Port B RAM input data + input clka, // Clock + input wea, // Port A write enable + input web, // Port B write enable + input ena, // Port A RAM Enable, for additional power savings, disable port when not in use + input enb, // Port B RAM Enable, for additional power savings, disable port when not in use + input rsta, // Port A output reset (does not affect memory contents) + input rstb, // Port B output reset (does not affect memory contents) + input regcea, // Port A output register enable + input regceb, // Port B output register enable + output [RAM_WIDTH-1:0] douta, // Port A RAM output data + output [RAM_WIDTH-1:0] doutb // Port B RAM output data +); + + reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0]; + reg [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}}; + reg [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}}; + + // actual read pipeline for inter-port write-first policy + reg [clogb2(RAM_DEPTH-1)-1:0] addra_rd; + reg [clogb2(RAM_DEPTH-1)-1:0] addrb_rd; + + // The following code either initializes the memory values to a specified file or to all zeros to match Xilinx hardware + generate + if (INIT_FILE == "xilinx_default_zeroes") // Explicit initialization with zeroes (power-up zero filling is not applicable for ASIC) + begin: init_bram_to_zero + integer ram_index; + initial + for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1) + BRAM[ram_index] = {RAM_WIDTH{1'b0}}; + end + else if (INIT_FILE != "") begin: use_init_file + initial + $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH-1); + end + endgenerate + + always @(posedge clka) + if (ena) + begin + addra_rd <= addra; + if (wea) begin + BRAM[addra] <= dina; + ram_data_a <= dina; + end else + ram_data_a <= BRAM[addra]; + end + // always @(*) ram_data_a = BRAM[addra_rd]; + + always @(posedge clka) + if (enb) + begin + addrb_rd <= addrb; + if (web) begin + BRAM[addrb] <= dinb; + ram_data_b <= dinb; + end else + ram_data_b <= BRAM[addrb]; + end + // always @(*) ram_data_b = BRAM[addrb_rd]; + + // The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register) + generate + if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register + + // The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing + assign douta = ram_data_a; + assign doutb = ram_data_b; + + end else begin: output_register + + // The following is a 2 clock cycle read latency with improve clock-to-out timing + + reg [RAM_WIDTH-1:0] douta_reg = {RAM_WIDTH{1'b0}}; + reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}}; + + always @(posedge clka) + if (rsta) + douta_reg <= {RAM_WIDTH{1'b0}}; + else if (regcea) + douta_reg <= ram_data_a; + + always @(posedge clka) + if (rstb) + doutb_reg <= {RAM_WIDTH{1'b0}}; + else if (regceb) + doutb_reg <= ram_data_b; + + assign douta = douta_reg; + assign doutb = doutb_reg; + + end + endgenerate + + // The following function calculates the address width based on specified RAM depth + function integer clogb2; + input integer depth; + for (clogb2=0; depth>0; clogb2=clogb2+1) + depth = depth >> 1; + endfunction + +endmodule + +// The following is an instantiation template for bram_tdp_1ck_wrfirst +/* + // Xilinx True Dual Port RAM, Write First with Single Clock + bram_tdp_1ck_wrfirst #( + .RAM_WIDTH(18), // Specify RAM data width + .RAM_DEPTH(1024), // Specify RAM depth (number of entries) + .RAM_PERFORMANCE("HIGH_PERFORMANCE"), // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" + .INIT_FILE("") // Specify name/location of RAM initialization file if using one (leave blank if not) + ) your_instance_name ( + .addra(addra), // Port A address bus, width determined from RAM_DEPTH + .addrb(addrb), // Port B address bus, width determined from RAM_DEPTH + .dina(dina), // Port A RAM input data, width determined from RAM_WIDTH + .dinb(dinb), // Port B RAM input data, width determined from RAM_WIDTH + .clka(clka), // Clock + .wea(wea), // Port A write enable + .web(web), // Port B write enable + .ena(ena), // Port A RAM Enable, for additional power savings, disable port when not in use + .enb(enb), // Port B RAM Enable, for additional power savings, disable port when not in use + .rsta(rsta), // Port A output reset (does not affect memory contents) + .rstb(rstb), // Port B output reset (does not affect memory contents) + .regcea(regcea), // Port A output register enable + .regceb(regceb), // Port B output register enable + .douta(douta), // Port A RAM output data, width determined from RAM_WIDTH + .doutb(doutb) // Port B RAM output data, width determined from RAM_WIDTH + ); +*/ diff --git a/piton/design/include/define.h.pyv b/piton/design/include/define.h.pyv index dd0a92420..2f160b031 100644 --- a/piton/design/include/define.h.pyv +++ b/piton/design/include/define.h.pyv @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // Copyright (c) 2015 Princeton University // All rights reserved. // @@ -57,6 +58,8 @@ from pyhplib import * print("`define PITON_NUM_TILES %d" % PITON_NUM_TILES) print("`define PITON_X_TILES %d" % PITON_X_TILES) print("`define PITON_Y_TILES %d" % PITON_Y_TILES) +if PITON_EXTRA_MEMS > 0: + print("`define PITON_EXTRA_MEMS %d" % PITON_EXTRA_MEMS) %> // NoC interface @@ -121,6 +124,8 @@ print("`define PITON_Y_TILES %d" % PITON_Y_TILES) `define MSG_ADDR 119:80 `define MSG_AMO_MASK1 135:128 +`define MSG_INI_Y 138:136 +`define MSG_INI_X 141:139 `define MSG_LSID 147:142 `define MSG_SDID 157:148 `define MSG_SRC_FBITS 161:158 @@ -141,6 +146,8 @@ print("`define PITON_Y_TILES %d" % PITON_Y_TILES) // HEADER 3 `define MSG_AMO_MASK1_ 7:0 +`define MSG_INI_Y_ 10:8 +`define MSG_INI_X_ 13:11 `define MSG_LSID_ 19:14 // 147-128:142-128 `define MSG_SDID_ 29:20 `define MSG_OPTIONS_3_ 29:0 @@ -310,6 +317,8 @@ print("`define PITON_Y_TILES %d" % PITON_Y_TILES) `define MSG_SRC_NODEID_WIDTH `NOC_NODEID_WIDTH `define MSG_MSHRID_WIDTH 8 `define MSG_L2_MISS_BITS 1 +`define MSG_INI_X_WIDTH 3 +`define MSG_INI_Y_WIDTH 3 //Transition data size `define MSG_DATA_SIZE_WIDTH 3 diff --git a/piton/design/include/piton_system.vh b/piton/design/include/piton_system.vh index 5b6618fd8..f34ce516a 100644 --- a/piton/design/include/piton_system.vh +++ b/piton/design/include/piton_system.vh @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // Copyright (c) 2015 Princeton University // All rights reserved. // @@ -118,6 +119,8 @@ `define PITON_CHIPSET_DIFF_CLK `elsif VCU118_BOARD `define PITON_CHIPSET_DIFF_CLK +`elsif ALVEO_BOARD + `define PITON_CHIPSET_DIFF_CLK `elsif XUPP3R_BOARD `define PITON_CHIPSET_DIFF_CLK `elsif GENESYS2_BOARD @@ -143,6 +146,11 @@ `undef PITON_FPGA_SD_BOOT `undef PITONSYS_SPI `define PITONSYS_AXI4_MEM +`elsif ALVEO_BOARD + `undef PITON_FPGA_SD_BOOT + `undef PITONSYS_SPI + `define PITONSYS_AXI4_MEM + `define PITONSYS_PCIE `endif // If PITON_FPGA_SD_BOOT is set we should always include SPI @@ -159,4 +167,6 @@ `define PITONSYS_DDR4 `elsif XUPP3R_BOARD `define PITONSYS_DDR4 +`elsif ALVEO_BOARD + `define PITONSYS_DDR4 `endif diff --git a/piton/design/rtl/system.v b/piton/design/rtl/system.v index e0ed161ac..3495e042d 100644 --- a/piton/design/rtl/system.v +++ b/piton/design/rtl/system.v @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // Copyright (c) 2015 Princeton University // All rights reserved. // @@ -142,7 +143,9 @@ module system( input sys_clk, `endif +`ifndef ALVEO_BOARD input sys_rst_n, +`endif `ifndef PITON_FPGA_SYNTH input pll_rst_n, @@ -181,11 +184,13 @@ module system( `ifndef NEXYSVIDEO_BOARD `ifndef XUPP3R_BOARD `ifndef F1_BOARD +`ifndef ALVEO_BOARD input tck_i, input tms_i, input trst_ni, input td_i, output td_o, +`endif//ALVEO_BOARD `endif//F1_BOARD `endif//XUPP3R_BOARD `endif //NEXYSVIDEO_BOARD @@ -208,6 +213,7 @@ module system( `ifndef F1_BOARD // Generalized interface for any FPGA board we support. // Not all signals will be used for all FPGA boards (see constraints) + `ifndef PITON_FPGA_MC_HBM `ifdef PITONSYS_DDR4 output ddr_act_n, output [`DDR3_BG_WIDTH-1:0] ddr_bg, @@ -219,19 +225,31 @@ module system( output [`DDR3_ADDR_WIDTH-1:0] ddr_addr, output [`DDR3_BA_WIDTH-1:0] ddr_ba, + `ifdef ALVEO_BOARD + output [`DDR3_CK_WIDTH-1:0] ddr_ck_c, + output [`DDR3_CK_WIDTH-1:0] ddr_ck_t, + `else output [`DDR3_CK_WIDTH-1:0] ddr_ck_n, output [`DDR3_CK_WIDTH-1:0] ddr_ck_p, + `endif output [`DDR3_CKE_WIDTH-1:0] ddr_cke, output ddr_reset_n, inout [`DDR3_DQ_WIDTH-1:0] ddr_dq, + `ifdef ALVEO_BOARD + inout [`DDR3_DQS_WIDTH-1:0] ddr_dqs_c, + inout [`DDR3_DQS_WIDTH-1:0] ddr_dqs_t, + `else inout [`DDR3_DQS_WIDTH-1:0] ddr_dqs_n, inout [`DDR3_DQS_WIDTH-1:0] ddr_dqs_p, + `endif `ifndef NEXYSVIDEO_BOARD output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 `ifdef XUPP3R_BOARD output ddr_parity, + `elsif ALVEO_BOARD + output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // XUPP3R_BOARD @@ -239,6 +257,7 @@ module system( output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 output [`DDR3_ODT_WIDTH-1:0] ddr_odt, + `endif // `ifndef PITON_FPGA_MC_HBM `else //ifndef F1_BOARD input mc_clk, // AXI Write Address Channel Signals @@ -346,7 +365,21 @@ module system( inout net_phy_mdio_io, output net_phy_mdc, `endif -`endif // PITON_FPGA_ETHERNETLITE +`elsif PITON_FPGA_ETH_CMAC // PITON_FPGA_ETHERNETLITE + `ifdef ALVEO_BOARD + // GTY quads connected to QSFP unit on Alveo board + input qsfp0_ref_clk_n, + input qsfp0_ref_clk_p, + + input qsfp1_ref_clk_n, + input qsfp1_ref_clk_p, + + input [3:0] qsfp_4x_grx_n, + input [3:0] qsfp_4x_grx_p, + output [3:0] qsfp_4x_gtx_n, + output [3:0] qsfp_4x_gtx_p, + `endif +`endif // PITON_FPGA_ETH_CMAC `endif // endif PITONSYS_IOCTRL `ifdef GENESYS2_BOARD @@ -386,12 +419,24 @@ module system( input [3:0] sw, `elsif XUPP3R_BOARD // no switches :( +`elsif ALVEO_BOARD + // no switches :( `else input [7:0] sw, `endif `ifdef XUPP3R_BOARD output [3:0] leds +`elsif ALVEO_BOARD + // no leds, but HBM Catastrophic Over temperature Out, should be tied to 0 to avoid problems when HBM is not used + input [15:0] pci_express_x16_rxn, + input [15:0] pci_express_x16_rxp, + output [15:0] pci_express_x16_txn, + output [15:0] pci_express_x16_txp, + input pcie_perstn, + input pcie_refclk_n, + input pcie_refclk_p, + output hbm_cattrip `else output [7:0] leds `endif @@ -474,6 +519,16 @@ wire offchip_processor_noc3_valid; wire [`NOC_DATA_WIDTH-1:0] offchip_processor_noc3_data; wire offchip_processor_noc3_yummy; +`ifdef PITON_EXTRA_MEMS + wire [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] processor_mcx_noc2_data; + wire [`PITON_EXTRA_MEMS-1:0] processor_mcx_noc2_valid; + wire [`PITON_EXTRA_MEMS-1:0] processor_mcx_noc2_yummy; + + wire [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] mcx_processor_noc3_data; + wire [`PITON_EXTRA_MEMS-1:0] mcx_processor_noc3_valid; + wire [`PITON_EXTRA_MEMS-1:0] mcx_processor_noc3_yummy; +`endif + // Passthru<->chipset source synchronous differential clocks `ifdef PITON_CHIPSET_CLKS_GEN wire chipset_passthru_clk_p; @@ -560,10 +615,41 @@ assign rtc = rtc_div[6]; assign uart_rts = 1'b0; `endif // VCU118_BOARD +`ifdef ALVEO_BOARD +wire [4:0] sw; +wire [4:0] pcie_gpio; +wire mem_calib_complete; +wire [7:0] leds; +reg hold_start; +// vio_sw vio_sw_i ( +// .clk(core_ref_clk), +// .probe_out0(sw[0]), +// .probe_out1(sw[1]), +// .probe_out2(sw[2]), +// .probe_out3(sw[3]), +// .probe_out4(sw[4]) +// ); + assign sw[3] = pcie_gpio[0]; //sys_rst_n + assign sw[4] = pcie_gpio[1]; // chip_rst_n + assign sw[0] = pcie_gpio[2]; // uart_boot_en + assign sw[2] = pcie_gpio[3]; // bootrom_linux + assign sw[1] = pcie_gpio[4]; // timeout_en + + // sw[4] = 1, test_start works as usual. + // sw[4] = 0, tile stays on reset until going high. + // 0) UART_BOOT_EN set to low (sw[0]), bootrom_Ariane (sw[2]=0), timeout low sw[1] + // 1) reset the fpga (sw[3]). + // 2) Load the Linux BBL via PCIe to address 0x8000_0000 (if UART_BOOT_EN = '1', this address is 0x0) + // 3) Active hold_start (sw[4]='1'), letting the RISC-V boot. +`endif + + // Different reset active levels for different boards always @ * begin -`ifdef PITON_FPGA_RST_ACT_HIGH +`ifdef ALVEO_BOARD + sys_rst_n_rect = sw[3]; +`elsif PITON_FPGA_RST_ACT_HIGH sys_rst_n_rect = ~sys_rst_n; `else // ifndef PITON_FPGA_RST_ACT_HIGH sys_rst_n_rect = sys_rst_n; @@ -577,7 +663,14 @@ always @ * begin chip_rst_n = sys_rst_n_rect & passthru_chip_rst_n; `ifdef PITONSYS_UART_BOOT + `ifndef ALVEO_BOARD chip_rst_n = chip_rst_n & test_start; + `else + hold_start = sw[4] & test_start; + chip_rst_n = chip_rst_n & hold_start; + `endif +`elsif ALVEO_BOARD // PYTONSYS_UART_BOOT + chip_rst_n = chip_rst_n & sw[4]; `endif `ifdef PITONSYS_UART_RESET chip_rst_n = chip_rst_n & uart_rst_out_n; @@ -602,7 +695,11 @@ begin // part of system). Current boards supported // for passthru only use active low, so it always // expects active low +`ifndef ALVEO_BOARD chipset_rst_n = sys_rst_n; +`else + chipset_rst_n = sw[3]; +`endif end // If there is no passthru, we need to set the resets @@ -644,6 +741,18 @@ assign passthru_pll_rst_n = 1'b1; // .TDO(td_o) // 1-bit input: Test Data Output (TDO) input for USER function. // ); // `endif +`ifdef ALVEO_BOARD + wire tck_i, tms_i, td_i, td_o; + // hook the RISC-V JTAG TAP into the FPGA JTAG chain + jtag_shell jtag_shell ( + .dbg_jtag_tck(tck_i), + .dbg_jtag_tms(tms_i), + .dbg_jtag_tdi(td_i), + .dbg_jtag_tdo(td_o), + .dbghub_clk(core_ref_clk) // Using Core clock as some free-running clock for Debug Hub + ); + wire trst_ni = 1'b1; +`endif `ifdef VC707_BOARD wire tck_i, tms_i, trst_ni, td_i, td_o; @@ -810,6 +919,18 @@ chip chip( .offchip_processor_noc3_data (offchip_processor_noc3_data), .offchip_processor_noc3_yummy (offchip_processor_noc3_yummy) `endif // endif PITON_NO_CHIP_BRIDGE + + `ifdef PITON_EXTRA_MEMS + , + .processor_mcx_noc2_data (processor_mcx_noc2_data), + .processor_mcx_noc2_valid(processor_mcx_noc2_valid), + .processor_mcx_noc2_yummy(processor_mcx_noc2_yummy), + + .mcx_processor_noc3_data (mcx_processor_noc3_data), + .mcx_processor_noc3_valid(mcx_processor_noc3_valid), + .mcx_processor_noc3_yummy(mcx_processor_noc3_yummy) + `endif + `ifdef PITON_RV64_PLATFORM `ifdef PITON_RV64_DEBUGUNIT // Debug @@ -941,6 +1062,16 @@ chipset chipset( // 250MHz diff input ref clock for DDR4 memory controller `ifdef PITONSYS_DDR4 + `ifdef PITONSYS_PCIE + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_gpio(pcie_gpio), + .pcie_perstn(pcie_perstn), + .pcie_refclk_n(pcie_refclk_n), + .pcie_refclk_p(pcie_refclk_p), + `endif .mc_clk_p(mc_clk_p), .mc_clk_n(mc_clk_n), `endif // PITONSYS_DDR4 @@ -1042,10 +1173,21 @@ chipset chipset( .chip_intf_credit_back(chip_intf_credit_back), `endif // endif PITON_NO_CHIP_BRIDGE PITON_SYS_INC_PASSTHRU + `ifdef PITON_EXTRA_MEMS + .processor_mcx_noc2_data (processor_mcx_noc2_data), + .processor_mcx_noc2_valid(processor_mcx_noc2_valid), + .processor_mcx_noc2_yummy(processor_mcx_noc2_yummy), + + .mcx_processor_noc3_data (mcx_processor_noc3_data), + .mcx_processor_noc3_valid(mcx_processor_noc3_valid), + .mcx_processor_noc3_yummy(mcx_processor_noc3_yummy), + `endif + // DRAM and I/O interfaces `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 `ifndef F1_BOARD +`ifndef PITON_FPGA_MC_HBM `ifdef PITONSYS_DDR4 .ddr_act_n(ddr_act_n), .ddr_bg(ddr_bg), @@ -1056,22 +1198,33 @@ chipset chipset( `endif // PITONSYS_DDR4 .ddr_addr(ddr_addr), .ddr_ba(ddr_ba), +`ifndef ALVEO_BOARD .ddr_ck_n(ddr_ck_n), .ddr_ck_p(ddr_ck_p), +`endif .ddr_cke(ddr_cke), .ddr_reset_n(ddr_reset_n), .ddr_dq(ddr_dq), +`ifndef ALVEO_BOARD .ddr_dqs_n(ddr_dqs_n), .ddr_dqs_p(ddr_dqs_p), +`endif `ifndef NEXYSVIDEO_BOARD .ddr_cs_n(ddr_cs_n), `endif // endif NEXYSVIDEO_BOARD `ifdef XUPP3R_BOARD .ddr_parity(ddr_parity), +`elsif ALVEO_BOARD + .ddr_parity(ddr_parity), + .ddr_ck_n(ddr_ck_c), + .ddr_ck_p(ddr_ck_t), + .ddr_dqs_n(ddr_dqs_c), + .ddr_dqs_p(ddr_dqs_t), `else .ddr_dm(ddr_dm), `endif .ddr_odt(ddr_odt), +`endif // `ifndef PITON_FPGA_MC_HBM `else //ifndef F1_BOARD .mc_clk(mc_clk), // AXI Write Address Channel Signals @@ -1167,8 +1320,20 @@ chipset chipset( .net_phy_rst_n (net_phy_rst_n), .net_phy_mdio_io (net_phy_mdio_io), .net_phy_mdc (net_phy_mdc), - - `endif // PITON_FPGA_ETHERNETLITE + `elsif PITON_FPGA_ETH_CMAC // PITON_FPGA_ETHERNETLITE + // GTY quads connected to QSFP unit on Alveo board + `ifdef PITON_FPGA_ETH_PORT1 + .qsfp_ref_clk_n (qsfp1_ref_clk_n), + .qsfp_ref_clk_p (qsfp1_ref_clk_p), + `else + .qsfp_ref_clk_n (qsfp0_ref_clk_n), + .qsfp_ref_clk_p (qsfp0_ref_clk_p), + `endif + .qsfp_4x_grx_n (qsfp_4x_grx_n), + .qsfp_4x_grx_p (qsfp_4x_grx_p), + .qsfp_4x_gtx_n (qsfp_4x_gtx_n), + .qsfp_4x_gtx_p (qsfp_4x_gtx_p), + `endif // PITON_FPGA_ETH_CMAC `endif // endif PITONSYS_IOCTRL `ifdef GENESYS2_BOARD @@ -1204,7 +1369,12 @@ chipset chipset( `endif `ifndef XUPP3R_BOARD +`ifdef ALVEO_BOARD + .hbm_cattrip(hbm_cattrip), + .sw(sw[2:0]), +`else .sw(sw), +`endif `endif .leds(leds) diff --git a/piton/design/xilinx/alveou250/constraints.xdc b/piton/design/xilinx/alveou250/constraints.xdc new file mode 100644 index 000000000..c65c46868 --- /dev/null +++ b/piton/design/xilinx/alveou250/constraints.xdc @@ -0,0 +1,144 @@ +# Modified by Barcelona Supercomputing Center on March 3rd, 2024 +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#----------------- System Clock ------------------- +# 2) SI335A - SiLabs SI5335A-B06201-GM Selectable output Oscillator 156.2500Mhz/161.1328125Mhz For QSFP0 REFCLK1 +# +# - OUT0--> SYSCLK_300_P/SYSCLK_300_N @ 300.0000Mhz to 1-to-4 Clock buffer (Fixed and Unchanged by FS[1:0]) +# | +# |--> SI53340-B-GM --> OUT0 SYSCLK0_300_P/SYSCLK0_300_N 300.000Mhz - System Clock for first DDR4 MIG interface +# | PINS: IO_L13P_T2L_N0_GC_QBC_63_AY37/IO_L13N_T2L_N1_GC_QBC_63_AY38 +# | +# |-> OUT1 SYSCLK1_300_P/SYSCLK1_300_N 300.000Mhz - System Clock for second DDR4 MIG interface. +# | PINS: IO_L11P_T1U_N8_GC_64_AW20/IO_L11N_T1U_N9_GC_64_AW19 +# | +# |-> OUT2 SYSCLK2_300_P/SYSCLK2_300_N 300.000Mhz - System Clock for third DDR4 MIG interface. +# | PINS: IO_L13P_T2L_N0_GC_QBC_70_F32/IO_L13N_T2L_N1_GC_QBC_70_E32 +# | +# |-> OUT3 SYSCLK3_300_P/SYSCLK3_300_N 300.000Mhz - System Clock for fourth DDR4 MIG interface. +# PINS: IO_L13P_T2L_N0_GC_QBC_72_J16/IO_L13N_T2L_N1_GC_QBC_72_H16 +# +# set_property -dict {PACKAGE_PIN AY38 IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK0_300_N ]; # Bank 42 VCCO - VCC1V2 Net "SYSCLK0_300_N" - IO_L13N_T2L_N1_GC_QBC_42 +# set_property -dict {PACKAGE_PIN AY37 IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK0_300_P ]; # Bank 42 VCCO - VCC1V2 Net "SYSCLK0_300_P" - IO_L13P_T2L_N0_GC_QBC_42 +# set_property -dict {PACKAGE_PIN AW19 IOSTANDARD LVDS } [get_ports SYSCLK1_300_N ]; # Bank 64 VCCO - VCC1V2 Net "SYSCLK1_300_N" - IO_L11N_T1U_N9_GC_64 +# set_property -dict {PACKAGE_PIN AW20 IOSTANDARD LVDS } [get_ports SYSCLK1_300_P ]; # Bank 64 VCCO - VCC1V2 Net "SYSCLK1_300_P" - IO_L11P_T1U_N8_GC_64 +# set_property -dict {PACKAGE_PIN E32 IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK2_300_N ]; # Bank 47 VCCO - VCC1V2 Net "SYSCLK2_300_N" - IO_L13N_T2L_N1_GC_QBC_47 +# set_property -dict {PACKAGE_PIN F32 IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK2_300_P ]; # Bank 47 VCCO - VCC1V2 Net "SYSCLK2_300_P" - IO_L13P_T2L_N0_GC_QBC_47 +# set_property -dict {PACKAGE_PIN H16 IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK3_300_N ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_N" - IO_L13N_T2L_N1_GC_QBC_70 +# set_property -dict {PACKAGE_PIN J16 IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK3_300_P ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_P" - IO_L13P_T2L_N0_GC_QBC_70 +set_property -dict {PACKAGE_PIN E32 IOSTANDARD DIFF_POD12_DCI } [get_ports chipset_clk_osc_n ]; # Bank 47 VCCO - VCC1V2 Net "SYSCLK2_300_N" - IO_L13N_T2L_N1_GC_QBC_47 +set_property -dict {PACKAGE_PIN F32 IOSTANDARD DIFF_POD12_DCI } [get_ports chipset_clk_osc_p ]; # Bank 47 VCCO - VCC1V2 Net "SYSCLK2_300_P" - IO_L13P_T2L_N0_GC_QBC_47 +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets chipset/clk_mmcm/inst/clkin1_ibufds/O] +set chip_clk [get_clocks -of_objects [get_pins -hierarchical clk_mmcm/chipset_clk]] +#-------------------------------------------- + +#----------------- PCIe signals ------------------- +#PCIE_PERSTN Active low input from PCIe Connector to Ultrascale+ Device to detect presence. +set_property -dict {PACKAGE_PIN BD21 IOSTANDARD LVCMOS12} [get_ports pcie_perstn]; # Bank 64 VCCO - VCC1V2 Net "PCIE_PERST_LS" - IO_L23P_T3U_N8_64 +set_property PACKAGE_PIN AM10 [get_ports pcie_refclk_n]; # Bank 226 Net "PEX_REFCLK_C_N" - MGTREFCLK0N_226 +set_property PACKAGE_PIN AM11 [get_ports pcie_refclk_p]; # Bank 226 Net "PEX_REFCLK_C_P" - MGTREFCLK0P_226 +create_clock -period 10.000 -name PCIE_CLK [get_ports pcie_refclk_p] + +# Timing constraints for clock domains crossings (CDC) +set qdma_clk [get_clocks -of_objects [get_pins -hierarchical qdma_0/axi_aclk]] +# set_false_path -from $xxx_clk -to $yyy_clk +# controlling resync paths to be less than source clock period +# (-datapath_only to exclude clock paths) +set_max_delay -datapath_only -from $qdma_clk -to $chip_clk [expr [get_property -min period $qdma_clk] * 0.9] + +# Specifying the placement of PCIe clock domain modules into single SLR to facilitate routing +# https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug912-vivado-properties.pdf#page=386 +#Collecting all units from correspondingly PCIe domain, +set pcie_clk_units [get_cells -of_objects [get_nets -of_objects [get_pins -hierarchical qdma_0/axi_aclk]]] +#Setting specific SLR to which PCIe pins are wired since placer may miss it if just "group_name" is applied +set_property USER_SLR_ASSIGNMENT SLR1 [get_cells "$pcie_clk_units"] +#-------------------------------------------- + +#----------------- DRAM related constarints ------------------- +# HBM Catastrophic Over temperature Output signal to Satellite Controller +# HBM_CATTRIP Active high indicator to Satellite controller to indicate the HBM has exceeded its maximum allowable temperature. +# This signal is not a dedicated Ultrascale+ Device output and is a derived signal in RTL. Making the signal Active will shut +# the Ultrascale+ Device power rails off. +# +# From UG1314 (Alveo U280 Data Center Accelerator Card User Guide): +# WARNING! When creating a design for this card, it is necessary to drive the CATTRIP pin. +# This pin is monitored by the card's satellite controller (SC) and represents the HBM_CATRIP (HBM +# catastrophic temperature failure). When instantiating the HBM IP in your design, the two HBM IP signals, +# DRAM_0_STAT_CATTRIP and DRAM_1_STAT_CATTRIP, must be ORed together and connected to this pin for +# proper card operation. If the pin is undefined it will be pulled High by the card causing the SC to infer a CATRIP +# failure and shut power down to the card. +# If you do not use the HBM IP in your design, you must drive the pin Low to avoid the SC shutting down the card. +# If the pin is undefined and the QSPI is programmed with the MCS file, there is a potential chance that the card +# will continuously power down and reset after the bitstream is loaded. This can result in the card being unusable. +# ------------------------------------------------------------------------ +# hbm_cattrip is not required for u250 since it doesn't support HBM. +# but for saving maximum compatibility in verilog sources connecting it to unsed port. +# ------------------------------------------------------------------------ +set_property PACKAGE_PIN AR20 [get_ports hbm_cattrip]; # Bank 64 VCCO - VCC1V8 Net "GPIO_MSP0" - IO_T0U_N12_VRP_64 +set_property IOSTANDARD LVCMOS12 [get_ports hbm_cattrip]; # Bank 64 VCCO - VCC1V8 Net "GPIO_MSP0" - IO_T0U_N12_VRP_64 +# ------- DRAM reference clock +set_property -dict {PACKAGE_PIN AW19 IOSTANDARD LVDS} [get_ports mc_clk_n]; # Bank 64 VCCO - VCC1V2 Net "SYSCLK1_300_N" - IO_L11N_T1U_N9_GC_64 +set_property -dict {PACKAGE_PIN AW20 IOSTANDARD LVDS} [get_ports mc_clk_p]; # Bank 64 VCCO - VCC1V2 Net "SYSCLK1_300_P" - IO_L11P_T1U_N8_GC_64 +#create_clock is needed in case of passing MEM_CLK through diff buffer (for HBM) +# create_clock -period 3.3333 -name MEM_CLK [get_ports "mc_clk_p"] +#-------------------------------------------- +# Timing constraints for CDC in SDRAM user interface, particularly in HBM APB which is disabled but clocked by fixed mem ref clock +set mref_clk [get_clocks -of_objects [get_pins -hierarchical meep_shell/mem_refclk_clk_p]] +# set_false_path -from $xxx_clk -to $yyy_clk +# controlling resync paths to be less than source clock period +# (-datapath_only to exclude clock paths) +set_max_delay -datapath_only -from $chip_clk -to $mref_clk [expr [get_property -min period $chip_clk] * 0.9] +set_max_delay -datapath_only -from $mref_clk -to $chip_clk [expr [get_property -min period $mref_clk] * 0.9] +#-------------------------------------------- + +#----------------- JTAG CDC ------------------- +# Timing constraints for clock domains crossings (CDC) +set jtag_clk [get_clocks -of_objects [get_pins -hierarchical jtag_shell/dbg_jtag_tck]] +# set_false_path -from $xxx_clk -to $yyy_clk +# controlling resync paths to be less than source clock period +# (-datapath_only to exclude clock paths) +# For JTAG clock we consider both edges +set_max_delay -datapath_only -from $chip_clk -to $jtag_clk [expr [get_property -min period $chip_clk] * 0.9 ] +set_max_delay -datapath_only -from $jtag_clk -to $chip_clk [expr [get_property -min period $jtag_clk] * 0.9 / 2] +#-------------------------------------------- + +#----------------- UART ------------------- +set_property -dict {PACKAGE_PIN BB20 IOSTANDARD LVCMOS12} [get_ports uart_tx]; # Bank 64 VCCO - VCC1V2 Net "USB_UART_RX" - IO_T3U_N12_64 +set_property -dict {PACKAGE_PIN BF18 IOSTANDARD LVCMOS12} [get_ports uart_rx]; # Bank 64 VCCO - VCC1V2 Net "USB_UART_TX" - IO_L24N_T3U_N11_64 +#-------------------------------------------- + +#----------------- Bitstream Configuration ------------------- +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] +# -------------------------------------------------------------- diff --git a/piton/design/xilinx/alveou250/ddr4.xdc b/piton/design/xilinx/alveou250/ddr4.xdc new file mode 100644 index 000000000..5508bd945 --- /dev/null +++ b/piton/design/xilinx/alveou250/ddr4.xdc @@ -0,0 +1,164 @@ +#-------------------------------------------- +# Timing constraints for CDC in DDR SDRAM user interface, particularly in NOC - DDR AXI transition (fifo, reset) +set sys_ck [get_clocks -of_objects [get_pins -hierarchical meep_shell/sys_clk]] +set mem_ck [get_clocks -of_objects [get_pins -hierarchical meep_shell/mem_clk]] +# set_false_path -from $xxx_clk -to $yyy_clk +# controlling resync paths to be less than source clock period +# (-datapath_only to exclude clock paths) +set_max_delay -datapath_only -from $mem_ck -to $sys_ck [expr [get_property -min period $mem_ck] * 0.9] +set_max_delay -datapath_only -from $sys_ck -to $mem_ck [expr [get_property -min period $sys_ck] * 0.9] +#-------------------------------------------- + +#-------------------------------------------- +## DDR4 RDIMM Controller 1, 72-bit Data Interface, x4 Componets, Single Rank +## <<>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order: +## JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 +## Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +## +set_property -dict {PACKAGE_PIN AN13 IOSTANDARD POD12_DCI } [get_ports ddr_dq[24] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ24" - IO_L23N_T3U_N9_67 +set_property -dict {PACKAGE_PIN AM13 IOSTANDARD POD12_DCI } [get_ports ddr_dq[26] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ26" - IO_L23P_T3U_N8_67 +set_property -dict {PACKAGE_PIN AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[6] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C3" - IO_L22N_T3U_N7_DBC_AD0N_67 +set_property -dict {PACKAGE_PIN AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[6] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T3" - IO_L22P_T3U_N6_DBC_AD0P_67 +set_property -dict {PACKAGE_PIN AR13 IOSTANDARD POD12_DCI } [get_ports ddr_dq[25] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ25" - IO_L24N_T3U_N11_67 +set_property -dict {PACKAGE_PIN AP13 IOSTANDARD POD12_DCI } [get_ports ddr_dq[27] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ27" - IO_L24P_T3U_N10_67 +set_property -dict {PACKAGE_PIN AM14 IOSTANDARD POD12_DCI } [get_ports ddr_dq[28] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ28" - IO_L21N_T3L_N5_AD8N_67 +set_property -dict {PACKAGE_PIN AL14 IOSTANDARD POD12_DCI } [get_ports ddr_dq[30] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ30" - IO_L21P_T3L_N4_AD8P_67 +set_property -dict {PACKAGE_PIN AT15 IOSTANDARD POD12_DCI } [get_ports ddr_dq[31] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ31" - IO_L20N_T3L_N3_AD1N_67 +set_property -dict {PACKAGE_PIN AR15 IOSTANDARD POD12_DCI } [get_ports ddr_dq[29] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ29" - IO_L20P_T3L_N2_AD1P_67 +set_property -dict {PACKAGE_PIN AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[7] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C12" - IO_L19N_T3L_N1_DBC_AD9N_67 +set_property -dict {PACKAGE_PIN AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[7] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T12" - IO_L19P_T3L_N0_DBC_AD9P_67 +set_property -dict {PACKAGE_PIN AV13 IOSTANDARD POD12_DCI } [get_ports ddr_dq[9] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ9" - IO_L17N_T2U_N9_AD10N_67 +set_property -dict {PACKAGE_PIN AU13 IOSTANDARD POD12_DCI } [get_ports ddr_dq[8] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ8" - IO_L17P_T2U_N8_AD10P_67 +set_property -dict {PACKAGE_PIN AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[2] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C1" - IO_L16N_T2U_N7_QBC_AD3N_67 +set_property -dict {PACKAGE_PIN AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[2] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T1" - IO_L16P_T2U_N6_QBC_AD3P_67 +set_property -dict {PACKAGE_PIN AW13 IOSTANDARD POD12_DCI } [get_ports ddr_dq[10] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ10" - IO_L18N_T2U_N11_AD2N_67 +set_property -dict {PACKAGE_PIN AW14 IOSTANDARD POD12_DCI } [get_ports ddr_dq[11] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ11" - IO_L18P_T2U_N10_AD2P_67 +set_property -dict {PACKAGE_PIN AV14 IOSTANDARD POD12_DCI } [get_ports ddr_dq[14] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ14" - IO_L15N_T2L_N5_AD11N_67 +set_property -dict {PACKAGE_PIN AU14 IOSTANDARD POD12_DCI } [get_ports ddr_dq[12] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ12" - IO_L15P_T2L_N4_AD11P_67 +set_property -dict {PACKAGE_PIN BA11 IOSTANDARD POD12_DCI } [get_ports ddr_dq[15] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ15" - IO_L14N_T2L_N3_GC_67 +set_property -dict {PACKAGE_PIN AY11 IOSTANDARD POD12_DCI } [get_ports ddr_dq[13] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ13" - IO_L14P_T2L_N2_GC_67 +set_property -dict {PACKAGE_PIN AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[3] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C10" - IO_L13N_T2L_N1_GC_QBC_67 +set_property -dict {PACKAGE_PIN AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[3] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T10" - IO_L13P_T2L_N0_GC_QBC_67 +set_property -dict {PACKAGE_PIN BA13 IOSTANDARD POD12_DCI } [get_ports ddr_dq[18] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ18" - IO_L11N_T1U_N9_GC_67 +set_property -dict {PACKAGE_PIN BA14 IOSTANDARD POD12_DCI } [get_ports ddr_dq[19] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ19" - IO_L11P_T1U_N8_GC_67 +set_property -dict {PACKAGE_PIN BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[4] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_67 +set_property -dict {PACKAGE_PIN BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[4] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_67 +set_property -dict {PACKAGE_PIN BB12 IOSTANDARD POD12_DCI } [get_ports ddr_dq[17] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ17" - IO_L12N_T1U_N11_GC_67 +set_property -dict {PACKAGE_PIN BA12 IOSTANDARD POD12_DCI } [get_ports ddr_dq[16] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ16" - IO_L12P_T1U_N10_GC_67 +set_property -dict {PACKAGE_PIN BA7 IOSTANDARD POD12_DCI } [get_ports ddr_dq[22] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ22" - IO_L9N_T1L_N5_AD12N_67 +set_property -dict {PACKAGE_PIN BA8 IOSTANDARD POD12_DCI } [get_ports ddr_dq[23] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ23" - IO_L9P_T1L_N4_AD12P_67 +set_property -dict {PACKAGE_PIN BC9 IOSTANDARD POD12_DCI } [get_ports ddr_dq[20] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ20" - IO_L8N_T1L_N3_AD5N_67 +set_property -dict {PACKAGE_PIN BB9 IOSTANDARD POD12_DCI } [get_ports ddr_dq[21] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ21" - IO_L8P_T1L_N2_AD5P_67 +set_property -dict {PACKAGE_PIN BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[5] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_67 +set_property -dict {PACKAGE_PIN BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[5] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_67 +set_property -dict {PACKAGE_PIN BD7 IOSTANDARD POD12_DCI } [get_ports ddr_dq[1] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ1" - IO_L5N_T0U_N9_AD14N_67 +set_property -dict {PACKAGE_PIN BC7 IOSTANDARD POD12_DCI } [get_ports ddr_dq[2] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ2" - IO_L5P_T0U_N8_AD14P_67 +set_property -dict {PACKAGE_PIN BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[0] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_67 +set_property -dict {PACKAGE_PIN BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[0] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_67 +set_property -dict {PACKAGE_PIN BD8 IOSTANDARD POD12_DCI } [get_ports ddr_dq[3] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ3" - IO_L6N_T0U_N11_AD6N_67 +set_property -dict {PACKAGE_PIN BD9 IOSTANDARD POD12_DCI } [get_ports ddr_dq[0] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ0" - IO_L6P_T0U_N10_AD6P_67 +set_property -dict {PACKAGE_PIN BF7 IOSTANDARD POD12_DCI } [get_ports ddr_dq[7] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ7" - IO_L3N_T0L_N5_AD15N_67 +set_property -dict {PACKAGE_PIN BE7 IOSTANDARD POD12_DCI } [get_ports ddr_dq[6] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ6" - IO_L3P_T0L_N4_AD15P_67 +set_property -dict {PACKAGE_PIN BE10 IOSTANDARD POD12_DCI } [get_ports ddr_dq[5] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ5" - IO_L2N_T0L_N3_67 +set_property -dict {PACKAGE_PIN BD10 IOSTANDARD POD12_DCI } [get_ports ddr_dq[4] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ4" - IO_L2P_T0L_N2_67 +set_property -dict {PACKAGE_PIN BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[1] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C9" - IO_L1N_T0L_N1_DBC_67 +set_property -dict {PACKAGE_PIN BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[1] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T9" - IO_L1P_T0L_N0_DBC_67 +set_property -dict {PACKAGE_PIN AM15 IOSTANDARD POD12_DCI } [get_ports ddr_dq[56] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ56" - IO_L23N_T3U_N9_66 +set_property -dict {PACKAGE_PIN AL15 IOSTANDARD POD12_DCI } [get_ports ddr_dq[57] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ57" - IO_L23P_T3U_N8_66 +set_property -dict {PACKAGE_PIN AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[14]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C7" - IO_L22N_T3U_N7_DBC_AD0N_66 +set_property -dict {PACKAGE_PIN AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[14]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T7" - IO_L22P_T3U_N6_DBC_AD0P_66 +#set_property -dict {PACKAGE_PIN AN18 IOSTANDARD LVCMOS12 } [get_ports ddr_event_n ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_EVENT_B" - IO_T3U_N12_66 +set_property -dict {PACKAGE_PIN AN16 IOSTANDARD POD12_DCI } [get_ports ddr_dq[59] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ59" - IO_L24N_T3U_N11_66 +set_property -dict {PACKAGE_PIN AN17 IOSTANDARD POD12_DCI } [get_ports ddr_dq[58] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ58" - IO_L24P_T3U_N10_66 +set_property -dict {PACKAGE_PIN AL16 IOSTANDARD POD12_DCI } [get_ports ddr_dq[63] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ63" - IO_L21N_T3L_N5_AD8N_66 +set_property -dict {PACKAGE_PIN AL17 IOSTANDARD POD12_DCI } [get_ports ddr_dq[62] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ62" - IO_L21P_T3L_N4_AD8P_66 +set_property -dict {PACKAGE_PIN AR18 IOSTANDARD POD12_DCI } [get_ports ddr_dq[60] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ60" - IO_L20N_T3L_N3_AD1N_66 +set_property -dict {PACKAGE_PIN AP18 IOSTANDARD POD12_DCI } [get_ports ddr_dq[61] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ61" - IO_L20P_T3L_N2_AD1P_66 +set_property -dict {PACKAGE_PIN AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[15]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C16" - IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -dict {PACKAGE_PIN AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[15]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T16" - IO_L19P_T3L_N0_DBC_AD9P_66 +set_property -dict {PACKAGE_PIN AU16 IOSTANDARD POD12_DCI } [get_ports ddr_dq[50] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ50" - IO_L17N_T2U_N9_AD10N_66 +set_property -dict {PACKAGE_PIN AU17 IOSTANDARD POD12_DCI } [get_ports ddr_dq[51] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ51" - IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[12]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C6" - IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -dict {PACKAGE_PIN AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[12]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T6" - IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -dict {PACKAGE_PIN AR17 IOSTANDARD LVCMOS12 } [get_ports ddr_reset_n ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_RESET_N" - IO_T2U_N12_66 +set_property -dict {PACKAGE_PIN AV16 IOSTANDARD POD12_DCI } [get_ports ddr_dq[48] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ48" - IO_L18N_T2U_N11_AD2N_66 +set_property -dict {PACKAGE_PIN AV17 IOSTANDARD POD12_DCI } [get_ports ddr_dq[49] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ49" - IO_L18P_T2U_N10_AD2P_66 +set_property -dict {PACKAGE_PIN AT17 IOSTANDARD POD12_DCI } [get_ports ddr_dq[55] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ55" - IO_L15N_T2L_N5_AD11N_66 +set_property -dict {PACKAGE_PIN AT18 IOSTANDARD POD12_DCI } [get_ports ddr_dq[54] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ54" - IO_L15P_T2L_N4_AD11P_66 +set_property -dict {PACKAGE_PIN BB16 IOSTANDARD POD12_DCI } [get_ports ddr_dq[53] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ53" - IO_L14N_T2L_N3_GC_66 +set_property -dict {PACKAGE_PIN BB17 IOSTANDARD POD12_DCI } [get_ports ddr_dq[52] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ52" - IO_L14P_T2L_N2_GC_66 +set_property -dict {PACKAGE_PIN AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[13]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C15" - IO_L13N_T2L_N1_GC_QBC_66 +set_property -dict {PACKAGE_PIN AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[13]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T15" - IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN AY17 IOSTANDARD POD12_DCI } [get_ports ddr_dq[40] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ40" - IO_L11N_T1U_N9_GC_66 +set_property -dict {PACKAGE_PIN AY18 IOSTANDARD POD12_DCI } [get_ports ddr_dq[42] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ42" - IO_L11P_T1U_N8_GC_66 +set_property -dict {PACKAGE_PIN BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[10]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C5" - IO_L10N_T1U_N7_QBC_AD4N_66 +set_property -dict {PACKAGE_PIN BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[10]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T5" - IO_L10P_T1U_N6_QBC_AD4P_66 +set_property -dict {PACKAGE_PIN BA17 IOSTANDARD POD12_DCI } [get_ports ddr_dq[41] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ41" - IO_L12N_T1U_N11_GC_66 +set_property -dict {PACKAGE_PIN BA18 IOSTANDARD POD12_DCI } [get_ports ddr_dq[43] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ43" - IO_L12P_T1U_N10_GC_66 +set_property -dict {PACKAGE_PIN BB15 IOSTANDARD POD12_DCI } [get_ports ddr_dq[45] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ45" - IO_L9N_T1L_N5_AD12N_66 +set_property -dict {PACKAGE_PIN BA15 IOSTANDARD POD12_DCI } [get_ports ddr_dq[44] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ44" - IO_L9P_T1L_N4_AD12P_66 +set_property -dict {PACKAGE_PIN BD11 IOSTANDARD POD12_DCI } [get_ports ddr_dq[47] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ47" - IO_L8N_T1L_N3_AD5N_66 +set_property -dict {PACKAGE_PIN BC11 IOSTANDARD POD12_DCI } [get_ports ddr_dq[46] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ46" - IO_L8P_T1L_N2_AD5P_66 +set_property -dict {PACKAGE_PIN BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[11]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C14" - IO_L7N_T1L_N1_QBC_AD13N_66 +set_property -dict {PACKAGE_PIN BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[11]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T14" - IO_L7P_T1L_N0_QBC_AD13P_66 +set_property -dict {PACKAGE_PIN BD13 IOSTANDARD POD12_DCI } [get_ports ddr_dq[35] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ35" - IO_L5N_T0U_N9_AD14N_66 +set_property -dict {PACKAGE_PIN BD14 IOSTANDARD POD12_DCI } [get_ports ddr_dq[33] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ33" - IO_L5P_T0U_N8_AD14P_66 +set_property -dict {PACKAGE_PIN BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[8] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_66 +set_property -dict {PACKAGE_PIN BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[8] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_66 +set_property -dict {PACKAGE_PIN BF12 IOSTANDARD POD12_DCI } [get_ports ddr_dq[34] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ34" - IO_L6N_T0U_N11_AD6N_66 +set_property -dict {PACKAGE_PIN BE13 IOSTANDARD POD12_DCI } [get_ports ddr_dq[32] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ32" - IO_L6P_T0U_N10_AD6P_66 +set_property -dict {PACKAGE_PIN BD15 IOSTANDARD POD12_DCI } [get_ports ddr_dq[36] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ36" - IO_L3N_T0L_N5_AD15N_66 +set_property -dict {PACKAGE_PIN BD16 IOSTANDARD POD12_DCI } [get_ports ddr_dq[37] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ37" - IO_L3P_T0L_N4_AD15P_66 +set_property -dict {PACKAGE_PIN BF13 IOSTANDARD POD12_DCI } [get_ports ddr_dq[39] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ39" - IO_L2N_T0L_N3_66 +set_property -dict {PACKAGE_PIN BF14 IOSTANDARD POD12_DCI } [get_ports ddr_dq[38] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ38" - IO_L2P_T0L_N2_66 +set_property -dict {PACKAGE_PIN BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[9] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C13" - IO_L1N_T0L_N1_DBC_66 +set_property -dict {PACKAGE_PIN BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[9] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T13" - IO_L1P_T0L_N0_DBC_66 +set_property -dict {PACKAGE_PIN AM25 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[15] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR15" - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +set_property -dict {PACKAGE_PIN AL25 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[14] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR14" - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +set_property -dict {PACKAGE_PIN AP26 IOSTANDARD SSTL12_DCI } [get_ports ddr_ba[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BA1" - IO_T3U_N12_PERSTN0_65 +set_property -dict {PACKAGE_PIN AN26 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[3] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR3" - IO_L24N_T3U_N11_DOUT_CSO_B_65 +set_property -dict {PACKAGE_PIN AM26 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[10] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR10" - IO_L24P_T3U_N10_EMCCLK_65 +#set_property -dict {PACKAGE_PIN AP24 IOSTANDARD SSTL12_DCI } [get_ports ddr_odt[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ODT1" - IO_L21N_T3L_N5_AD8N_D07_65 +#set_property -dict {PACKAGE_PIN AP23 IOSTANDARD SSTL12_DCI } [get_ports ddr_cs_n[3] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B3" - IO_L21P_T3L_N4_AD8P_D06_65 +#set_property -dict {PACKAGE_PIN AM24 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[17] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR17" - IO_L20N_T3L_N3_AD1N_D09_65 +set_property -dict {PACKAGE_PIN AL24 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[13] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR13" - IO_L20P_T3L_N2_AD1P_D08_65 +set_property -dict {PACKAGE_PIN AN24 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR0" - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +set_property -dict {PACKAGE_PIN AN23 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[16] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR16" - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +#set_property -dict {PACKAGE_PIN AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports ddr_ck_c[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_C1" - IO_L17N_T2U_N9_AD10N_D15_65 +#set_property -dict {PACKAGE_PIN AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports ddr_ck_t[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_T1" - IO_L17P_T2U_N8_AD10P_D14_65 +set_property -dict {PACKAGE_PIN AT23 IOSTANDARD SSTL12_DCI } [get_ports ddr_parity ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_PAR" - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +#set_property -dict {PACKAGE_PIN AR23 IOSTANDARD SSTL12_DCI } [get_ports ddr_cs_n[2] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B2" - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +#set_property -dict {PACKAGE_PIN AP25 IOSTANDARD SSTL12_DCI } [get_ports ddr_cs_n[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B1" - IO_T2U_N12_CSI_ADV_B_65 +set_property -dict {PACKAGE_PIN AU24 IOSTANDARD SSTL12_DCI } [get_ports ddr_ba[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BA0" - IO_L18N_T2U_N11_AD2N_D13_65 +set_property -dict {PACKAGE_PIN AT24 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR1" - IO_L18P_T2U_N10_AD2P_D12_65 +set_property -dict {PACKAGE_PIN AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports ddr_ck_c[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_C0" - IO_L15N_T2L_N5_AD11N_A03_D19_65 +set_property -dict {PACKAGE_PIN AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports ddr_ck_t[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_T0" - IO_L15P_T2L_N4_AD11P_A02_D18_65 +set_property -dict {PACKAGE_PIN AV24 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[6] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR6" - IO_L14N_T2L_N3_GC_A05_D21_65 +set_property -dict {PACKAGE_PIN AV23 IOSTANDARD SSTL12_DCI } [get_ports ddr_cs_n[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B0" - IO_L14P_T2L_N2_GC_A04_D20_65 +set_property -dict {PACKAGE_PIN AW26 IOSTANDARD SSTL12_DCI } [get_ports ddr_bg[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BG1" - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +set_property -dict {PACKAGE_PIN AW25 IOSTANDARD SSTL12_DCI } [get_ports ddr_act_n ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ACT_B" - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +#set_property -dict {PACKAGE_PIN AY26 IOSTANDARD LVCMOS12 } [get_ports ddr_alert_n ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ALERT_B" - IO_L11N_T1U_N9_GC_A11_D27_65 +set_property -dict {PACKAGE_PIN AY25 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[8] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR8" - IO_L11P_T1U_N8_GC_A10_D26_65 +set_property -dict {PACKAGE_PIN AY23 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[5] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR5" - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +set_property -dict {PACKAGE_PIN AY22 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[4] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR4" - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +set_property -dict {PACKAGE_PIN BA25 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[11] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR11" - IO_T1U_N12_SMBALERT_65 +set_property -dict {PACKAGE_PIN AW24 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[2] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR2" - IO_L12N_T1U_N11_GC_A09_D25_65 +set_property -dict {PACKAGE_PIN AW23 IOSTANDARD SSTL12_DCI } [get_ports ddr_odt[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ODT0" - IO_L12P_T1U_N10_GC_A08_D24_65 +set_property -dict {PACKAGE_PIN BB25 IOSTANDARD SSTL12_DCI } [get_ports ddr_cke[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CKE0" - IO_L9N_T1L_N5_AD12N_A15_D31_65 +#set_property -dict {PACKAGE_PIN BB24 IOSTANDARD SSTL12_DCI } [get_ports ddr_cke[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CKE1" - IO_L9P_T1L_N4_AD12P_A14_D30_65 +set_property -dict {PACKAGE_PIN BA23 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[9] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR9" - IO_L8N_T1L_N3_AD5N_A17_65 +set_property -dict {PACKAGE_PIN BA22 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[7] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR7" - IO_L8P_T1L_N2_AD5P_A16_65 +set_property -dict {PACKAGE_PIN BC22 IOSTANDARD SSTL12_DCI } [get_ports ddr_bg[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BG0" - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +set_property -dict {PACKAGE_PIN BB22 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[12] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR12" - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +set_property -dict {PACKAGE_PIN BF25 IOSTANDARD POD12_DCI } [get_ports ddr_dq[64] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ64" - IO_L5N_T0U_N9_AD14N_A23_65 +set_property -dict {PACKAGE_PIN BF24 IOSTANDARD POD12_DCI } [get_ports ddr_dq[65] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ65" - IO_L5P_T0U_N8_AD14P_A22_65 +set_property -dict {PACKAGE_PIN BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[16]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_C8" - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +set_property -dict {PACKAGE_PIN BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[16]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_T8" - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +set_property -dict {PACKAGE_PIN BE25 IOSTANDARD POD12_DCI } [get_ports ddr_dq[67] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ67" - IO_L6N_T0U_N11_AD6N_A21_65 +set_property -dict {PACKAGE_PIN BD25 IOSTANDARD POD12_DCI } [get_ports ddr_dq[66] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ66" - IO_L6P_T0U_N10_AD6P_A20_65 +set_property -dict {PACKAGE_PIN BF23 IOSTANDARD POD12_DCI } [get_ports ddr_dq[70] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ70" - IO_L3N_T0L_N5_AD15N_A27_65 +set_property -dict {PACKAGE_PIN BE23 IOSTANDARD POD12_DCI } [get_ports ddr_dq[71] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ71" - IO_L3P_T0L_N4_AD15P_A26_65 +set_property -dict {PACKAGE_PIN BD23 IOSTANDARD POD12_DCI } [get_ports ddr_dq[68] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ68" - IO_L2N_T0L_N3_FWE_FCS2_B_65 +set_property -dict {PACKAGE_PIN BC23 IOSTANDARD POD12_DCI } [get_ports ddr_dq[69] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ69" - IO_L2P_T0L_N2_FOE_B_65 +set_property -dict {PACKAGE_PIN BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_c[17]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_C17" - IO_L1N_T0L_N1_DBC_RS1_65 +set_property -dict {PACKAGE_PIN BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports ddr_dqs_t[17]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_T17" - IO_L1P_T0L_N0_DBC_RS0_65 diff --git a/piton/design/xilinx/alveou250/devices_ariane.xml b/piton/design/xilinx/alveou250/devices_ariane.xml new file mode 120000 index 000000000..9200076c2 --- /dev/null +++ b/piton/design/xilinx/alveou250/devices_ariane.xml @@ -0,0 +1 @@ +../alveou280/devices_ariane.xml \ No newline at end of file diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc new file mode 100644 index 000000000..b98413d0e --- /dev/null +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -0,0 +1,118 @@ +# Modified by Barcelona Supercomputing Center on March 3rd, 2024 +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#----------------- System Clock ------------------- +set_property -dict {PACKAGE_PIN BJ6 IOSTANDARD LVDS} [get_ports chipset_clk_osc_n] +set_property -dict {PACKAGE_PIN BH6 IOSTANDARD LVDS} [get_ports chipset_clk_osc_p] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets chipset/clk_mmcm/inst/clkin1_ibufds/O] +set chip_clk [get_clocks -of_objects [get_pins -hierarchical clk_mmcm/chipset_clk]] +#-------------------------------------------- + +#----------------- PCIe signals ------------------- +#PCIE_PERSTN Active low input from PCIe Connector to Ultrascale+ Device to detect presence. +set_property -dict {PACKAGE_PIN BH26 IOSTANDARD LVCMOS18} [get_ports pcie_perstn] +set_property PACKAGE_PIN AR14 [get_ports pcie_refclk_n] +set_property PACKAGE_PIN AR15 [get_ports pcie_refclk_p] +create_clock -period 10.000 -name PCIE_CLK [get_ports pcie_refclk_p] + +# Timing constraints for clock domains crossings (CDC) +set qdma_clk [get_clocks -of_objects [get_pins -hierarchical qdma_0/axi_aclk]] +# set_false_path -from $xxx_clk -to $yyy_clk +# controlling resync paths to be less than source clock period +# (-datapath_only to exclude clock paths) +set_max_delay -datapath_only -from $qdma_clk -to $chip_clk [expr [get_property -min period $qdma_clk] * 0.9] + +# Specifying the placement of PCIe clock domain modules into single SLR to facilitate routing +# https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug912-vivado-properties.pdf#page=386 +#Collecting all units from correspondingly PCIe domain, +set pcie_clk_units [get_cells -of_objects [get_nets -of_objects [get_pins -hierarchical qdma_0/axi_aclk]]] +#Setting specific SLR to which PCIe pins are wired since placer may miss it if just "group_name" is applied +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells "$pcie_clk_units"] +#-------------------------------------------- + +#----------------- DRAM related constarints ------------------- +# HBM Catastrophic Over temperature Output signal to Satellite Controller +# HBM_CATTRIP Active high indicator to Satellite controller to indicate the HBM has exceeded its maximum allowable temperature. +# This signal is not a dedicated Ultrascale+ Device output and is a derived signal in RTL. Making the signal Active will shut +# the Ultrascale+ Device power rails off. +# +# From UG1314 (Alveo U280 Data Center Accelerator Card User Guide): +# WARNING! When creating a design for this card, it is necessary to drive the CATTRIP pin. +# This pin is monitored by the card's satellite controller (SC) and represents the HBM_CATRIP (HBM +# catastrophic temperature failure). When instantiating the HBM IP in your design, the two HBM IP signals, +# DRAM_0_STAT_CATTRIP and DRAM_1_STAT_CATTRIP, must be ORed together and connected to this pin for +# proper card operation. If the pin is undefined it will be pulled High by the card causing the SC to infer a CATRIP +# failure and shut power down to the card. +# If you do not use the HBM IP in your design, you must drive the pin Low to avoid the SC shutting down the card. +# If the pin is undefined and the QSPI is programmed with the MCS file, there is a potential chance that the card +# will continuously power down and reset after the bitstream is loaded. This can result in the card being unusable. +# ------------------------------------------------------------------------ +set_property PACKAGE_PIN D32 [get_ports hbm_cattrip]; # Bank 75 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_75 +set_property IOSTANDARD LVCMOS18 [get_ports hbm_cattrip]; # Bank 75 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_75 +set_property PULLTYPE PULLDOWN [get_ports hbm_cattrip]; # Setting HBM_CATTRIP to low by default to avoid the SC shutting down the card +# ------- DRAM reference clock +set_property -dict {PACKAGE_PIN BJ44 IOSTANDARD LVDS} [get_ports mc_clk_n]; # Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 +set_property -dict {PACKAGE_PIN BJ43 IOSTANDARD LVDS} [get_ports mc_clk_p]; # Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +#create_clock is needed in case of passing MEM_CLK through diff buffer (for HBM) +create_clock -period 10.000 -name MEM_CLK [get_ports "mc_clk_p"] +#-------------------------------------------- +# Timing constraints for CDC in SDRAM user interface, particularly in HBM APB which is disabled but clocked by fixed mem ref clock +set mref_clk [get_clocks -of_objects [get_pins -hierarchical meep_shell/mem_refclk_clk_p]] +# set_false_path -from $xxx_clk -to $yyy_clk +# controlling resync paths to be less than source clock period +# (-datapath_only to exclude clock paths) +set_max_delay -datapath_only -from $chip_clk -to $mref_clk [expr [get_property -min period $chip_clk] * 0.9] +set_max_delay -datapath_only -from $mref_clk -to $chip_clk [expr [get_property -min period $mref_clk] * 0.9] +#-------------------------------------------- + +#----------------- JTAG CDC ------------------- +# Timing constraints for clock domains crossings (CDC) +set jtag_clk [get_clocks -of_objects [get_pins -hierarchical jtag_shell/dbg_jtag_tck]] +# set_false_path -from $xxx_clk -to $yyy_clk +# controlling resync paths to be less than source clock period +# (-datapath_only to exclude clock paths) +# For JTAG clock we consider both edges +set_max_delay -datapath_only -from $chip_clk -to $jtag_clk [expr [get_property -min period $chip_clk] * 0.9 ] +set_max_delay -datapath_only -from $jtag_clk -to $chip_clk [expr [get_property -min period $jtag_clk] * 0.9 / 2] +#-------------------------------------------- + +#----------------- UART ------------------- +set_property -dict {PACKAGE_PIN B33 IOSTANDARD LVCMOS18} [get_ports uart_tx] +set_property -dict {PACKAGE_PIN A28 IOSTANDARD LVCMOS18} [get_ports uart_rx] +#-------------------------------------------- + +#----------------- Bitstream Configuration ------------------- +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] +# -------------------------------------------------------------- diff --git a/piton/design/xilinx/alveou280/ddr4.xdc b/piton/design/xilinx/alveou280/ddr4.xdc new file mode 100644 index 000000000..e053ed123 --- /dev/null +++ b/piton/design/xilinx/alveou280/ddr4.xdc @@ -0,0 +1,334 @@ +#-------------------------------------------- +# Timing constraints for CDC in DDR SDRAM user interface, particularly in NOC - DDR AXI transition (fifo, reset) +set sys_ck [get_clocks -of_objects [get_pins -hierarchical meep_shell/sys_clk]] +set mem_ck [get_clocks -of_objects [get_pins -hierarchical meep_shell/mem_clk]] +# set_false_path -from $xxx_clk -to $yyy_clk +# controlling resync paths to be less than source clock period +# (-datapath_only to exclude clock paths) +set_max_delay -datapath_only -from $mem_ck -to $sys_ck [expr [get_property -min period $mem_ck] * 0.9] +set_max_delay -datapath_only -from $sys_ck -to $mem_ck [expr [get_property -min period $sys_ck] * 0.9] +#-------------------------------------------- + +#-------------------------------------------- +## DDR4 RDIMM Controller 0, 72-bit Data Interface, x4 Componets, Single Rank +## <<>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order: +## JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 +## Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +## +set_property PACKAGE_PIN BE51 [ get_ports {ddr_dq[42]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ42" - IO_L24N_T3U_N11_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[42]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ42" - IO_L24N_T3U_N11_66 +set_property PACKAGE_PIN BD51 [ get_ports {ddr_dq[43]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ43" - IO_L24P_T3U_N10_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[43]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ43" - IO_L24P_T3U_N10_66 +set_property PACKAGE_PIN BE50 [ get_ports {ddr_dq[40]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ40" - IO_L23N_T3U_N9_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[40]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ40" - IO_L23N_T3U_N9_66 +set_property PACKAGE_PIN BE49 [ get_ports {ddr_dq[41]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ41" - IO_L23P_T3U_N8_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[41]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ41" - IO_L23P_T3U_N8_66 +set_property PACKAGE_PIN BF48 [ get_ports {ddr_dqs_c[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C5" - IO_L22N_T3U_N7_DBC_AD0N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C5" - IO_L22N_T3U_N7_DBC_AD0N_66 +set_property PACKAGE_PIN BF47 [ get_ports {ddr_dqs_t[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T5" - IO_L22P_T3U_N6_DBC_AD0P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T5" - IO_L22P_T3U_N6_DBC_AD0P_66 +set_property PACKAGE_PIN BF52 [ get_ports {ddr_dq[44]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ44" - IO_L21N_T3L_N5_AD8N_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[44]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ44" - IO_L21N_T3L_N5_AD8N_66 +set_property PACKAGE_PIN BF51 [ get_ports {ddr_dq[45]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ45" - IO_L21P_T3L_N4_AD8P_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[45]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ45" - IO_L21P_T3L_N4_AD8P_66 +set_property PACKAGE_PIN BG50 [ get_ports {ddr_dq[46]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ46" - IO_L20N_T3L_N3_AD1N_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[46]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ46" - IO_L20N_T3L_N3_AD1N_66 +set_property PACKAGE_PIN BF50 [ get_ports {ddr_dq[47]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ47" - IO_L20P_T3L_N2_AD1P_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[47]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ47" - IO_L20P_T3L_N2_AD1P_66 +set_property PACKAGE_PIN BG49 [ get_ports {ddr_dqs_c[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C14" - IO_L19N_T3L_N1_DBC_AD9N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C14" - IO_L19N_T3L_N1_DBC_AD9N_66 +set_property PACKAGE_PIN BG48 [ get_ports {ddr_dqs_t[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T14" - IO_L19P_T3L_N0_DBC_AD9P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T14" - IO_L19P_T3L_N0_DBC_AD9P_66 +#set_property PACKAGE_PIN BG47 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T3U_N12_66 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T3U_N12_66 +#set_property PACKAGE_PIN BF53 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T2U_N12_66 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T2U_N12_66 +set_property PACKAGE_PIN BE54 [ get_ports {ddr_dq[67]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ67" - IO_L18N_T2U_N11_AD2N_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[67]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ67" - IO_L18N_T2U_N11_AD2N_66 +set_property PACKAGE_PIN BE53 [ get_ports {ddr_dq[66]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ66" - IO_L18P_T2U_N10_AD2P_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[66]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ66" - IO_L18P_T2U_N10_AD2P_66 +set_property PACKAGE_PIN BG54 [ get_ports {ddr_dq[64]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ64" - IO_L17N_T2U_N9_AD10N_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[64]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ64" - IO_L17N_T2U_N9_AD10N_66 +set_property PACKAGE_PIN BG53 [ get_ports {ddr_dq[65]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ65" - IO_L17P_T2U_N8_AD10P_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[65]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ65" - IO_L17P_T2U_N8_AD10P_66 +set_property PACKAGE_PIN BJ54 [ get_ports {ddr_dqs_c[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C8" - IO_L16N_T2U_N7_QBC_AD3N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C8" - IO_L16N_T2U_N7_QBC_AD3N_66 +set_property PACKAGE_PIN BH54 [ get_ports {ddr_dqs_t[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T8" - IO_L16P_T2U_N6_QBC_AD3P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T8" - IO_L16P_T2U_N6_QBC_AD3P_66 +set_property PACKAGE_PIN BK54 [ get_ports {ddr_dq[70]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ70" - IO_L15N_T2L_N5_AD11N_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[70]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ70" - IO_L15N_T2L_N5_AD11N_66 +set_property PACKAGE_PIN BK53 [ get_ports {ddr_dq[71]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ71" - IO_L15P_T2L_N4_AD11P_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[71]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ71" - IO_L15P_T2L_N4_AD11P_66 +set_property PACKAGE_PIN BH52 [ get_ports {ddr_dq[68]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ68" - IO_L14N_T2L_N3_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[68]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ68" - IO_L14N_T2L_N3_GC_66 +set_property PACKAGE_PIN BG52 [ get_ports {ddr_dq[69]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ69" - IO_L14P_T2L_N2_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[69]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ69" - IO_L14P_T2L_N2_GC_66 +set_property PACKAGE_PIN BJ53 [ get_ports {ddr_dqs_c[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C17" - IO_L13N_T2L_N1_GC_QBC_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C17" - IO_L13N_T2L_N1_GC_QBC_66 +set_property PACKAGE_PIN BJ52 [ get_ports {ddr_dqs_t[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T17" - IO_L13P_T2L_N0_GC_QBC_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T17" - IO_L13P_T2L_N0_GC_QBC_66 +set_property PACKAGE_PIN BH50 [ get_ports {ddr_dq[48]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ48" - IO_L12N_T1U_N11_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[48]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ48" - IO_L12N_T1U_N11_GC_66 +set_property PACKAGE_PIN BH49 [ get_ports {ddr_dq[51]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ51" - IO_L12P_T1U_N10_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[51]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ51" - IO_L12P_T1U_N10_GC_66 +set_property PACKAGE_PIN BJ51 [ get_ports {ddr_dq[49]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ49" - IO_L11N_T1U_N9_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[49]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ49" - IO_L11N_T1U_N9_GC_66 +set_property PACKAGE_PIN BH51 [ get_ports {ddr_dq[50]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ50" - IO_L11P_T1U_N8_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[50]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ50" - IO_L11P_T1U_N8_GC_66 +set_property PACKAGE_PIN BJ47 [ get_ports {ddr_dqs_c[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C6" - IO_L10N_T1U_N7_QBC_AD4N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C6" - IO_L10N_T1U_N7_QBC_AD4N_66 +set_property PACKAGE_PIN BH47 [ get_ports {ddr_dqs_t[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T6" - IO_L10P_T1U_N6_QBC_AD4P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T6" - IO_L10P_T1U_N6_QBC_AD4P_66 +set_property PACKAGE_PIN BJ49 [ get_ports {ddr_dq[54]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ54" - IO_L9N_T1L_N5_AD12N_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[54]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ54" - IO_L9N_T1L_N5_AD12N_66 +set_property PACKAGE_PIN BJ48 [ get_ports {ddr_dq[55]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ55" - IO_L9P_T1L_N4_AD12P_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[55]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ55" - IO_L9P_T1L_N4_AD12P_66 +set_property PACKAGE_PIN BK51 [ get_ports {ddr_dq[53]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ53" - IO_L8N_T1L_N3_AD5N_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[53]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ53" - IO_L8N_T1L_N3_AD5N_66 +set_property PACKAGE_PIN BK50 [ get_ports {ddr_dq[52]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ52" - IO_L8P_T1L_N2_AD5P_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[52]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ52" - IO_L8P_T1L_N2_AD5P_66 +set_property PACKAGE_PIN BK49 [ get_ports {ddr_dqs_c[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C15" - IO_L7N_T1L_N1_QBC_AD13N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C15" - IO_L7N_T1L_N1_QBC_AD13N_66 +set_property PACKAGE_PIN BK48 [ get_ports {ddr_dqs_t[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T15" - IO_L7P_T1L_N0_QBC_AD13P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T15" - IO_L7P_T1L_N0_QBC_AD13P_66 +#set_property PACKAGE_PIN BL48 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_66 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_66 +#set_property PACKAGE_PIN BL50 #N/A ;# Bank 66 VCCO - VCC1V2 Net "VRP_61" - IO_T0U_N12_VRP_66 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 66 VCCO - VCC1V2 Net "VRP_61" - IO_T0U_N12_VRP_66 +set_property PACKAGE_PIN BL53 [ get_ports {ddr_dq[33]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ33" - IO_L6N_T0U_N11_AD6N_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[33]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ33" - IO_L6N_T0U_N11_AD6N_66 +set_property PACKAGE_PIN BL52 [ get_ports {ddr_dq[34]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ34" - IO_L6P_T0U_N10_AD6P_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[34]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ34" - IO_L6P_T0U_N10_AD6P_66 +set_property PACKAGE_PIN BM52 [ get_ports {ddr_dq[32]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ32" - IO_L5N_T0U_N9_AD14N_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[32]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ32" - IO_L5N_T0U_N9_AD14N_66 +set_property PACKAGE_PIN BL51 [ get_ports {ddr_dq[35]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ35" - IO_L5P_T0U_N8_AD14P_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[35]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ35" - IO_L5P_T0U_N8_AD14P_66 +set_property PACKAGE_PIN BM50 [ get_ports {ddr_dqs_c[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_66 +set_property PACKAGE_PIN BM49 [ get_ports {ddr_dqs_t[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_66 +set_property PACKAGE_PIN BN49 [ get_ports {ddr_dq[38]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ38" - IO_L3N_T0L_N5_AD15N_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[38]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ38" - IO_L3N_T0L_N5_AD15N_66 +set_property PACKAGE_PIN BM48 [ get_ports {ddr_dq[39]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ39" - IO_L3P_T0L_N4_AD15P_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[39]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ39" - IO_L3P_T0L_N4_AD15P_66 +set_property PACKAGE_PIN BN51 [ get_ports {ddr_dq[37]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ37" - IO_L2N_T0L_N3_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[37]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ37" - IO_L2N_T0L_N3_66 +set_property PACKAGE_PIN BN50 [ get_ports {ddr_dq[36]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ36" - IO_L2P_T0L_N2_66 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[36]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ36" - IO_L2P_T0L_N2_66 +set_property PACKAGE_PIN BP49 [ get_ports {ddr_dqs_c[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C13" - IO_L1N_T0L_N1_DBC_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C13" - IO_L1N_T0L_N1_DBC_66 +set_property PACKAGE_PIN BP48 [ get_ports {ddr_dqs_t[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T13" - IO_L1P_T0L_N0_DBC_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T13" - IO_L1P_T0L_N0_DBC_66 +## +## DDR4 RDIMM Control, Command and Address +## The DIMM interfaces have connectivity to support UDIMM, RDIMM, LRDIMM and 3DS devices. +## The below constraints are configured to support DDR4, Single Rank, RDIMMs with x4 Compnent Connectivity and the unused pins are commented out. +## The System Clock for the MEMORY interface are comemented out and moved to the Clock section of the XDC file +## +set_property PACKAGE_PIN BE44 [ get_ports {ddr_addr[13]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR13" - IO_L24N_T3U_N11_DOUT_CSO_B_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[13]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR13" - IO_L24N_T3U_N11_DOUT_CSO_B_65 +set_property PACKAGE_PIN BE43 [ get_ports {ddr_addr[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR14" - IO_L24P_T3U_N10_EMCCLK_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR14" - IO_L24P_T3U_N10_EMCCLK_65 +#set_property PACKAGE_PIN BD42 [ get_ports {ddr_cs_n[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_cs_n[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +#set_property PACKAGE_PIN BC42 [ get_ports {ddr_alert_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L23P_T3U_N8_I2C_SCLK_65 +#set_property IOSTANDARD LVCMOS12 [ get_ports {ddr_alert_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L23P_T3U_N8_I2C_SCLK_65 +#set_property PACKAGE_PIN BE46 [ get_ports {ddr_odt[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_odt[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +#set_property PACKAGE_PIN BE45 [ get_ports {ddr_cs_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_cs_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +set_property PACKAGE_PIN BF43 [ get_ports {ddr_addr[5]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR5" - IO_L21N_T3L_N5_AD8N_D07_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[5]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR5" - IO_L21N_T3L_N5_AD8N_D07_65 +set_property PACKAGE_PIN BF42 [ get_ports {ddr_addr[3]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR3" - IO_L21P_T3L_N4_AD8P_D06_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[3]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR3" - IO_L21P_T3L_N4_AD8P_D06_65 +set_property PACKAGE_PIN BF46 [ get_ports {ddr_addr[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR0" - IO_L20N_T3L_N3_AD1N_D09_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR0" - IO_L20N_T3L_N3_AD1N_D09_65 +set_property PACKAGE_PIN BF45 [ get_ports {ddr_parity} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_PAR" - IO_L20P_T3L_N2_AD1P_D08_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_parity} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_PAR" - IO_L20P_T3L_N2_AD1P_D08_65 +set_property PACKAGE_PIN BE41 [ get_ports {ddr_bg[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG1" - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_bg[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG1" - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +set_property PACKAGE_PIN BD41 [ get_ports {ddr_addr[11]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR11" - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[11]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR11" - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +set_property PACKAGE_PIN BF41 [ get_ports {ddr_bg[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG0" - IO_T3U_N12_PERSTN0_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_bg[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG0" - IO_T3U_N12_PERSTN0_65 +set_property PACKAGE_PIN BH41 [ get_ports {ddr_act_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ACT_B" - IO_T2U_N12_CSI_ADV_B_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_act_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ACT_B" - IO_T2U_N12_CSI_ADV_B_65 +set_property PACKAGE_PIN BG45 [ get_ports {ddr_addr[10]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR10" - IO_L18N_T2U_N11_AD2N_D13_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[10]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR10" - IO_L18N_T2U_N11_AD2N_D13_65 +set_property PACKAGE_PIN BG44 [ get_ports {ddr_odt[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT0" - IO_L18P_T2U_N10_AD2P_D12_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_odt[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT0" - IO_L18P_T2U_N10_AD2P_D12_65 +set_property PACKAGE_PIN BG43 [ get_ports {ddr_addr[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR1" - IO_L17N_T2U_N9_AD10N_D15_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR1" - IO_L17N_T2U_N9_AD10N_D15_65 +set_property PACKAGE_PIN BG42 [ get_ports {ddr_addr[6]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR6" - IO_L17P_T2U_N8_AD10P_D14_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[6]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR6" - IO_L17P_T2U_N8_AD10P_D14_65 +set_property PACKAGE_PIN BJ46 [ get_ports {ddr_ck_c[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C0" - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +set_property IOSTANDARD DIFF_SSTL12_DCI [ get_ports {ddr_ck_c[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C0" - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +set_property PACKAGE_PIN BH46 [ get_ports {ddr_ck_t[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T0" - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +set_property IOSTANDARD DIFF_SSTL12_DCI [ get_ports {ddr_ck_t[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T0" - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +#set_property PACKAGE_PIN BK41 [ get_ports {ddr_ck_c[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L15N_T2L_N5_AD11N_A03_D19_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_ck_c[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L15N_T2L_N5_AD11N_A03_D19_65 +#set_property PACKAGE_PIN BJ41 [ get_ports {ddr_ck_t[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L15P_T2L_N4_AD11P_A02_D18_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_ck_t[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L15P_T2L_N4_AD11P_A02_D18_65 +set_property PACKAGE_PIN BH45 [ get_ports {ddr_ba[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA0" - IO_L14N_T2L_N3_GC_A05_D21_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_ba[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA0" - IO_L14N_T2L_N3_GC_A05_D21_65 +set_property PACKAGE_PIN BH44 [ get_ports {ddr_addr[16]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR16" - IO_L14P_T2L_N2_GC_A04_D20_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[16]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR16" - IO_L14P_T2L_N2_GC_A04_D20_65 +#set_property PACKAGE_PIN BJ42 [ get_ports {ddr_cke[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_cke[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +set_property PACKAGE_PIN BH42 [ get_ports {ddr_cke[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE0" - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_cke[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE0" - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +## Clocks at top of XDC +#set_property PACKAGE_PIN BJ44 [ get_ports {sys_clk0_n} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 +#set_property IOSTANDARD LVDS [ get_ports {sys_clk0_n} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 +#set_property PACKAGE_PIN BJ43 [ get_ports {sys_clk0_p} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +#set_property IOSTANDARD LVDS [ get_ports {sys_clk0_p} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +### <<<>>> No external BIAS on AC coupled LVDS clock inputs to 1.2V bank so this constraint is added to recenter LVDS signal on 1.2V IO standard. +#set_property DQS_BIAS TRUE [ get_ports {sys_clk0_p} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +#set_property PACKAGE_PIN BK44 #N/A ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L11N_T1U_N9_GC_A11_D27_65 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L11N_T1U_N9_GC_A11_D27_65 +set_property PACKAGE_PIN BK43 [ get_ports {ddr_addr[8]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR8" - IO_L11P_T1U_N8_GC_A10_D26_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[8]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR8" - IO_L11P_T1U_N8_GC_A10_D26_65 +set_property PACKAGE_PIN BK46 [ get_ports {ddr_cs_n[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B0" - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_cs_n[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B0" - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +set_property PACKAGE_PIN BK45 [ get_ports {ddr_addr[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR2" - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR2" - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +set_property PACKAGE_PIN BL43 [ get_ports {ddr_addr[7]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR7" - IO_L9N_T1L_N5_AD12N_A15_D31_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[7]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR7" - IO_L9N_T1L_N5_AD12N_A15_D31_65 +set_property PACKAGE_PIN BL42 [ get_ports {ddr_addr[12]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR12" - IO_L9P_T1L_N4_AD12P_A14_D30_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[12]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR12" - IO_L9P_T1L_N4_AD12P_A14_D30_65 +set_property PACKAGE_PIN BL46 [ get_ports {ddr_addr[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR15" - IO_L8N_T1L_N3_AD5N_A17_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR15" - IO_L8N_T1L_N3_AD5N_A17_65 +set_property PACKAGE_PIN BL45 [ get_ports {ddr_addr[4]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR4" - IO_L8P_T1L_N2_AD5P_A16_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[4]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR4" - IO_L8P_T1L_N2_AD5P_A16_65 +set_property PACKAGE_PIN BM47 [ get_ports {ddr_ba[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA1" - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_ba[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA1" - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +#set_property PACKAGE_PIN BL47 [ get_ports {ddr_addr[17]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[17]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +set_property PACKAGE_PIN BM42 [ get_ports {ddr_addr[9]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR9" - IO_T1U_N12_SMBALERT_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports {ddr_addr[9]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR9" - IO_T1U_N12_SMBALERT_65 +set_property PACKAGE_PIN BN45 [ get_ports {ddr_dq[57]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ57" - IO_L6N_T0U_N11_AD6N_A21_65 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[57]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ57" - IO_L6N_T0U_N11_AD6N_A21_65 +set_property PACKAGE_PIN BM45 [ get_ports {ddr_dq[59]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ59" - IO_L6P_T0U_N10_AD6P_A20_65 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[59]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ59" - IO_L6P_T0U_N10_AD6P_A20_65 +set_property PACKAGE_PIN BN44 [ get_ports {ddr_dq[56]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ56" - IO_L5N_T0U_N9_AD14N_A23_65 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[56]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ56" - IO_L5N_T0U_N9_AD14N_A23_65 +set_property PACKAGE_PIN BM44 [ get_ports {ddr_dq[58]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ58" - IO_L5P_T0U_N8_AD14P_A22_65 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[58]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ58" - IO_L5P_T0U_N8_AD14P_A22_65 +set_property PACKAGE_PIN BP46 [ get_ports {ddr_dqs_c[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C7" - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C7" - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +set_property PACKAGE_PIN BN46 [ get_ports {ddr_dqs_t[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T7" - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T7" - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +set_property PACKAGE_PIN BP44 [ get_ports {ddr_dq[61]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ61" - IO_L3N_T0L_N5_AD15N_A27_65 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[61]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ61" - IO_L3N_T0L_N5_AD15N_A27_65 +set_property PACKAGE_PIN BP43 [ get_ports {ddr_dq[60]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ60" - IO_L3P_T0L_N4_AD15P_A26_65 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[60]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ60" - IO_L3P_T0L_N4_AD15P_A26_65 +set_property PACKAGE_PIN BP47 [ get_ports {ddr_dq[63]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ63" - IO_L2N_T0L_N3_FWE_FCS2_B_65 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[63]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ63" - IO_L2N_T0L_N3_FWE_FCS2_B_65 +set_property PACKAGE_PIN BN47 [ get_ports {ddr_dq[62]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ62" - IO_L2P_T0L_N2_FOE_B_65 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[62]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ62" - IO_L2P_T0L_N2_FOE_B_65 +set_property PACKAGE_PIN BP42 [ get_ports {ddr_dqs_c[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C16" - IO_L1N_T0L_N1_DBC_RS1_65 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C16" - IO_L1N_T0L_N1_DBC_RS1_65 +set_property PACKAGE_PIN BN42 [ get_ports {ddr_dqs_t[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T16" - IO_L1P_T0L_N0_DBC_RS0_65 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T16" - IO_L1P_T0L_N0_DBC_RS0_65 +set_property PACKAGE_PIN BJ31 [ get_ports {ddr_dq[8]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ8" - IO_L24N_T3U_N11_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[8]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ8" - IO_L24N_T3U_N11_64 +set_property PACKAGE_PIN BH31 [ get_ports {ddr_dq[9]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ9" - IO_L24P_T3U_N10_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[9]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ9" - IO_L24P_T3U_N10_64 +set_property PACKAGE_PIN BF33 [ get_ports {ddr_dq[11]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ11" - IO_L23N_T3U_N9_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[11]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ11" - IO_L23N_T3U_N9_64 +set_property PACKAGE_PIN BF32 [ get_ports {ddr_dq[10]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ10" - IO_L23P_T3U_N8_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[10]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ10" - IO_L23P_T3U_N8_64 +set_property PACKAGE_PIN BK30 [ get_ports {ddr_dqs_c[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C1" - IO_L22N_T3U_N7_DBC_AD0N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C1" - IO_L22N_T3U_N7_DBC_AD0N_64 +set_property PACKAGE_PIN BJ29 [ get_ports {ddr_dqs_t[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T1" - IO_L22P_T3U_N6_DBC_AD0P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T1" - IO_L22P_T3U_N6_DBC_AD0P_64 +set_property PACKAGE_PIN BG32 [ get_ports {ddr_dq[15]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ15" - IO_L21N_T3L_N5_AD8N_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[15]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ15" - IO_L21N_T3L_N5_AD8N_64 +set_property PACKAGE_PIN BF31 [ get_ports {ddr_dq[14]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ14" - IO_L21P_T3L_N4_AD8P_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[14]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ14" - IO_L21P_T3L_N4_AD8P_64 +set_property PACKAGE_PIN BH30 [ get_ports {ddr_dq[13]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ13" - IO_L20N_T3L_N3_AD1N_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[13]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ13" - IO_L20N_T3L_N3_AD1N_64 +set_property PACKAGE_PIN BH29 [ get_ports {ddr_dq[12]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ12" - IO_L20P_T3L_N2_AD1P_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[12]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ12" - IO_L20P_T3L_N2_AD1P_64 +set_property PACKAGE_PIN BG30 [ get_ports {ddr_dqs_c[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C10" - IO_L19N_T3L_N1_DBC_AD9N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C10" - IO_L19N_T3L_N1_DBC_AD9N_64 +set_property PACKAGE_PIN BG29 [ get_ports {ddr_dqs_t[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L19P_T3L_N0_DBC_AD9P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L19P_T3L_N0_DBC_AD9P_64 +#set_property PACKAGE_PIN BK29 [ get_ports {ddr_event_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_64 +#set_property IOSTANDARD LVCMOS12 [ get_ports {ddr_event_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_64 +set_property PACKAGE_PIN BG33 [ get_ports {ddr_reset_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_RESET_N" - IO_T2U_N12_64 +set_property IOSTANDARD LVCMOS12 [ get_ports {ddr_reset_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_RESET_N" - IO_T2U_N12_64 +set_property PACKAGE_PIN BH35 [ get_ports {ddr_dq[25]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ25" - IO_L18N_T2U_N11_AD2N_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[25]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ25" - IO_L18N_T2U_N11_AD2N_64 +set_property PACKAGE_PIN BH34 [ get_ports {ddr_dq[24]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ24" - IO_L18P_T2U_N10_AD2P_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[24]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ24" - IO_L18P_T2U_N10_AD2P_64 +set_property PACKAGE_PIN BF36 [ get_ports {ddr_dq[27]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ27" - IO_L17N_T2U_N9_AD10N_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[27]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ27" - IO_L17N_T2U_N9_AD10N_64 +set_property PACKAGE_PIN BF35 [ get_ports {ddr_dq[26]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ26" - IO_L17P_T2U_N8_AD10P_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[26]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ26" - IO_L17P_T2U_N8_AD10P_64 +set_property PACKAGE_PIN BK35 [ get_ports {ddr_dqs_c[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C3" - IO_L16N_T2U_N7_QBC_AD3N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C3" - IO_L16N_T2U_N7_QBC_AD3N_64 +set_property PACKAGE_PIN BK34 [ get_ports {ddr_dqs_t[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T3" - IO_L16P_T2U_N6_QBC_AD3P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T3" - IO_L16P_T2U_N6_QBC_AD3P_64 +set_property PACKAGE_PIN BG35 [ get_ports {ddr_dq[31]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ31" - IO_L15N_T2L_N5_AD11N_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[31]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ31" - IO_L15N_T2L_N5_AD11N_64 +set_property PACKAGE_PIN BG34 [ get_ports {ddr_dq[30]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ30" - IO_L15P_T2L_N4_AD11P_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[30]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ30" - IO_L15P_T2L_N4_AD11P_64 +set_property PACKAGE_PIN BJ34 [ get_ports {ddr_dq[29]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ29" - IO_L14N_T2L_N3_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[29]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ29" - IO_L14N_T2L_N3_GC_64 +set_property PACKAGE_PIN BJ33 [ get_ports {ddr_dq[28]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ28" - IO_L14P_T2L_N2_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[28]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ28" - IO_L14P_T2L_N2_GC_64 +set_property PACKAGE_PIN BJ32 [ get_ports {ddr_dqs_c[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_64 +set_property PACKAGE_PIN BH32 [ get_ports {ddr_dqs_t[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_64 +set_property PACKAGE_PIN BL33 [ get_ports {ddr_dq[19]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ19" - IO_L12N_T1U_N11_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[19]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ19" - IO_L12N_T1U_N11_GC_64 +set_property PACKAGE_PIN BK33 [ get_ports {ddr_dq[18]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ18" - IO_L12P_T1U_N10_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[18]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ18" - IO_L12P_T1U_N10_GC_64 +set_property PACKAGE_PIN BL31 [ get_ports {ddr_dq[17]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ17" - IO_L11N_T1U_N9_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[17]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ17" - IO_L11N_T1U_N9_GC_64 +set_property PACKAGE_PIN BK31 [ get_ports {ddr_dq[16]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ16" - IO_L11P_T1U_N8_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[16]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ16" - IO_L11P_T1U_N8_GC_64 +set_property PACKAGE_PIN BM35 [ get_ports {ddr_dqs_c[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_64 +set_property PACKAGE_PIN BL35 [ get_ports {ddr_dqs_t[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_64 +set_property PACKAGE_PIN BM33 [ get_ports {ddr_dq[21]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ21" - IO_L9N_T1L_N5_AD12N_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[21]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ21" - IO_L9N_T1L_N5_AD12N_64 +set_property PACKAGE_PIN BL32 [ get_ports {ddr_dq[20]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ20" - IO_L9P_T1L_N4_AD12P_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[20]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ20" - IO_L9P_T1L_N4_AD12P_64 +set_property PACKAGE_PIN BP34 [ get_ports {ddr_dq[23]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ23" - IO_L8N_T1L_N3_AD5N_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[23]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ23" - IO_L8N_T1L_N3_AD5N_64 +set_property PACKAGE_PIN BN34 [ get_ports {ddr_dq[22]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ22" - IO_L8P_T1L_N2_AD5P_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[22]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ22" - IO_L8P_T1L_N2_AD5P_64 +set_property PACKAGE_PIN BN35 [ get_ports {ddr_dqs_c[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_64 +set_property PACKAGE_PIN BM34 [ get_ports {ddr_dqs_t[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_64 +#set_property PACKAGE_PIN BP33 #N/A ;# Bank 64 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_64 +#set_property IOSTANDARD LVCMOS12 #N/A ;# Bank 64 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_64 +set_property PACKAGE_PIN BP32 [ get_ports {ddr_dq[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ1" - IO_L6N_T0U_N11_AD6N_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ1" - IO_L6N_T0U_N11_AD6N_64 +set_property PACKAGE_PIN BN32 [ get_ports {ddr_dq[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ0" - IO_L6P_T0U_N10_AD6P_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ0" - IO_L6P_T0U_N10_AD6P_64 +set_property PACKAGE_PIN BM30 [ get_ports {ddr_dq[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ3" - IO_L5N_T0U_N9_AD14N_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ3" - IO_L5N_T0U_N9_AD14N_64 +set_property PACKAGE_PIN BL30 [ get_ports {ddr_dq[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ2" - IO_L5P_T0U_N8_AD14P_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ2" - IO_L5P_T0U_N8_AD14P_64 +set_property PACKAGE_PIN BN30 [ get_ports {ddr_dqs_c[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_64 +set_property PACKAGE_PIN BN29 [ get_ports {ddr_dqs_t[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_64 +set_property PACKAGE_PIN BP31 [ get_ports {ddr_dq[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ6" - IO_L3N_T0L_N5_AD15N_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ6" - IO_L3N_T0L_N5_AD15N_64 +set_property PACKAGE_PIN BN31 [ get_ports {ddr_dq[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ7" - IO_L3P_T0L_N4_AD15P_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ7" - IO_L3P_T0L_N4_AD15P_64 +set_property PACKAGE_PIN BP29 [ get_ports {ddr_dq[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ4" - IO_L2N_T0L_N3_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ4" - IO_L2N_T0L_N3_64 +set_property PACKAGE_PIN BP28 [ get_ports {ddr_dq[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ5" - IO_L2P_T0L_N2_64 +set_property IOSTANDARD POD12_DCI [ get_ports {ddr_dq[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ5" - IO_L2P_T0L_N2_64 +set_property PACKAGE_PIN BM29 [ get_ports {ddr_dqs_c[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C9" - IO_L1N_T0L_N1_DBC_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_c[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C9" - IO_L1N_T0L_N1_DBC_64 +set_property PACKAGE_PIN BM28 [ get_ports {ddr_dqs_t[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T9" - IO_L1P_T0L_N0_DBC_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {ddr_dqs_t[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T9" - IO_L1P_T0L_N0_DBC_64 diff --git a/piton/design/xilinx/alveou280/devices_ariane.xml b/piton/design/xilinx/alveou280/devices_ariane.xml new file mode 100644 index 000000000..63c69f0f6 --- /dev/null +++ b/piton/design/xilinx/alveou280/devices_ariane.xml @@ -0,0 +1,88 @@ + + + + + chip + + + + mem + 0x80000000 + + 0x180000000 + + + dma_pool + 0x8040000000 + + 0x40000000 + 0x10000000 + + + + + iob + 0x9f00000000 + 0x10 + + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + + net + 0xfff0800000 + 0x400000 + + + + + + ariane_debug + 0xfff1000000 + 0x1000 + + + + + ariane_bootrom + 0xfff1010000 + 0x10000 + + + + + ariane_clint + 0xfff1020000 + 0xc0000 + + + + + ariane_plic + 0xfff1100000 + 0x4000000 + + + + + diff --git a/piton/design/xilinx/alveou55c/constraints.xdc b/piton/design/xilinx/alveou55c/constraints.xdc new file mode 100644 index 000000000..50ce7ee80 --- /dev/null +++ b/piton/design/xilinx/alveou55c/constraints.xdc @@ -0,0 +1,118 @@ +# Modified by Barcelona Supercomputing Center on March 3rd, 2024 +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#----------------- System Clock ------------------- +set_property -dict {PACKAGE_PIN BL10 IOSTANDARD LVDS} [get_ports chipset_clk_osc_n] +set_property -dict {PACKAGE_PIN BK10 IOSTANDARD LVDS} [get_ports chipset_clk_osc_p] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets chipset/clk_mmcm/inst/clkin1_ibufds/O] +set chip_clk [get_clocks -of_objects [get_pins -hierarchical clk_mmcm/chipset_clk]] +#-------------------------------------------- + +#----------------- PCIe signals ------------------- +#PCIE_PERSTN Active low input from PCIe Connector to Ultrascale+ Device to detect presence. +set_property -dict {PACKAGE_PIN BF41 IOSTANDARD LVCMOS18} [get_ports pcie_perstn] +set_property PACKAGE_PIN AR14 [get_ports pcie_refclk_n] +set_property PACKAGE_PIN AR15 [get_ports pcie_refclk_p] +create_clock -period 10.000 -name PCIE_CLK [get_ports pcie_refclk_p] + +# Timing constraints for clock domains crossings (CDC) +set qdma_clk [get_clocks -of_objects [get_pins -hierarchical qdma_0/axi_aclk]] +# set_false_path -from $xxx_clk -to $yyy_clk +# controlling resync paths to be less than source clock period +# (-datapath_only to exclude clock paths) +set_max_delay -datapath_only -from $qdma_clk -to $chip_clk [expr [get_property -min period $qdma_clk] * 0.9] + +# Specifying the placement of PCIe clock domain modules into single SLR to facilitate routing +# https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug912-vivado-properties.pdf#page=386 +#Collecting all units from correspondingly PCIe domain, +set pcie_clk_units [get_cells -of_objects [get_nets -of_objects [get_pins -hierarchical qdma_0/axi_aclk]]] +#Setting specific SLR to which PCIe pins are wired since placer may miss it if just "group_name" is applied +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells "$pcie_clk_units"] +#-------------------------------------------- + +#----------------- DRAM related constarints ------------------- +# HBM Catastrophic Over temperature Output signal to Satellite Controller +# HBM_CATTRIP Active high indicator to Satellite controller to indicate the HBM has exceeded its maximum allowable temperature. +# This signal is not a dedicated Ultrascale+ Device output and is a derived signal in RTL. Making the signal Active will shut +# the Ultrascale+ Device power rails off. +# +# From UG1314 (Alveo U280 Data Center Accelerator Card User Guide): +# WARNING! When creating a design for this card, it is necessary to drive the CATTRIP pin. +# This pin is monitored by the card's satellite controller (SC) and represents the HBM_CATRIP (HBM +# catastrophic temperature failure). When instantiating the HBM IP in your design, the two HBM IP signals, +# DRAM_0_STAT_CATTRIP and DRAM_1_STAT_CATTRIP, must be ORed together and connected to this pin for +# proper card operation. If the pin is undefined it will be pulled High by the card causing the SC to infer a CATRIP +# failure and shut power down to the card. +# If you do not use the HBM IP in your design, you must drive the pin Low to avoid the SC shutting down the card. +# If the pin is undefined and the QSPI is programmed with the MCS file, there is a potential chance that the card +# will continuously power down and reset after the bitstream is loaded. This can result in the card being unusable. +# ------------------------------------------------------------------------ +set_property PACKAGE_PIN BE45 [get_ports hbm_cattrip]; # Bank 75 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_75 +set_property IOSTANDARD LVCMOS18 [get_ports hbm_cattrip]; # Bank 75 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_75 +set_property PULLTYPE PULLDOWN [get_ports hbm_cattrip]; # Setting HBM_CATTRIP to low by default to avoid the SC shutting down the card +# ------- DRAM reference clock +set_property -dict {PACKAGE_PIN BK44 IOSTANDARD LVDS} [get_ports mc_clk_n]; # Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 +set_property -dict {PACKAGE_PIN BK43 IOSTANDARD LVDS} [get_ports mc_clk_p]; # Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +#create_clock is needed in case of passing MEM_CLK through diff buffer (for HBM) +create_clock -period 10.000 -name MEM_CLK [get_ports "mc_clk_p"] +#-------------------------------------------- +# Timing constraints for CDC in SDRAM user interface, particularly in HBM APB which is disabled but clocked by fixed mem ref clock +set mref_clk [get_clocks -of_objects [get_pins -hierarchical meep_shell/mem_refclk_clk_p]] +# set_false_path -from $xxx_clk -to $yyy_clk +# controlling resync paths to be less than source clock period +# (-datapath_only to exclude clock paths) +set_max_delay -datapath_only -from $chip_clk -to $mref_clk [expr [get_property -min period $chip_clk] * 0.9] +set_max_delay -datapath_only -from $mref_clk -to $chip_clk [expr [get_property -min period $mref_clk] * 0.9] +#-------------------------------------------- + +#----------------- JTAG CDC ------------------- +# Timing constraints for clock domains crossings (CDC) +set jtag_clk [get_clocks -of_objects [get_pins -hierarchical jtag_shell/dbg_jtag_tck]] +# set_false_path -from $xxx_clk -to $yyy_clk +# controlling resync paths to be less than source clock period +# (-datapath_only to exclude clock paths) +# For JTAG clock we consider both edges +set_max_delay -datapath_only -from $chip_clk -to $jtag_clk [expr [get_property -min period $chip_clk] * 0.9 ] +set_max_delay -datapath_only -from $jtag_clk -to $chip_clk [expr [get_property -min period $jtag_clk] * 0.9 / 2] +#-------------------------------------------- + +#----------------- UART ------------------- +set_property -dict {PACKAGE_PIN BJ41 IOSTANDARD LVCMOS18} [get_ports uart_tx] +set_property -dict {PACKAGE_PIN BK41 IOSTANDARD LVCMOS18} [get_ports uart_rx] +#-------------------------------------------- + +#----------------- Bitstream Configuration ------------------- +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] +# -------------------------------------------------------------- diff --git a/piton/design/xilinx/alveou55c/devices_ariane.xml b/piton/design/xilinx/alveou55c/devices_ariane.xml new file mode 120000 index 000000000..9200076c2 --- /dev/null +++ b/piton/design/xilinx/alveou55c/devices_ariane.xml @@ -0,0 +1 @@ +../alveou280/devices_ariane.xml \ No newline at end of file diff --git a/piton/design/xilinx/design.tcl b/piton/design/xilinx/design.tcl index 61c944dd0..20de75646 100644 --- a/piton/design/xilinx/design.tcl +++ b/piton/design/xilinx/design.tcl @@ -1,3 +1,4 @@ +# Modified by Barcelona Supercomputing Center on March 3rd, 2022 # Copyright (c) 2017 Princeton University # All rights reserved. # @@ -34,11 +35,37 @@ set DESIGN_INCLUDE_DIRS "" set DESIGN_DEFAULT_VERILOG_MACROS "PITON_FULL_SYSTEM PITON_FPGA_NO_DMBR MERGE_L1_DCACHE FPGA_SYN_1THREAD FPGA_FORCE_SRAM_ICACHE_TAG FPGA_FORCE_SRAM_LSU_ICACHE FPGA_FORCE_SRAM_DCACHE_TAG FPGA_FORCE_SRAM_LSU_DCACHE FPGA_FORCE_SRAM_RF16X160 FPGA_FORCE_SRAM_RF32X80 CONFIG_DISABLE_BIST_CLEAR" +set CORE_RTL_FILES "" + +if {[info exists ::env(PITON_ARIANE)]} { + set fp [open "$::env(ARIANE_ROOT)/Flist.ariane" r] + set file_data [read $fp] + set data [split $file_data "\n"] + set ARIANE_RTL_FILES {} + puts "Sources from $::env(ARIANE_ROOT)/Flist.ariane:" + foreach line $data { + set line [regsub -all {\r} $line ""] + set line [regsub -all {\+.*} $line ""] + set line [regsub {cpp.*} $line ""] + set line [regsub {//.*} $line ""] + set line [regsub {#.*} $line ""] + if {[string trim $line] eq ""} then continue + lappend ARIANE_RTL_FILES "$::env(ARIANE_ROOT)/${line}" + puts "$::env(ARIANE_ROOT)/${line}" + } + close $fp + + set CORE_RTL_FILES [concat ${CORE_RTL_FILES} ${ARIANE_RTL_FILES}] + puts "Including Ariane RTL files" +} + + set DESIGN_RTL_IMPL_FILES [concat \ ${SYSTEM_RTL_IMPL_FILES} \ ${CHIP_RTL_IMPL_FILES} \ ${PASSTHRU_RTL_IMPL_FILES} \ ${CHIPSET_RTL_IMPL_FILES} \ + ${CORE_RTL_FILES} \ ] set DESIGN_INCLUDE_FILES [concat \ diff --git a/piton/tools/bin/pyhplib.py b/piton/tools/bin/pyhplib.py index 2cdffcaab..abc0200fd 100644 --- a/piton/tools/bin/pyhplib.py +++ b/piton/tools/bin/pyhplib.py @@ -1,3 +1,4 @@ +# Modified by Barcelona Supercomputing Center on March 3rd, 2022 # Copyright (c) 2017 Princeton University # All rights reserved. # @@ -41,6 +42,9 @@ PITON_NUM_TILES = int(os.environ.get('PITON_NUM_TILES', '-1')) #print "//num_tiles:", num_tiles +PITON_EXTRA_MEMS = int(os.environ.get('PITON_EXTRA_MEMS', '-1')) +PITON_MC_INDICES = (os.environ.get('PITON_MC_INDICES', '0')) + PITON_NETWORK_CONFIG = (os.environ.get("PITON_NETWORK_CONFIG", "2dmesh_config")) if PITON_X_TILES == -1: @@ -269,6 +273,7 @@ def ReadDevicesXMLFile(): # go through each field of device base = 0 length = 0 + fragment = 0 name = "" noc2_in = False virtual = False @@ -280,6 +285,8 @@ def ReadDevicesXMLFile(): base = int(text, 0) elif tag == "length": length = int(text, 0) + elif tag == "fragment": + fragment = int(text, 0) elif tag == "name": name = text elif tag == "noc2in": @@ -298,7 +305,7 @@ def ReadDevicesXMLFile(): if name == "chip": devicesInfo.insert(0, {"name": name, "portnum": portnum, "base": base, "length": length, "noc2_in": noc2_in, "virtual": virtual, "stream_accessible":stream_accessible}) else: - devicesInfo.append({"name": name, "portnum": portnum, "base": base, "length": length, "noc2_in": noc2_in, "virtual": virtual, "stream_accessible":stream_accessible}) + devicesInfo.append({"name": name, "portnum": portnum, "base": base, "length": length, "fragment": fragment, "noc2_in": noc2_in, "virtual": virtual, "stream_accessible":stream_accessible}) return devicesInfo @@ -329,3 +336,51 @@ def GenBramFPGA(depth, width): end endmodule """ % (depth, width, depth_log2, width, depth_log2, width, width, depth, width)) + + +def get_manhattan_distance(p, q): + """ + Return the manhattan distance between points p and q + assuming both to have the same number of dimensions + """ + # sum of absolute difference between coordinates + distance = 0 + for p_i,q_i in zip(p,q): + distance += abs(p_i - q_i) + return distance + +#this function in also existed in sims,2. make sure both behave the same +def get_mc_mapping(piton_X,piton_Y,indices,mc_num,net_conf): + mc_list = indices.split(",") + edge_idx = 0; + mc_map=[] + for i in range(piton_X): + for j in range(piton_Y): + currentid = (i, j); + flatid = i + (j * piton_X); + exists = str(flatid) in mc_list + endp = piton_X * piton_Y; + if (net_conf != "xbar_config" and edge_idx < mc_num and exists == True): + index= mc_list.index(str(flatid)) + if (i == 0 and j != 0): # Tile 0 west port is occupied by "offchip" connection + endp = endp + piton_X + piton_X + j; + mc_map.insert(index,{'id':flatid,'x':i,'y':j,'n':0,'p':'W','endp':endp}) + edge_idx += 1 + + elif (j == piton_Y-1): # and i != 0 + endp = endp + piton_X + i; + mc_map.insert(index,{'id':flatid,'x':i,'y':j,'n':0,'p':'S','endp':endp}) + edge_idx += 1 + + elif (i == piton_X-1): # and j != PITON_Y_TILES-1 + endp = endp + piton_X + piton_X + piton_Y + j; + mc_map.insert(index,{'id':flatid,'x':i,'y':j,'n':0,'p':'E','endp':endp}) + edge_idx += 1 + + elif (j == 0): # and i != PITON_X_TILES-1 + endp = endp + i; + mc_map.insert(index,{'id':flatid,'x':i,'y':j,'n':0,'p':'N','endp':endp}) + edge_idx += 1 + else: + sys.stderr.write("Fatal: %s is not an edge router\n" % flatid) + return mc_map diff --git a/piton/tools/bin/riscvlib.py b/piton/tools/bin/riscvlib.py index c607229ca..5d9749ba3 100644 --- a/piton/tools/bin/riscvlib.py +++ b/piton/tools/bin/riscvlib.py @@ -1,4 +1,5 @@ #!/usr/bin/env python3 +# Modified by Barcelona Supercomputing Center on March 3rd, 2022 # Copyright 2019 ETH Zurich and University of Bologna. # Copyright and related rights are licensed under the Solderpad Hardware # License, Version 0.51 (the "License"); you may not use this file except in @@ -201,13 +202,53 @@ def gen_riscv_dts(devices, nCpus, cpuFreq, timeBaseFreq, periphFreq, dtsPath, ti }; ''' % (addrBase, _reg_fmt(addrBase, addrLen, 2, 2)) + for i in range(len(devices)): + if devices[i]["name"] == "dma_pool": + addrBase = devices[i]["base"] + addrLen = devices[i]["length"] + # Small hack to be able to access the whole space defined in the devices.xml file + # but still using just a fragment (256M) for particular dma pool. + addrFrag = devices[i]["fragment"] + addrOnic = addrBase + addrLen - addrFrag + tmpStr += ''' + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + eth_pool: eth_pool_node { + reg = <%s>; + compatible = "shared-dma-pool"; + }; + onic_pool: onic_pool_node { + reg = <%s>; + compatible = "shared-dma-pool"; + }; + }; + ''' % (_reg_fmt(addrBase, addrFrag, 2, 2), + _reg_fmt(addrOnic, addrFrag, 2, 2)) + #''' % (addrBase, _reg_fmt(addrBase, addrLen, 2, 2)) + + tmpStr += ''' + eth0_clk: eth0_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + ''' + # TODO: this needs to be extended # get the number of interrupt sources + # When using Ethernet + DMA, the number of IRQs for Ethernet is 2 instead of 1 + # TODO: Make a difference in the devices_$(core).xml between "net" and "dma_net", as the number of interrupts is different. + # TODO: An alternative is to add a field in the device xml file that holds the number of interrupts. numIrqs = 0 devWithIrq = ["uart", "net"]; for i in range(len(devices)): if devices[i]["name"] in devWithIrq: numIrqs += 1 + if devices[i]["name"] == "net": + numIrqs += 1 # get the remaining periphs @@ -286,35 +327,55 @@ def gen_riscv_dts(devices, nCpus, cpuFreq, timeBaseFreq, periphFreq, dtsPath, ti if devices[i]["name"] == "net": addrBase = devices[i]["base"] addrLen = devices[i]["length"] + dmaChannelMM2S = addrBase + 0x0 + dmaChannelS2MM = addrBase + 0x30 tmpStr += ''' - eth: ethernet@%08x { - compatible = "xlnx,xps-ethernetlite-1.00.a"; - device_type = "network"; + ethernet0 { + xlnx,rxmem = <0x5f2>; + carv,mtu = <0x5dc>; + carv,no-mac; + device_type = "network"; + local-mac-address = [00 0a 35 23 07 84]; + axistream-connected = <0xfe>; + compatible = "xlnx,xxv-ethernet-1.0-carv"; + memory-region = <ð_pool>; + }; + + dma_eth: dma@%08x { + xlnx,include-dre; + phandle = <0xfe>; + #dma-cells = <1>; + compatible = "xlnx,axi-dma-1.00.a"; + clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk"; + clocks = <ð0_clk>, <ð0_clk>, <ð0_clk>, <ð0_clk>; reg = <%s>; + interrupt-names = "mm2s_introut", "s2mm_introut"; interrupt-parent = <&PLIC0>; - interrupts = <%d>; - local-mac-address = [ 00 18 3E 02 E3 E5 ]; - phy-handle = <&phy0>; - xlnx,duplex = <0x1>; - xlnx,include-global-buffers = <0x1>; - xlnx,include-internal-loopback = <0x0>; - xlnx,include-mdio = <0x1>; - xlnx,rx-ping-pong = <0x1>; - xlnx,s-axi-id-width = <0x1>; - xlnx,tx-ping-pong = <0x1>; - xlnx,use-internal = <0x0>; - axi_ethernetlite_0_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - phy0: phy@1 { - compatible = "ethernet-phy-id001C.C915"; - device_type = "ethernet-phy"; - reg = <1>; - }; + interrupts = <%d %d>; + xlnx,addrwidth = <0x28>; + xlnx,include-sg; + xlnx,sg-length-width = <0x17>; + + dma-channel@%08x { + compatible = "xlnx,axi-dma-mm2s-channel"; + dma-channels = <1>; + interrupts = <%d>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x00>; + xlnx,include-dre; + }; + + dma-channel@%08x { + compatible = "xlnx,axi-dma-s2mm-channel"; + dma-channels = <1>; + interrupts = <%d>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x00>; + xlnx,include-dre; }; }; - ''' % (addrBase, _reg_fmt(addrBase, addrLen, 2, 2), ioDeviceNr) - ioDeviceNr+=1 + ''' % (addrBase, _reg_fmt(addrBase, addrLen, 2, 2), ioDeviceNr, ioDeviceNr+1, dmaChannelMM2S, ioDeviceNr, dmaChannelS2MM, ioDeviceNr+1) + ioDeviceNr+=2 tmpStr += ''' }; diff --git a/piton/tools/src/proto/alveo_tools/run_pitonstream.sh b/piton/tools/src/proto/alveo_tools/run_pitonstream.sh new file mode 100755 index 000000000..9d7c39df2 --- /dev/null +++ b/piton/tools/src/proto/alveo_tools/run_pitonstream.sh @@ -0,0 +1,21 @@ + +#To build app for basic Ariane design and load it via UART, in separate terminal: +# $ cd $PITON_ROOT/ +# $ source piton/ariane_setup.sh # Piton tools setup (https://github.com/PrincetonUniversity/openpiton#environment-setup-1) +# $ pitonstream --board alveou280 --design system --core ariane --x_tiles 1 --y_tiles 1 --port ttyUSB2 --file ./piton/verif/diag/c/riscv/ariane/test.list +#pitonstream compiles sources from test.list by folowing (taken from uart_piton.log or sims.log): +# $ cd ./build +# $ sims -sys=manycore -novcs_build -midas_only -midas_args="-DUART_DIV_LATCH=0x36 -DFPGA_HW -DCIOP -DNO_SLAN_INIT_SPC" hello_world.c -ariane -uart_dmw -x_tiles=1 -y_tiles=1 + +pcienum=`lspci -m -d 10ee:| cut -d' ' -f 1 | cut -d ':' -f 1` + +# Here a path to Xilinx PCIe DMA driver binary should be applied +# export PATH=path_to_Xilinx_PCIe_drivers/QDMA/linux-kernel/bin/:$PATH + +#PCIe GPIO bus: {Timeout_en(bit4), Bootrom_nOS(bit3), UartBoot_en(bit2), Ariane_rstn(bit1), System_rstn(bit0)} +dma-ctl qdma${pcienum}000 reg write bar 2 0x0 0x0 #Both resets +sleep 2 +dma-ctl qdma${pcienum}000 reg write bar 2 0x0 0x1D #Release system reset, we must wait until the memory is filled with 0s +sleep 2 +#pitonstream must be running and at this moment, it says "TEST_OUTPUT", and it is waiting for Arine reset to be released +dma-ctl qdma${pcienum}000 reg write bar 2 0x0 0x1F #Release Ariane's reset diff --git a/piton/tools/src/proto/alveou250/board.tcl b/piton/tools/src/proto/alveou250/board.tcl new file mode 100644 index 000000000..44869eba7 --- /dev/null +++ b/piton/tools/src/proto/alveou250/board.tcl @@ -0,0 +1,34 @@ +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# +# Board specific variables +# Not intended to be run standalone +# + +set BOARD_PART "" +set FPGA_PART "xcu250-figd2104-2L-e" +set VIVADO_FLOW_PERF_OPT 1 +set BOARD_DEFAULT_VERILOG_MACROS "ALVEO_BOARD" diff --git a/piton/tools/src/proto/alveou280/board.tcl b/piton/tools/src/proto/alveou280/board.tcl new file mode 100644 index 000000000..78f0efc95 --- /dev/null +++ b/piton/tools/src/proto/alveou280/board.tcl @@ -0,0 +1,34 @@ +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# +# Board specific variables +# Not intended to be run standalone +# + +set BOARD_PART "" +set FPGA_PART "xcu280-fsvh2892-2L-e" +set VIVADO_FLOW_PERF_OPT 1 +set BOARD_DEFAULT_VERILOG_MACROS "ALVEO_BOARD" diff --git a/piton/tools/src/proto/alveou55c/board.tcl b/piton/tools/src/proto/alveou55c/board.tcl new file mode 100644 index 000000000..d2cbf1389 --- /dev/null +++ b/piton/tools/src/proto/alveou55c/board.tcl @@ -0,0 +1,34 @@ +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# +# Board specific variables +# Not intended to be run standalone +# + +set BOARD_PART "" +set FPGA_PART "xcu55c-fsvh2892-2L-e" +set VIVADO_FLOW_PERF_OPT 1 +set BOARD_DEFAULT_VERILOG_MACROS "ALVEO_BOARD" diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 04a332390..1bc45d717 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -25,7 +25,7 @@ # Format: # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 -system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768 +system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,100,8192;alveou55c,100,8192;alveou250,100,8192 chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 diff --git a/piton/tools/src/proto/board.list b/piton/tools/src/proto/board.list index 6149781e9..a02567e2a 100644 --- a/piton/tools/src/proto/board.list +++ b/piton/tools/src/proto/board.list @@ -1,3 +1,4 @@ +# Modified by Barcelona Supercomputing Center on March 3rd, 2022 # Copyright (c) 2017 Princeton University # All rights reserved. # @@ -30,3 +31,6 @@ nexysVideo vivado f1 vivado vcu118 vivado xupp3r vivado +alveou280 vivado +alveou55c vivado +alveou250 vivado diff --git a/piton/tools/src/proto/common/pyhp_preprocess.tcl b/piton/tools/src/proto/common/pyhp_preprocess.tcl index c6cf582f2..f0497c238 100644 --- a/piton/tools/src/proto/common/pyhp_preprocess.tcl +++ b/piton/tools/src/proto/common/pyhp_preprocess.tcl @@ -33,9 +33,15 @@ proc pyhp_preprocess {RTL_IMPL_FILES} { # Setup temporary filename for preprocessed verilog set RTL_IMPL_FILENAME_LEN [string length ${RTL_IMPL_FILE}] + set EXT [string range ${RTL_IMPL_FILE} [expr ${RTL_IMPL_FILENAME_LEN} - 3] [expr ${RTL_IMPL_FILENAME_LEN} ]] + if { $EXT == ".sv"} { + set GEN_RTL_IMPL_FILE [string range ${RTL_IMPL_FILE} 0 [expr ${RTL_IMPL_FILENAME_LEN} - 3]] + append GEN_RTL_IMPL_FILE "tmp.sv" + } else { set GEN_RTL_IMPL_FILE [string range ${RTL_IMPL_FILE} 0 [expr ${RTL_IMPL_FILENAME_LEN} - 2]] append GEN_RTL_IMPL_FILE "tmp." append GEN_RTL_IMPL_FILE [string index ${RTL_IMPL_FILE} [expr ${RTL_IMPL_FILENAME_LEN} - 1]] + } # credit goes to https://github.com/PrincetonUniversity/openpiton/issues/50 # and https://www.xilinx.com/support/answers/72570.html diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index ae700b81d..96549716a 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -1,3 +1,4 @@ +# Modified by Barcelona Supercomputing Center on March 3rd, 2022 # Copyright (c) 2016 Princeton University # All rights reserved. # @@ -28,7 +29,7 @@ # Not intended to be run standalone # -set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include" +set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/src/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/src/util ${DV_ROOT}/design/chip/tile/ariane/include" # RTL include files set GLOBAL_INCLUDE_FILES [list \ @@ -123,6 +124,7 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/l2/rtl/l2_dir.v" \ "${DV_ROOT}/design/chip/tile/l2/rtl/l2_data.v" \ "${DV_ROOT}/design/chip/tile/l2/rtl/l2_amo_alu.v" \ + "${DV_ROOT}/design/chip/tile/l2/rtl/l2_to_mc.v" \ "${DV_ROOT}/design/chip/tile/l2/rtl/sram_wrappers/sram_l2_tag.v" \ "${DV_ROOT}/design/chip/tile/l2/rtl/sram_wrappers/sram_l2_state.v" \ "${DV_ROOT}/design/chip/tile/l2/rtl/sram_wrappers/sram_l2_dir.v" \ @@ -396,6 +398,8 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1i_tag.v" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ +] +set ARIANE_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/core/include/cv64a6_imafdc_sv39_config_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/include/riscv_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ @@ -651,17 +655,17 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/uart_reseter.v" \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/fake_boot_ctrl.v" \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/eth_top.v" \ - "${DV_ROOT}/design/chipset/mc/rtl/mc_top.v" \ + "${DV_ROOT}/design/chipset/mc/rtl/mc_top.sv" \ "${DV_ROOT}/design/chipset/mc/rtl/f1_mc_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/noc_mig_bridge.v" \ "${DV_ROOT}/design/chipset/mc/rtl/memory_zeroer.v" \ "${DV_ROOT}/design/chipset/noc_axilite_bridge/rtl/noc_axilite_bridge.v" \ "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge.v" \ - "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.v" \ - "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_deser.v" \ - "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_read.v" \ - "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_write.v" \ - "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_buffer.v" \ + "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_buffer.sv" \ + "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.sv" \ + "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_deser.sv" \ + "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_read.sv" \ + "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_write.sv" \ "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_sram_data.v" \ "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_sram_req.v" \ "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/axi4_zeroer.v" \ @@ -716,6 +720,8 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/l2/rtl/l2_encoder.v" \ "${DV_ROOT}/design/common/rtl/chip_rst_seq.v" \ "${DV_ROOT}/design/common/rtl/alarm_counter.v" \ + "${DV_ROOT}/design/common/rtl/bram_sdp_1ck.v" \ + "${DV_ROOT}/design/common/rtl/bram_tdp_1ck_wrfirst.v" \ "${DV_ROOT}/design/common/uart/rtl/Const.v" \ "${DV_ROOT}/design/common/uart/rtl/Counter.v" \ "${DV_ROOT}/design/common/uart/rtl/ParityGen.v" \ diff --git a/piton/tools/src/proto/common/setup.tcl b/piton/tools/src/proto/common/setup.tcl index ffd26822b..6263fd788 100644 --- a/piton/tools/src/proto/common/setup.tcl +++ b/piton/tools/src/proto/common/setup.tcl @@ -1,3 +1,4 @@ +# Modified by Barcelona Supercomputing Center on March 3rd, 2022 # Copyright (c) 2016 Princeton University # All rights reserved. # @@ -170,11 +171,11 @@ if {[info exists ::env(PITON_ARIANE)]} { exec make all MAX_HARTS=$::env(PITON_NUM_TILES) UART_FREQ=$::env(CONFIG_SYS_FREQ) 2>@1 } puts "INFO: done" - # two targets per hart (M,S) and two interrupt sources (UART, Ethernet) + # two targets per hart (M,S) and two interrupt sources (UART, DMA Ethernet(2)) set NUM_TARGETS [expr 2*$::env(PITON_NUM_TILES)] - set NUM_SOURCES 2 + set NUM_SOURCES 3 puts "INFO: generating PLIC for Ariane ($NUM_TARGETS targets, $NUM_SOURCES sources)..." - cd $::env(ARIANE_ROOT)/corev_apu/rv_plic/rtl + cd $::env(ARIANE_ROOT)/src/rv_plic/rtl exec ./gen_plic_addrmap.py -t $NUM_TARGETS -s $NUM_SOURCES > plic_regmap.sv cd $TMP diff --git a/piton/tools/src/proto/fpga_lib.py b/piton/tools/src/proto/fpga_lib.py index 46f0870ea..1beb0b6a4 100644 --- a/piton/tools/src/proto/fpga_lib.py +++ b/piton/tools/src/proto/fpga_lib.py @@ -1,4 +1,5 @@ #!/usr/bin/env python3 +# Modified by Barcelona Supercomputing Center on March 3rd, 2022 # Copyright (c) 2015 Princeton University # All rights reserved. # @@ -48,6 +49,9 @@ NOC_PAYLOAD_WIDTH = 512 STORAGE_BLOCK_BIT_WIDTH = { "ddr": { "vc707":512, "vcu118":512, + "alveou280":512, + "alveou55c":512, + "alveou250":512, "xupp3r":512, "nexys4ddr":128, "genesys2":256, @@ -56,6 +60,9 @@ }, "bram": { "vc707":512, "vcu118":512, + "alveou280":512, + "alveou55c":512, + "alveou250":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -65,6 +72,9 @@ }, "dmw": { "vc707":512, "vcu118":512, + "alveou280":512, + "alveou55c":512, + "alveou250":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -76,6 +86,9 @@ STORAGE_ADDRESSABLE_BIT_WIDTH = { "ddr": { "vc707":64, "vcu118":64, + "alveou280":64, + "alveou55c":64, + "alveou250":64, "xupp3r":64, "nexys4ddr":16, "genesys2":32, @@ -84,6 +97,9 @@ }, "bram": { "vc707":512, "vcu118":512, + "alveou280":512, + "alveou55c":512, + "alveou250":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -93,6 +109,9 @@ }, "dmw": { "vc707":512, "vcu118":512, + "alveou280":512, + "alveou55c":512, + "alveou250":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -104,6 +123,9 @@ STORAGE_BIT_SIZE = { "ddr": { "vc707":8*2**30, "vcu118":2*8*2**30, + "alveou280":2*8*2**30, + "alveou55c":2*8*2**30, + "alveou250":2*8*2**30, "xupp3r":32*8*2**30, "nexys4ddr":8*128*2**20, "genesys2":8*2**30, @@ -112,6 +134,9 @@ }, "bram": { "vc707":16384*512, "vcu118":16384*512, + "alveou280":16384*512, + "alveou55c":16384*512, + "alveou250":16384*512, "xupp3r":16384*512, "nexys4ddr":16384*512, "genesys2":16384*512, @@ -121,6 +146,9 @@ }, "dmw": { "vc707":8*2**30, "vcu118":2*8*2**30, + "alveou280":2*8*2**30, + "alveou55c":2*8*2**30, + "alveou250":2*8*2**30, "xupp3r":32*8*2**30, "nexys4ddr":8*128*2**20, "genesys2":8*2**30, diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 5818ca49c..337184cb0 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -1,4 +1,5 @@ #!/usr/bin/env python3 +# Modified by Barcelona Supercomputing Center on March 3rd, 2022 # Copyright (c) 2015 Princeton University # All rights reserved. # @@ -54,7 +55,7 @@ FLOW_STEP_OPTIONS = ["project", "impl"] def usage(): print(file=sys.stderr) print("Usage:\nprotosyn -b [-d ] [--bram-test ]", end=' ', file=sys.stderr) - print("[--from ] [--to ] [--no-ddr] [--uart-dmw ddr] [--eth] [--oled ]", file=sys.stderr) + print("[--from ] [--to ] [--no-ddr] [--uart-dmw ddr] [--eth] [--ethport] [--oled ]", file=sys.stderr) print(file=sys.stderr) print(" -b, --board ", file=sys.stderr) print(" Name of a supported Xilinx's development board. Available options are:", file=sys.stderr) @@ -64,6 +65,9 @@ def usage(): print(" genesys2", file=sys.stderr) print(" nexysVideo", file=sys.stderr) print(" f1", file=sys.stderr) + print(" alveou280", file=sys.stderr) + print(" alveou55c", file=sys.stderr) + print(" alveou250", file=sys.stderr) print("\n -d, --design ", file=sys.stderr) print(" Name of design module to synthesize. The default is 'system', which", file=sys.stderr) print(" synthesizes a full system with chip and chipset. See", file=sys.stderr) @@ -95,11 +99,21 @@ def usage(): print(" --config_l2_associativity ", file=sys.stderr) print(" Cache associativities, default: 4", file=sys.stderr) print("\n --bram-test ", file=sys.stderr) - print(" Name of the test to be mapped into BRAM", file=sys.stderr) + print(" Name of the test to be simulated and mapped into BRAM/DRAM", file=sys.stderr) + print("\n --verdi-dbg", file=sys.stderr) + print(" Create Verdi compliant simulation database of test specified by --bram-test option", file=sys.stderr) print("\n --no-ddr", file=sys.stderr) print(" Implement design without DDR memory", file=sys.stderr) + print("\n --hbm", file=sys.stderr) + print(" Implement design with HBM as system memory, enforced for Alveo U55C board", file=sys.stderr) + print("\n --multimc ", file=sys.stderr) + print(" Implement design with multiple connections to system memory", file=sys.stderr) + print("\n --multimc_indices ", file=sys.stderr) + print(" Comma separated list of edge routers IDs connected to MCs.", file=sys.stderr) print("\n --eth", file=sys.stderr) print(" Add Ethernet controller to implementation", file=sys.stderr) + print("\n --ethport ", file=sys.stderr) + print(" Define board-level Ethernet port number", file=sys.stderr) print("\n --uart-dmw ", file=sys.stderr) print(" Implement design with Direct Memory Write (DMW) from UART module turned on.", file=sys.stderr) print(" Storage type: \"ddr\"", file=sys.stderr) @@ -290,6 +304,7 @@ def makeProject(board, design_data, work_dir, log_dir, slurm, dep_list): proj_script = os.path.join(DV_ROOT, "tools/src/proto/" + tool + "/gen_project.tcl") proj_log = os.path.join(log_dir, PROJECT_BUILD_LOG) jname = "protosyn_mkproj_%s_%s" % (board, design_data["ID"]) + setSysFreq(board, design_data) jid = None if (tool == "vivado"): jid = run_vivado(proj_log, proj_script, design_data["PATH"], board, \ @@ -303,7 +318,7 @@ def makeProject(board, design_data, work_dir, log_dir, slurm, dep_list): return jid -def runImplFlow(board, design_data, work_dir, log_dir, def_list, slurm, dep_list): +def runImplFlow(board, eth, design_data, work_dir, log_dir, def_list, slurm, dep_list): prev_dir = os.getcwd() os.chdir(work_dir) @@ -344,6 +359,10 @@ def runImplFlow(board, design_data, work_dir, log_dir, def_list, slurm, dep_list jid = run_ise(impl_log, impl_flow, design_data["PATH"], board, \ slurm, 8, 64000, "6:00:00", jname, dep_list) + # Copy sw defines for Ethernet core to proper place + if (board == "alveou280" or board == "alveou55c" or board == "alveou250") and eth: + os.system('cp -rf $MODEL_DIR/%s/system/bd/Eth_CMAC_syst/ip/Eth_CMAC_syst_eth100gb_0/Eth_CMAC_syst_eth100gb_0/header_files/* $DV_ROOT/design/chipset/io_ctrl/xilinx/common/ip_cores/eth_cmac_syst/app4eth_syst/cpp/syst_hw/' % board) + os.chdir(prev_dir) return jid @@ -460,10 +479,15 @@ def setParserOptions(parser): parser.add_option("--config_l15_associativity", dest="config_l15_associativity", action="store", default=4) parser.add_option("--config_l2_associativity", dest="config_l2_associativity", action="store", default=4) parser.add_option("--bram-test", dest="test_name", action="store") + parser.add_option("--verdi-dbg", dest="verdi_dbg", action="store_true", default=False) parser.add_option("--from", dest="from_step", action="store", default=None) parser.add_option("--to", dest="to_step", action="store", default=None) parser.add_option("--no-ddr", dest="no_ddr", action="store_true", default=False) + parser.add_option("--hbm", dest="hbm", action="store_true", default=False) + parser.add_option("--multimc", dest="multimc", action="store", default=0) + parser.add_option("--multimc_indices", dest="multimc_indices", action="store", default=None) parser.add_option("--eth", dest="eth", action="store_true", default=False) + parser.add_option("--ethport", dest="ethport", action="store", default=0) parser.add_option("--uart-dmw", dest="uart_dmw", action="store", default=None) parser.add_option("--uart-reset", dest="uart_reset", action="store_true", default=False) parser.add_option("--asic-rtl", dest="asic_rtl", action="store_true", default=False) @@ -505,6 +529,20 @@ def makeDefList(options): else: # default option defines.append("PITON_FPGA_MC_DDR3") + if not options.hbm and (options.board == "alveou55c"): + print_info("Enforcing --hbm option for %s board" % options.board) + options.hbm = True + + if options.hbm and (options.board == "alveou250"): + print_info("Disabling --hbm option for %s board" % options.board) + options.hbm = False + + # --hbm option for utilizing HBM + if options.hbm: + defines.append("PITON_FPGA_MC_HBM") + os.environ['PROTOSYN_RUNTIME_HBM'] = "TRUE" + print_info("HBM is defined as primary system SDRAM") + # --axi4_mem option if (options.axi4_mem == True): if (options.board not in {"vc707", "xupp3r"}): @@ -517,13 +555,13 @@ def makeDefList(options): defines.append("PITONSYS_MEM_ZEROER") # do not use SD controller if BRAM is used for boot or a test or if board doesn't have sd - if (options.test_name != None) or (options.board in {"piton_board", 'xupp3r', "f1"}): + if (options.test_name != None) or (options.board in {"piton_board", "xupp3r", "f1", "alveou280", "alveou55c", "alveou250"}): pass else: # default option defines.append("PITON_FPGA_SD_BOOT") # --bram-test option - if options.test_name != None: + if (options.test_name != None and options.uart_dmw == "bram"): defines.append("PITON_FPGA_BRAM_TEST") defines.append("PITONSYS_NO_MC") @@ -586,7 +624,17 @@ def makeDefList(options): if options.eth or options.design == "chipset" or options.design == "system": # Ethernet controller is supported on Genesys2 and nexysVideo if options.board == "genesys2" or options.board == "nexysVideo": + defines.append("PITON_FPGA_ETH") defines.append("PITON_FPGA_ETHERNETLITE") + # Ethernet controller is also supported on Alveo boards + elif options.board == "alveou280" or options.board == "alveou55c" or options.board == "alveou250": + defines.append("PITON_FPGA_ETH") + if options.eth: + defines.append("PITON_FPGA_ETH_CMAC") + os.environ['PROTOSYN_RUNTIME_ETH'] = "TRUE" + if int(options.ethport) > 0: + defines.append("PITON_FPGA_ETH_PORT1") + os.environ['PROTOSYN_RUNTIME_ETHPORT'] = "1" else: print_info("--eth option is ignored for %s" % options.board) @@ -644,6 +692,60 @@ def genUARTInit(board, design_data): 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000;""" % div, file=f) f.close() +def setSysFreq(board, design_data): + print_info("Passing to implementation system clock frequency: %s MHz" % design_data["BOARDS"][board]["FREQ"]) + os.environ['SYSTEM_FREQ'] = str(design_data["BOARDS"][board]["FREQ"]) + + +def unique(list1): + unique_list = [] + for x in list1: + if x not in unique_list: + unique_list.append(x) + return unique_list + +def get_both_xy_edge_routers_ids (piton_X, piton_Y): + edges=[] + i=0 + j=0 + for i in range(piton_X): # first row + id = j * piton_X + i; + edges.append(id) + + i=piton_X-1 + for j in range(1,piton_Y,1): #last column + id = j * piton_X + i + edges.append(id) + + j=piton_Y-1 + for i in reversed(list(range(1, piton_X-1))): # last row + id = j * piton_X + i + edges.append(id) + + i=0; + for j in reversed(list(range(1, piton_Y))): #first column + id = j * piton_X + i + edges.append(id) + return unique(edges) + +def distribute_mc_equal_space_on_all_edges (x_tiles, y_tiles, multimc): + edge_ids = get_both_xy_edge_routers_ids (x_tiles,y_tiles) + edges = len(edge_ids) + d = 0 + if(multimc > 0) : + d = int(edges/multimc) + mc_num=0 + mmc = '' + for m in range (multimc): + mc_num= int (d * m) + mc_id = edge_ids[mc_num] + if(m==0) : + mmc=str(mc_id) + else : + mmc= mmc + "," + str(mc_id) + return mmc + + def main(): parser = OptionParser(add_help_option=False) parser = setParserOptions(parser) @@ -731,6 +833,57 @@ def main(): os.environ['PITON_Y_TILES'] = str(options.y_tiles) os.environ['PITON_NUM_TILES'] = str(options.num_tiles) + os.environ['PITON_EXTRA_MEMS'] = "0" + if options.multimc: + options.edge_tiles = 2 * (int(options.x_tiles)-1 + int(options.y_tiles)-1) + if int(options.edge_tiles) > int(options.num_tiles) or int(options.edge_tiles) < 1: + options.edge_tiles = options.num_tiles + if int(options.edge_tiles) > int(options.multimc): + options.edge_tiles =int(options.multimc) + if not options.hbm: + print_info("--multimc option is ignored without --hbm option") + elif int(options.edge_tiles) > 30: + print_info("Extra (" + str(options.edge_tiles) + ") connections to HBM (one per edge tile) are limited to 30.") + os.environ['PITON_EXTRA_MEMS'] = str(30) + else: + print_info("Extra (" + str(options.edge_tiles) + ") connections to HBM (one per edge tile) will be used.") + os.environ['PITON_EXTRA_MEMS'] = str(options.edge_tiles) + + if options.multimc_indices: + print_info ("MC indices:" + options.multimc_indices) + options.multimc_indices = options.multimc_indices + mc_tiles=[] + mc_tiles.extend(options.multimc_indices.split(",")) + l = len(mc_tiles) + #check indices size be equal with multimc + if( l != int(options.multimc) ): + print_error("Error : the number of tiles in multimc_indices is " + str(l) + " which is not equal to given multimc (" + options.multimc +")" ) + sys.exit(1) + unique_list = [] + for x in mc_tiles: + #check indices are unique + if x not in unique_list: + unique_list.append(x) + else : + print_error("Error : " + str(x) + " is repeated in " + str(mc_tiles) ) + sys.exit(1) + #check indices are int + if ( not x.isdigit()) : + print_error("Error : " + str(x) + " is not a valid int number " ) + sys.exit(1) + #check indices are in edge + x_p = int(x) % int(options.x_tiles) + y_p = (int(x) - x_p) / int(options.y_tiles) + if( x_p != 0 and y_p !=0 and x_p != int (options.x_tiles) -1 and y_p != int(options.y_tiles)-1) : + edge_ids = get_both_xy_edge_routers_ids (int(options.x_tiles),int(options.y_tiles)) + print_error("Error: the tile number " + x + " (" + str(int(x_p)) +","+ str(int(y_p)) + ") in multimc_indices is not an edge router. Edge Ids are:"+str(edge_ids)) + sys.exit(1) + os.environ['PITON_MC_INDICES']=options.multimc_indices + else : + options.multimc_indices=distribute_mc_equal_space_on_all_edges(int(options.x_tiles),int(options.y_tiles),int(os.environ['PITON_EXTRA_MEMS'])) + print_info ("No memory controller (MC) indices are given as input. Distribute MCs with equal space on all edges:" + options.multimc_indices) + os.environ['PITON_MC_INDICES']=options.multimc_indices + # core variant print_info("core = " + str(options.core)) for i in range(int(options.num_tiles)): @@ -768,6 +921,8 @@ def main(): os.environ['RTL_ARIANE' + str(i)] = "1" print_info('setenv RTL_ARIANE' + str(i)) + os.system('$DV_ROOT/design/chip/tile/ariane_patch/ariane_patch.sh') + elif options.core == 'sparc': # this is the default os.environ['PITON_OST1'] = "1" @@ -852,6 +1007,27 @@ def main(): if options.core == 'ariane': config += ' -ariane' + if options.board: + config += ' -board=' + options.board + + if options.eth: + config += ' -eth' + + if options.hbm: + config += ' -hbm' + + if options.uart_dmw: + config += ' -uart_dmw' + + if options.verdi_dbg: + config += ' -vcs_build_args=+vcs+fsdbon' + \ + ' -vcs_build_args=-kdb' + \ + ' -vcs_build_args=-debug_access+all' + \ + ' -vcs_build_args=-debug_region=cell+encrypt' + \ + ' -vcs_build_args=-LDFLAGS' + \ + ' -vcs_build_args=-Wl,--no-as-needed' + \ + ' -vcs_build_args=+vcs+lic+wait' + print_info("Synthesizing a test: %s" % options.test_name) print_info("Compilation started") ret_val = os.system('sims -sys=manycore' + config + ' -vcs_build -vcs_build_args=+libext+.v -vcs_build_args=-Mupdate > %s/compilation.log' % rc_dir.log) @@ -917,7 +1093,7 @@ def main(): if int(options.jobs)>1: print_info("Using %d jobs in Vivado" % int(options.jobs)) os.environ['NUM_VIVADO_JOBS'] = str(int(options.jobs)) - jid = runImplFlow(options.board, design_data, rc_dir.work, rc_dir.log, defines, options.slurm, dep_list) + jid = runImplFlow(options.board, options.eth, design_data, rc_dir.work, rc_dir.log, defines, options.slurm, dep_list) if jid != None: dep_list.append(jid) diff --git a/piton/tools/src/proto/vivado/gen_project.tcl b/piton/tools/src/proto/vivado/gen_project.tcl index 71183f47c..b20881894 100644 --- a/piton/tools/src/proto/vivado/gen_project.tcl +++ b/piton/tools/src/proto/vivado/gen_project.tcl @@ -1,3 +1,4 @@ +# Modified by Barcelona Supercomputing Center on March 3rd, 2022 # Copyright (c) 2016 Princeton University # All rights reserved. # @@ -77,6 +78,84 @@ foreach prj_file ${ALL_FILES} { } add_files -norecurse -fileset $fileset_obj $files_to_add +#Generating IP cores for Alveo boards +if { $BOARD_DEFAULT_VERILOG_MACROS == "ALVEO_BOARD" } { + + # Create IP of Xilix MMCM and frequency setup + if {[info exists ::env(PROTOSYN_RUNTIME_BOARD)] && $::env(PROTOSYN_RUNTIME_BOARD)=="alveou250"} { + set BRD_FREQ 300 + } else { + set BRD_FREQ 100 + } + puts "Setting MMCM input frequency to ${BRD_FREQ}MHz " + set SYS_FREQ $env(SYSTEM_FREQ) + puts "Setting MMCM output frequency to ${SYS_FREQ}MHz " + create_ip -vendor xilinx.com -library ip -name clk_wiz -version 6.0 -module_name clk_mmcm + set_property -dict [list CONFIG.PRIM_SOURCE {Differential_clock_capable_pin}] [get_ips clk_mmcm] + set_property -dict [list CONFIG.PRIM_IN_FREQ "$BRD_FREQ"] [get_ips clk_mmcm] + set_property -dict [list CONFIG.OPTIMIZE_CLOCKING_STRUCTURE_EN {true}] [get_ips clk_mmcm] + set_property -dict [list CONFIG.CLKOUT2_USED {true}] [get_ips clk_mmcm] + set_property -dict [list CONFIG.CLK_OUT1_PORT {chipset_clk}] [get_ips clk_mmcm] + set_property -dict [list CONFIG.CLK_OUT2_PORT {mc_sys_clk}] [get_ips clk_mmcm] + set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ "$SYS_FREQ"] [get_ips clk_mmcm] + set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {100}] [get_ips clk_mmcm] + + # Create IP of Xilinx UART + create_ip -vendor xilinx.com -library ip -name axi_uart16550 -version 2.0 -module_name uart_16550 + + # Create IP of Xilinx AXI traffic generator + create_ip -vendor xilinx.com -library ip -name axi_traffic_gen -version 3.0 -module_name atg_uart_init + set_property -dict [list CONFIG.C_ATG_SYSTEM_INIT_ADDR_MIF "$DV_ROOT/design/chipset/io_ctrl/xilinx/$BOARD/ip_cores/atg_uart_init/uart_addr.coe"] [get_ips atg_uart_init] + set_property -dict [list CONFIG.C_ATG_SYSTEM_INIT_DATA_MIF "$DV_ROOT/design/chipset/io_ctrl/xilinx/$BOARD/ip_cores/atg_uart_init/uart_data.coe"] [get_ips atg_uart_init] + set_property -dict [list CONFIG.C_ATG_MODE {AXI4-Lite}] [get_ips atg_uart_init] + + # Create IP of Xilinx async FIFO + create_ip -vendor xilinx.com -library ip -name fifo_generator -version 13.2 -module_name afifo_w64_d128_std + set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] [get_ips afifo_w64_d128_std] + set_property -dict [list CONFIG.Input_Data_Width {64}] [get_ips afifo_w64_d128_std] + set_property -dict [list CONFIG.Input_Depth {128}] [get_ips afifo_w64_d128_std] + set_property -dict [list CONFIG.Use_Embedded_Registers {false}] [get_ips afifo_w64_d128_std] + set_property -dict [list CONFIG.Enable_Safety_Circuit {false}] [get_ips afifo_w64_d128_std] + + # Generating PCIe-based Shell + # (to save BD: write_bd_tcl -force -no_project_wrapper ../piton/design/chipset/meep/meep_shell.tcl) + source $DV_ROOT/design/chipset/meep/meep_shell.tcl + + # Generating JTAG Shell + # (to save BD: write_bd_tcl -force -no_project_wrapper ../piton/design/chipset/meep/jtag_shell.tcl) + source $DV_ROOT/design/chipset/meep/jtag_shell.tcl + + # Generating Ethernet system + if {[info exists ::env(PROTOSYN_RUNTIME_BOARD)]} { + set g_board_part [string map {"alveo" ""} $::env(PROTOSYN_RUNTIME_BOARD)] + } + if {[info exists ::env(PROTOSYN_RUNTIME_ETHPORT)] && $::env(PROTOSYN_RUNTIME_ETHPORT)=="1"} { + set g_eth_port "qsfp1" + } else { + set g_eth_port "qsfp0" + } + if {[info exists ::env(PROTOSYN_RUNTIME_HBM)] && + $::env(PROTOSYN_RUNTIME_HBM)=="TRUE"} { + set g_dma_mem "hbm" + } else { + set g_dma_mem "ddr" + } + set g_saxi_prot "AXI4-512" + set g_saxi_freq "split" + set g_max_dma_addr_width "40" + set g_root_dir "./" + puts "Generating 100GbE on port `${g_eth_port}` with AXI slave `${g_saxi_prot}` and DMA memory at `${g_dma_mem}` for board `${g_board_part}`" + # set argv [list $g_board_part $g_eth_port $g_dma_mem $g_saxi_freq $g_saxi_prot] + # set argc 5 + # source $DV_ROOT/design/chipset/io_ctrl/xilinx/common/ip_cores/eth_cmac_syst/tcl/gen_project.tcl + # first adding the IP repository path of the Ehternet RX FIFO + set ip_repo_paths [get_property ip_repo_paths [current_project]] + lappend ip_repo_paths $DV_ROOT/design/chipset/io_ctrl/xilinx/common/ip_cores/eth_cmac_syst/ip_repo/eth_rx_fifo + set_property ip_repo_paths $ip_repo_paths [current_project] + update_ip_catalog -rebuild + source $DV_ROOT/design/chipset/io_ctrl/xilinx/common/ip_cores/eth_cmac_syst/tcl/eth_cmac_syst.tcl +} + # Set 'sources_1' fileset file properties for local files foreach inc_file $ALL_INCLUDE_FILES { if {[file exists $inc_file]} { @@ -192,6 +271,17 @@ set_property "used_in_implementation" "1" $file_obj set_property "used_in_synthesis" "1" $file_obj +if { $BOARD_DEFAULT_VERILOG_MACROS == "ALVEO_BOARD" } { + if {[info exists ::env(PROTOSYN_RUNTIME_ETH)] && + $::env(PROTOSYN_RUNTIME_ETH)=="TRUE"} { + add_files -fileset [get_filesets constrs_1] "$DV_ROOT/design/chipset/io_ctrl/xilinx/common/ip_cores/eth_cmac_syst/xdc/eth_syst_$g_board_part.xdc" + } + if {![info exists ::env(PROTOSYN_RUNTIME_HBM)] || + $::env(PROTOSYN_RUNTIME_HBM)!="TRUE"} { + add_files -fileset [get_filesets constrs_1] "$BOARD_DIR/ddr4.xdc" + } +} + # Set 'constrs_1' fileset properties set_property "name" "constrs_1" $fileset_obj set_property "target_constrs_file" "$constraints_file" $fileset_obj diff --git a/piton/tools/src/proto/vivado/impl_flow.tcl b/piton/tools/src/proto/vivado/impl_flow.tcl index c195d4be0..24c607ae4 100644 --- a/piton/tools/src/proto/vivado/impl_flow.tcl +++ b/piton/tools/src/proto/vivado/impl_flow.tcl @@ -69,3 +69,68 @@ if {[get_property PROGRESS [get_runs impl_1]] != "100%"} { } else { puts "INFO: Implementation passed!" } + +set VIVADO_POSTROUTEPHYSOPT $::env(VIVADO_POSTROUTEPHYSOPT) +if {$VIVADO_POSTROUTEPHYSOPT && $BOARD_DEFAULT_VERILOG_MACROS == "ALVEO_BOARD"} { + + open_run impl_1 + set CurrentSlack [get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] + if { [expr $CurrentSlack < 0.000] } { + + # Here is iterative routing procedure applying a set of strategies + file mkdir $env(PITON_ROOT)/build/iter_impl + + # Explore routing strategies + set RouteDirectives "NoTimingRelaxation \ + Explore \ + MoreGlobalIterations \ + HigherDelayCost \ + AdvancedSkewModeling \ + AlternateCLBRouting \ + AggressiveExplore \ + Default" + + set PhysOptDirectives "Explore \ + ExploreWithHoldFix \ + AggressiveExplore \ + AlternateReplication \ + AggressiveFanoutOpt \ + AddRetime \ + AlternateFlowWithRetiming \ + RuntimeOptimized \ + ExploreWithAggressiveHoldFix \ + Default" + + set route_loops [llength $RouteDirectives] + puts "=== Running route_design with $route_loops strategies" + for {set route_loop 0} {$route_loop < $route_loops} {incr route_loop} { + set route_design_directive [lindex $RouteDirectives $route_loop] + route_design -directive $route_design_directive + set CurrentSlack [get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] + puts "=== Finished $route_loop of $route_loops route_design $route_design_directive on [exec date] (WNS: $CurrentSlack)" + + set i 0 + set nloops [llength $PhysOptDirectives] + # Post-Route Physical Optimization is effective when WNS is above -0.5ns, and could be stuck otherwise + if { [expr {$CurrentSlack >= -0.5 || $route_loop == ($route_loops-1)}] } { + for {set i 0} {$i < $nloops} {incr i} { + set CurrentDirective [lindex $PhysOptDirectives $i] + phys_opt_design -directive $CurrentDirective + # Get the Slack after the optimization + set CurrentSlack [get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] + puts "--- Finished post-route ($route_loop/$route_loops) phys_opt_design ($i/$nloops ) with directive $CurrentDirective (WNS: $CurrentSlack)" + } + } + set CurrentSlack [get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] + puts "=== Finished phys_opt_design after $route_loop of $route_loops route_design $route_design_directive on [exec date] (WNS: $CurrentSlack)" + write_checkpoint -force $env(PITON_ROOT)/build/iter_impl/post_route${route_loop}_${route_design_directive}.dcp + + if { [expr $CurrentSlack >= 0.000] } { + break + } + } + + write_bitstream -force $env(PITON_ROOT)/build/iter_impl/iter_system.bit + + } +} diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index 2f6fc0c81..ef017f441 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -1,3 +1,4 @@ +// Modified by Barcelona Supercomputing Center on March 3rd, 2022 // Modified by Princeton University on June 9th, 2015 // ========== Copyright Header Begin ========================================== // @@ -71,6 +72,8 @@ -config_rtl=PITON_RV64_CLINT -config_rtl=PITON_RV64_PLIC -config_rtl=WT_DCACHE + // suppressing error in Questa: piton/design/chip/tile/ariane/src/scoreboard.sv(356): (vopt-8386) Illegal assignment to type 'enum reg[3:0] ' from type 'bit signed[31:0]': An enum variable may only be assigned the same enum typed variable or one of its values + -msm_build_args=-suppress 8386 #endif -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.clib_common -flist=$DV_ROOT/design/chip/tile/common/rtl/Flist.dlib_common @@ -108,6 +111,26 @@ -flist=$DV_ROOT/design/chip/tinyoram/rtl/Flist.oram -config_rtl=ORAM_ON" -sim_run_args=+oram" +#endif +#ifdef ALVEO_BOARD + -vcs_build_args=-y $DV_ROOT/design/chipset/io_ctrl/rtl/ + -vcs_build_args=-y $DV_ROOT/design/chipset/mc/rtl/ +libext+.sv + -vcs_build_args=-y $DV_ROOT/design/chipset/noc_axi4_bridge/rtl/ + -sim_build_args=+incdir+$DV_ROOT/design/chipset/noc_axi4_bridge/rtl/ + -sim_build_args=+define+PITONSYS_IOCTRL + -sim_build_args=+define+PITONSYS_UART + -sim_build_args=+define+PITON_UART16550 + -sim_build_args=+define+PITON_FPGA_MC_SIM +#ifdef UART_BOOT + -vcs_build_args=-y $DV_ROOT/design/chipset/rtl/ + -sim_build_args=+define+PITONSYS_UART_BOOT +#endif +#ifdef ETH_CORE + -sim_build_args=+define+PITON_FPGA_ETH +#endif +#ifdef HBM_DEF + -sim_build_args=+define+PITON_FPGA_MC_HBM +#endif #endif // No scan chains @@ -127,7 +150,7 @@ -vlt_build_args=-DSYNC_MUX - -rtl_timeout=50000 + -rtl_timeout=5000000 -sim_run_args=+spc_pipe=0 -sim_run_args=+doerrorfinish -sim_run_args=+dowarningfinish diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index d2905648f..345ffe56c 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -1,3 +1,4 @@ +# Modified by Barcelona Supercomputing Center on March 3rd, 2022 # Modified by Princeton University on June 9th, 2015 # ========== Copyright Header Begin ========================================== # @@ -173,6 +174,9 @@ Getopt::Long::Configure ('no_auto_abbrev') ; 'parallel' => 0, 'ost1' => 0, 'ariane' => 0, + 'hbm_lat' => 0, + 'multimc' => 0, + 'multimc_indices' => "", 'pico' => 0, 'pico_het' => 0, 'post_process_cmd' => [], @@ -326,6 +330,9 @@ GetOptions (\%opt, 'parallel!', 'ost1!', 'ariane!', + 'hbm_lat!', + 'multimc=s', + 'multimc_indices=s', 'pico!', 'pico_het!', 'sparcv9!', @@ -342,6 +349,11 @@ GetOptions (\%opt, 'simslog!', 'simslog_name=s', 'build_id=s', + 'vlt_build!', + 'board=s', + 'eth!', + 'hbm!', + 'uart_dmw!', ) ; die ("DIE. -ariane and -pico/-pico_het cannot be set simultaneously") if ($opt{ariane} && ($opt{pico} || $opt{pico_het})) ; @@ -357,6 +369,12 @@ push (@{$opt{config_cpp_args}}, "-DFLIST_OST1") if ($opt{ost1} || $opt{pico_ push (@{$opt{config_cpp_args}}, "-DFLIST_PICO") if ($opt{pico} || $opt{pico_het}) ; push (@{$opt{config_cpp_args}}, "-DFLIST_ARIANE") if ($opt{ariane}) ; push (@{$opt{config_cpp_args}}, "-DFLIST_ORAM") if ($opt{oram}) ; +push (@{$opt{config_cpp_args}}, "-DVERILATOR") if ($opt{vlt_build}) ; +# Other boards may be added here for simple MC/UART/Ethernet access simulation +push (@{$opt{config_cpp_args}}, "-DALVEO_BOARD") if (($opt{board}) and (($opt{board} eq "alveou280") || ($opt{board} eq "alveou55c") || ($opt{board} eq "alveou250"))) ; +push (@{$opt{config_cpp_args}}, "-DUART_BOOT") if ($opt{uart_dmw}) ; +push (@{$opt{config_cpp_args}}, "-DETH_CORE") if ($opt{eth}) ; +push (@{$opt{config_cpp_args}}, "-DHBM_DEF") if ($opt{hbm}) ; ################################################################################ # define $result_dir @@ -1172,8 +1190,11 @@ sub gen_flist } else { my $linepyv = (split(' ',substr($line, 0, -1)))[-1] . ".pyv"; # print("\$linepyv is $linepyv\n"); - my $linetmp = substr($line, 0, -3) . ".tmp.". substr($line, -2, 1); - my $linetmpout = (split(' ',substr($line, 0, -3)))[-1] . ".tmp." . substr($line, -2, 1); + my $ext = substr($line, -4, -1); + # print("\$ext=$ext\n"); + my $linetmp = ($ext eq '.sv')? substr($line, 0, -4) . ".tmp.sv" : substr($line, 0, -3) . ".tmp.". substr($line, -2, 1); + my $linetmpout = ($ext eq '.sv')? (split(' ',substr($line, 0, -4)))[-1] . ".tmp.sv" : (split(' ',substr($line, 0, -3)))[-1] . ".tmp.". substr($line, -2, 1); + # print("\$linetmp is $linetmp\n"); if (-e $linepyv) { # print("original is $line\n"); !system("pyhp.py $linepyv > $linetmpout") or die("Error running PyHP for $linepyv\n");; @@ -1279,7 +1300,7 @@ sub pre_build # 2 targets per core (M/S mode) my $num_targets = 2 * $ENV{PITON_NUM_TILES}; print "generating PLIC for rv64 platform with $num_targets targets and $num_sources sources...\n"; - !system("cd $ENV{ARIANE_ROOT}/corev_apu/rv_plic/rtl && ./gen_plic_addrmap.py -t $num_targets -s $num_sources > plic_regmap.sv") or + !system("cd $ENV{ARIANE_ROOT}/src/rv_plic/rtl && ./gen_plic_addrmap.py -t $num_targets -s $num_sources > plic_regmap.sv") or die (" Error generating PLIC for rv64 platform."); print "done\n"; } @@ -1531,9 +1552,11 @@ sub generic_sim_build $build_cmd .= "--unroll-count 256 " ; $build_cmd .= "-CFLAGS -DVERILATOR " ; $build_cmd .= "-CFLAGS -DPITON_DPI " ; + $build_cmd .= "-CFLAGS -DVERILATOR_VCD " ; $build_cmd .= "-CFLAGS -lstdc++ " ; $build_cmd .= "-CFLAGS -I$dv_root/tools/pli/iop " ; $build_cmd .= "-CFLAGS -I$dv_root/tools/verilator " ; + $build_cmd .= "--savable " ; } if ($opt{other_sim_build}) { if (($opt{other_sim_build_cmd}) eq "") { @@ -2462,6 +2485,109 @@ sub find_diag_path return $full_path[0] ; } +############################################################################### +#get_mc_mapping +############################################################################### +sub get_mc_mapping { + my ($piton_X,$piton_Y,$indices,$mc_num,$net_conf)=@_; + my @mc_list = split(",",$indices); + my $edge_idx = 0; + my @mc_map; + for (my $i=0; $i< $piton_X; $i++){ + for (my $j=0; $j< $piton_Y; $j++){ + #currentid = (i, j); + my $flatid = $i + ($j * $piton_X); + my $exists = grep( /^$flatid$/, @mc_list); + my $endp = $piton_X * $piton_Y; + if ($net_conf ne "xbar_config" && $edge_idx < $mc_num && $exists > 0){ + my $index =-1; + my $u=0; + foreach my $p ( @mc_list){ + $index =$u if ($flatid == $p); + $u++; + } + if ($i == 0 && $j != 0){ # Tile 0 west port is occupied by "offchip" connection + $endp = $endp + $piton_X + $piton_X + $j; + my %h=('id'=> $flatid,'x'=> $i,'y'=> $j,'n'=> 0,'p'=> 'W','endp'=> $endp); + push (@mc_map,\%h); + $edge_idx += 1 + + }elsif ($j == $piton_Y-1){ # and i != 0 + $endp = $endp + $piton_X + $i; + my %h=('id'=> $flatid,'x'=> $i,'y'=> $j,'n'=> 0,'p'=> 'S','endp'=> $endp); + push (@mc_map,\%h); + $edge_idx += 1 + + }elsif ($i == $piton_X-1){ # and j != PITON_Y_TILES-1 + $endp = $endp + $piton_X + $piton_X + $piton_Y + $j; + my %h=('id'=> $flatid,'x'=> $i,'y'=> $j,'n'=> 0,'p'=> 'E','endp'=> $endp); + push (@mc_map,\%h); + $edge_idx += 1 + + }elsif ($j == 0){ # and i != PITON_X_TILES-1 + $endp = $endp + $i; + my %h=('id'=> $flatid,'x'=> $i,'y'=> $j,'n'=> 0,'p'=> 'N','endp'=> $endp); + push (@mc_map,\%h); + $edge_idx += 1 + }else{ + die "Fatal: $flatid is not an edge router\n"; + } + } + } + } + return @mc_map; +} + +sub uniq { + my %seen; + return grep { !$seen{$_}++ } @_; +} + +sub get_both_xy_edge_routers_ids{ + my ($x, $y)=@_; + my @edges; + my $i; + my $j; + $j=0; + for ($i=0; $i<$x; $i++){my $id= $j*$x+$i;push (@edges,$id);} # first row + $i=$x-1; + for ($j=1; $j<$y; $j++){my $id= $j*$x+$i;push (@edges,$id);} #last column + $j=$y-1; + for ($i=$x-2; $i>0; $i--){my $id= $j*$x+$i;push (@edges,$id);} # last row + $i=0; + for ($j=$y-1; $j>0; $j--){my $id= $j*$x+$i;push (@edges,$id);} #first column + #print join(',',@edges), "\n"; + return uniq(@edges); +} + +sub get_first_y_edge_routers_ids{ + my ($x, $y)=@_; + my @edges; + my $i; + my $j; + $i=0; + for ($j=$y-1; $j>=0; $j--){my $id= $j*$x+$i;push (@edges,$id);} #first column + return uniq(@edges); +} + +sub distribute_mc_equal_space_on_all_edges { + my ($x,$y,$mc)=@_; + my @edge_ids =get_both_xy_edge_routers_ids ($x,$y); + my $edges = scalar @edge_ids; + my $d= ($mc==0)? 0 : ($edges/$mc); + my $mc_num=0; + my $mmc = ''; + for (my $m=0; $m<$mc; $m++){ + $mc_num= int ($d * $m); + my $mc_id = $edge_ids[$mc_num]; + $mmc.=($m==0)? "$mc_id" : ",$mc_id"; + } + print "all_edges : @edge_ids ; mmcs: $mmc \n"; + return $mmc +} + + + ################################################################################ # parse all arguments from command line and config file ################################################################################ @@ -2594,6 +2720,7 @@ sub parse_args 'num_tile=s', 'x_tiles=s', 'y_tiles=s', + 'board=s', 'dynamic_csm=s', 'gui!', 'log_all!', @@ -2651,8 +2778,20 @@ sub parse_args } } + # Patching Ariane submodule + if ($opt{ariane}) { + system("$ENV{DV_ROOT}/design/chip/tile/ariane_patch/ariane_patch.sh"); + } + + # Considering board specific defines, needed when sims is run from protosyn, not to confuse it with their incorrect values + if ($opt{board}) { + $ENV{PROTOSYN_RUNTIME_DESIGN_PATH} = $ENV{DV_ROOT} . "/design/xilinx"; + $ENV{PROTOSYN_RUNTIME_BOARD} = $opt{board}; + } + else { $ENV{PROTOSYN_RUNTIME_DESIGN_PATH} = $ENV{DV_ROOT} . "/verif/env/manycore"; $ENV{PROTOSYN_RUNTIME_BOARD} = ""; + } # these arguments may not have any options associated with them @@ -2727,7 +2866,110 @@ sub parse_args $ENV{PITON_PICO_HET} = $opt{pico_het}; $ENV{PITON_ARIANE} = $opt{ariane}; $ENV{PITON_RV64_PLATFORM} = "1" if ($opt{rv64_platform}); + $ENV{PITON_HBM_LAT} = $opt{hbm_lat}; push (@{$opt{config_rtl}}, "PITON_PICO_HET") if ($opt{pico_het}); + push (@{$opt{config_rtl}}, "PITON_HBM_LAT") if ($opt{hbm_lat}); + + my @mc_map; + + $ENV{PITON_EXTRA_MEMS} =0; + if ($opt{multimc}>0){ + my $piton_num_tiles=($opt{x_tiles} * $opt{y_tiles}); + my $edge_tiles = 2 * ($opt{x_tiles}-1 + $opt{y_tiles}-1); + if ($edge_tiles > $piton_num_tiles || $edge_tiles < 1){ + $edge_tiles = $piton_num_tiles; + } + if($edge_tiles > $opt{multimc} ){ + $edge_tiles =$opt{multimc}; + } + if (!$opt{hbm}){ + die ("DIE. Could not use -multimc option without -hbm option"); + } + + elsif ($edge_tiles > 30){ + print "Extra $edge_tiles connections to HBM (one per edge tile) are limited to 30.\n"; + $ENV{PITON_EXTRA_MEMS} =30; + } + else{ + print "Extra $edge_tiles connections to HBM will be used.\n"; + $ENV{PITON_EXTRA_MEMS} = $edge_tiles; + } + + if($opt{multimc_indices}){ + $ENV{PITON_MC_INDICES} =$opt{multimc_indices}; + my $str = $opt{multimc_indices}; + my @mc_tiles=split(/,/,$str); + my $l = scalar (@mc_tiles); + if( $l != $edge_tiles ){ + die ("DIE. the number of tile in multimc_indices $l is not equal to the number of multimc $edge_tiles.\n"); + } + my %seen; + foreach my $p ( @mc_tiles){ + die ("DIE. multiple tile number ($p) is given in multimc_indices:$str.\n") if(defined $seen{$p}); + $seen{$p}=1; + die ("DIE. $p is not a valid integer number in multimc_indices:$str.\n") if ( $p !~ /^[+-]?\d+$/); + die ("DIE. The tile number $p should be smaller that total number of tiles ($piton_num_tiles).\n") if ( $p >= $piton_num_tiles); + my $x_p = $p % $opt{x_tiles}; + my $y_p = ($p - $x_p) / $opt{y_tiles}; + if($x_p!=0 && $y_p!=0 && $x_p != $opt{x_tiles}-1 && $y_p!= $opt{y_tiles}-1){ + die ("DIE. The tile number $p ($x_p,$y_p) in multimc_indices is not an edge router.\n"); + } + + } + }else{ + my $mc_tiles=distribute_mc_equal_space_on_all_edges($opt{x_tiles},$opt{y_tiles},$ENV{PITON_EXTRA_MEMS}); + print "No memory controller (MC) indices are given as input. Distribute MCs with equal space on all edges:$mc_tiles\n"; + $ENV{PITON_MC_INDICES} =$mc_tiles; + } + + @mc_map = get_mc_mapping ($opt{x_tiles},$opt{y_tiles},$opt{multimc_indices},$ENV{PITON_EXTRA_MEMS},$ENV{PITON_NETWORK_CONFIG}); + } + + +my $mmc_num= $ENV{PITON_EXTRA_MEMS}; +my $mmc_num_tmp = ($mmc_num==0)? 1 : $mmc_num; +my $map_file =" + // This file is autogenrated using sims,2 and contains the memory controller mapping information + #ifndef MC_TILE_CONNECT_H + #define MC_TILE_CONNECT_H + + #define PITON_PORT_L 0 + #define PITON_PORT_E 1 + #define PITON_PORT_N 2 + #define PITON_PORT_W 3 + #define PITON_PORT_S 4 + + typedef struct \{ + unsigned int x; + unsigned int y; + unsigned int p; + unsigned int id; + unsigned int endp; + \} mc_map_t; + + #define MCS_NUM $mmc_num + + mc_map_t mc_map\[$mmc_num_tmp\]=\{ +"; + my $f=0; + foreach my $k (@mc_map){ + my $ax = $k->{'x'}; + my $ay = $k->{'y'}; + my $ap = $k->{'p'}; + my $id = $k->{'id'}; + my $endp = $k->{'endp'}; + $map_file .=",\n" if ($f!=0); + $f=1; + $map_file .=" \{ $ax, $ay, PITON_PORT_$ap, $id, $endp \}" + } + $map_file .="\{ 0,0,0,0,0\}" if($f==0); + + $map_file .= "\};\n #endif \n"; + my $mfile=$ENV{DV_ROOT} . "/tools/verilator/mcs_map_info.h"; + open( FFF, ">$mfile" ) or die "Can't open '$map_file': $!\n"; + print FFF $map_file; + close(FFF); + my $pton_x_tiles=""; my $pton_y_tiles=""; @@ -2902,6 +3144,9 @@ OPENPITON ARGUMENTS in the x dimension and Y tiles in the y dimension. If -x_tiles and -y_tiles is not specified, the default is X=1 and Y=1. The maximum value for both X and Y is 1024. + -board= enables board specific definitions. + -eth enables ethernet related hardware. + -hbm enables HBM related definitions. -ed_enable enable Execution Drafting in each core. @@ -3045,6 +3290,21 @@ VERILOG COMPILATION RELATED this specifies that the ARIANE RV64GC core shall be used in this case, programs are compiled and assembled using the RISCV GCC toolchain. + -hbm_lat + this specifies that the simulator considers an estimated latency for packets read from HBM memory. + without specifying this flag, the HBM memory (fake-memory module) has an ideal single-cycle read latency. + + -multimc=CHANNEL_NUMBER + default is zero and embeds only one memory controller (MC) in chipset. Given any inteher number + greater than zero (n) results in n MCs connected to routers located in edges. Each router located in + edge of the Mesh, can have maximum of one MC. The list of edge routers having MC should be given + using multimc_indices argument. + + -multimc_indices'= + This defines where each MC should be placed. The input is the list of edge tile's IDs seprated by ',' + the tile ID is (Y_index * x_tiles) + X_index; The number of edge routers in multimc_indices should be + equal to multimc + VERILOG RUNTIME RELATED -vcs_run/-novcs_run diff --git a/piton/verif/diag/c/riscv/ariane/mem_test.c b/piton/verif/diag/c/riscv/ariane/mem_test.c new file mode 100644 index 000000000..bddab315a --- /dev/null +++ b/piton/verif/diag/c/riscv/ariane/mem_test.c @@ -0,0 +1,224 @@ +// On-chip Static memory test +// Author: Alexander Kropotov, Barcelona Supercomputing Center + +#include +#include +#include +#include + +// #include +// #include + +#include "util.h" // for multi-core support + +int main(int argc, char ** argv) { + + // synchronization variable + volatile static uint32_t amo_cnt = 0; + // synchronize with other cores and wait until it is this core's turn + while(argv[0][0] != amo_cnt); + + enum { + RTL_SIMUL = 0, + MEM_BASEADDR = 0x8040000000, + MEM_ADRRANGE = RTL_SIMUL ? 512 : 0x00080000, + ETH_SYST_BASEADDR = 0xfff0800000, + TX_MEM_CPU_BASEADDR = ETH_SYST_BASEADDR + 0x00100000, + RX_MEM_CPU_BASEADDR = ETH_SYST_BASEADDR + 0x00200000 + + // SDRAM access; to exclude UART access read check below should be changed to "==" + // MEM_BASEADDR = 0x1ADD0000, + // MEM_ADRRANGE = 0x4000 + }; + + uint8_t volatile* memPtr8 = (uint8_t*)MEM_BASEADDR; //TX_MEM_CPU_BASEADDR, RX_MEM_CPU_BASEADDR + // int fid = open("/dev/mem", O_RDWR); + // if( fid < 0 ) { + // printf("Could not open /dev/mem \n"); + // exit(1); + // } + // memPtr8 = (uint8_t*)mmap(0, MEM_ADRRANGE, PROT_READ|PROT_WRITE, MAP_SHARED, fid, MEM_BASEADDR); + // if (memPtr8 == MAP_FAILED) { + // printf("Memory mapping of On-chip Static memory failed.\n"); + // exit(1); + // } + uint16_t volatile* memPtr16 = (uint16_t*)memPtr8; + uint32_t volatile* memPtr32 = (uint32_t*)memPtr8; + uint64_t volatile* memPtr64 = (uint64_t*)memPtr8; + + size_t const memBytes = MEM_ADRRANGE / sizeof(uint8_t); + size_t const axiWidth = 512 / 8; + + if (!RTL_SIMUL) { + printf("-- MEM test --\n"); + printf("-- Hart %d of %d: Test of MEM at addr 0x%lx(virt: 0x%lx) with size %d -- \n", + argv[0][0], argv[0][1], MEM_BASEADDR, (size_t)memPtr8, MEM_ADRRANGE); + // printf(" Checking memory with random values from %x to %x \n", 0, RAND_MAX); + // first clearing previously stored values + for (size_t addr = 0; addr < memBytes; ++addr) memPtr8 [addr] = 0; + } + + // filling the memory with some adddress function + uint64_t val = 0; + for (uint64_t addr = 0; addr < memBytes; addr += (RTL_SIMUL ? axiWidth:1)) { + val = (val >> 8) | ((addr ^ (~addr >> 8)) << 56); + size_t axiWordIdx = addr/axiWidth; + // changing written data type every wide AXI word + if (axiWordIdx%4 == 0) memPtr8 [addr ] = val >> 56; + if (axiWordIdx%4 == 1) memPtr16[addr/2] = val >> 48; + if (axiWordIdx%4 == 2) memPtr32[addr/4] = val >> 32; + if (axiWordIdx%4 == 3) memPtr64[addr/8] = val; + } + + // checking written values + val = 0; + size_t simulInc = 0; + for (uint64_t addr = 0; addr < memBytes; addr += (RTL_SIMUL ? simulInc:1) ) { + simulInc = axiWidth+1 + ((addr&4) ? 0 : (addr&3)); + val = (val >> 8) | ((addr ^ (~addr >> 8)) << 56); + // checking readback using different data types + if ((addr%8) == 7 && memPtr64[addr/8] != val) { + printf("ERR:HRT=%d ADR=%lx W64=%lx ", argv[0][0], addr, memPtr64[addr/8]); + if (RTL_SIMUL) continue; + printf(" expected = %lx \n", val); + exit(1); + } + if ((addr%4) == 3 && memPtr32[addr/4] != (val >> 32)) { + printf("ERR:HRT=%d ADR=%lx W32=%x ", argv[0][0], addr, memPtr32[addr/4]); + if (RTL_SIMUL) continue; + printf(" expected = %lx \n", val >> 32); + exit(1); + } + if ((addr%2) == 1 && memPtr16[addr/2] != (val >> 48)) { + printf("ERR:HRT=%d ADR=%lx W16=%x ", argv[0][0], addr, memPtr16[addr/2]); + if (RTL_SIMUL) continue; + printf(" expected = %lx \n", val >> 48); + exit(1); + } + if ( memPtr8 [addr ] != (val >> 56)) { + printf("ERR:HRT=%d ADR=%lx BYTE=%x ", argv[0][0], addr, memPtr8[addr]); + if (RTL_SIMUL) continue; + printf(" expected = %lx \n", val >> 56); + exit(1); + } + } + + if (!RTL_SIMUL) + printf("-- MEM test on hart %d of %d harts Passed --\n", argv[0][0], argv[0][1]); + + + if (!RTL_SIMUL && 0) { + printf("-- Hart %d of %d: BW measurement of memcpy() of MEM at addr 0x%lx(virt: 0x%lx) with size %d (100Gb Eth core is required)-- \n", + argv[0][0], argv[0][1], MEM_BASEADDR, (size_t)memPtr8, MEM_ADRRANGE); + + // Using Timer in 100Gb Eth core + enum { + TMRCTR_BASEADDR = ETH_SYST_BASEADDR + 0x00015000, + XTC_MAX_LOAD_VALUE = 0xFFFFFFFF, // Max supported load value for timer/counter + // Register Offset Definitions + // Register offsets within a timer counter, there are multiple timer counters within a single device + XTC_TCSR_OFFSET = 0 / sizeof(uint32_t), // Control/Status register + XTC_TLR_OFFSET = 4 / sizeof(uint32_t), // Load register + XTC_TCR_OFFSET = 8 / sizeof(uint32_t), // Timer counter register + // Control Status Register Bit Definitions + // Control Status Register bit masks, Used to configure the timer counter device. + XTC_CSR_CASC_MASK = 0x00000800, // Cascade Mode + XTC_CSR_ENABLE_ALL_MASK = 0x00000400, // Enables all timer counters + XTC_CSR_ENABLE_PWM_MASK = 0x00000200, // Enables the Pulse Width Modulation + XTC_CSR_INT_OCCURED_MASK = 0x00000100, // If bit is set, an interrupt has occured. + // If set and '1' is written to this bit position, bit is cleared. + XTC_CSR_ENABLE_TMR_MASK = 0x00000080, // Enables only the specific timer + XTC_CSR_ENABLE_INT_MASK = 0x00000040, // Enables the interrupt output. + XTC_CSR_LOAD_MASK = 0x00000020, // Loads the timer using the load value provided earlier in the Load Register, XTC_TLR_OFFSET. + XTC_CSR_AUTO_RELOAD_MASK = 0x00000010, // In compare mode, configures the timer counter to reload from the Load Register. + // The default mode causes the timer counter to hold when the compare value is hit. + // In capture mode, configures the timer counter to not hold the previous capture value + // if a new event occurs. + // The default mode cause the timer counter to hold the capture value until recognized. + XTC_CSR_EXT_CAPTURE_MASK = 0x00000008, // Enables the external input to the timer counter. + XTC_CSR_EXT_GENERATE_MASK = 0x00000004, // Enables the external generate output for the timer. + XTC_CSR_DOWN_COUNT_MASK = 0x00000002, // Configures the timer counter to count down from start value, the default is to count up + XTC_CSR_CAPTURE_MODE_MASK = 0x00000001 // Enables the timer to capture the timer counter value when the external capture line is asserted. + // The default mode is compare mode. + }; + uint32_t volatile* timerPtr = (uint32_t*)TMRCTR_BASEADDR; + float const TIMER_TICK = 1e-2; //us + // Timer initialization + timerPtr[XTC_TLR_OFFSET] = 0; // Set the compare register to 0. + timerPtr[XTC_TCSR_OFFSET] = XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK; // Reset the timer and the interrupt. + timerPtr[XTC_TCSR_OFFSET] = 0; // Release the reset. + + // first clearing previously stored values + for (size_t addr = 0; addr < memBytes; ++addr) memPtr8 [addr] = 0; + // filling 1st half of the memory with some adddress function + uint64_t val = 0; + for (uint64_t addr = 0; addr < memBytes/2; ++addr) { + val = (val >> 8) | ((addr ^ (~addr >> 8)) << 56); + memPtr8[addr] = val >> 56; + } + + // Resetting and starting Timer + // Read the current register contents such that only the necessary bits of the register are modified in the following operations + uint32_t timerCSR = timerPtr[XTC_TCSR_OFFSET]; + // Reset the timer counter such that it reloads from the compare register and the interrupt is cleared simultaneously, + // the interrupt can only be cleared after reset such that the interrupt condition is cleared + timerPtr[XTC_TCSR_OFFSET] = XTC_CSR_LOAD_MASK; + // Remove the reset condition such that the timer counter starts running with the value loaded from the compare register + timerPtr[XTC_TCSR_OFFSET] = timerCSR | XTC_CSR_ENABLE_TMR_MASK; + + // copying 1st half to the 2nd + memcpy((void*)(memPtr8 + MEM_ADRRANGE/2), (const void*)(memPtr8), MEM_ADRRANGE/2); + + float ownTime = timerPtr[XTC_TCR_OFFSET] * TIMER_TICK; // Get time + if (0) { + // Stop Timer, not needed if time is already captured + timerCSR = timerPtr[XTC_TCSR_OFFSET]; // Read the current register contents + timerCSR &= (uint32_t)(~(XTC_CSR_ENABLE_TMR_MASK)); // Disable the timer counter such that it's not running + timerPtr[XTC_TCSR_OFFSET] = timerCSR; //Write out the updated value to the actual register. + } + + // checking copied values + val = 0; + for (uint64_t addr = 0; addr < memBytes/2; ++addr) { + val = (val >> 8) | ((addr ^ (~addr >> 8)) << 56); + if (memPtr8[addr + memBytes/2] != (val >> 56)) { + printf("ERROR memcpy low->high:HRT=%d ADR=%lx BYTE=%x ", argv[0][0], addr + memBytes/2, memPtr8[addr + memBytes/2]); + printf(" expected = %lx \n", val >> 56); + exit(1); + } + } + float ownSpeed = memBytes/2 / ownTime * 1e6 / 1024; + printf("Low->High memcpy time: %ld us, Speed: %ld kB/s \n", (uint64_t)ownTime, (uint64_t)ownSpeed); + + // clearing 1st half of the memory + for (size_t addr = 0; addr < memBytes/2; ++addr) memPtr8 [addr] = 0; + + // Resetting and starting Timer + timerCSR = timerPtr[XTC_TCSR_OFFSET]; + timerPtr[XTC_TCSR_OFFSET] = XTC_CSR_LOAD_MASK; + timerPtr[XTC_TCSR_OFFSET] = timerCSR | XTC_CSR_ENABLE_TMR_MASK; + // copying 2nd half to the 1st + memcpy((void*)(memPtr8), (const void*)(memPtr8 + MEM_ADRRANGE/2), MEM_ADRRANGE/2); + ownTime = timerPtr[XTC_TCR_OFFSET] * TIMER_TICK; // Get time + + // checking copied values + val = 0; + for (uint64_t addr = 0; addr < memBytes/2; ++addr) { + val = (val >> 8) | ((addr ^ (~addr >> 8)) << 56); + if (memPtr8[addr] != (val >> 56)) { + printf("ERROR memcpy high->low:HRT=%d ADR=%lx BYTE=%x ", argv[0][0], addr, memPtr8[addr]); + printf(" expected = %lx \n", val >> 56); + exit(1); + } + } + ownSpeed = memBytes/2 / ownTime * 1e6 / 1024; + printf("High->Low memcpy time: %ld us, Speed: %ld kB/s \n", (uint64_t)ownTime, (uint64_t)ownSpeed); + + printf("-- BW measurement on hart %d of %d harts Passed --\n", argv[0][0], argv[0][1]); + } + + // increment atomic counter + ATOMIC_OP(amo_cnt, 1, add, w); + + return 0; +} diff --git a/piton/verif/diag/c/riscv/ariane/test.list b/piton/verif/diag/c/riscv/ariane/test.list new file mode 100644 index 000000000..7de6a166b --- /dev/null +++ b/piton/verif/diag/c/riscv/ariane/test.list @@ -0,0 +1,2 @@ +hello_world.c +accu_test.c diff --git a/piton/verif/env/common/fake_mem_ctrl.flist b/piton/verif/env/common/fake_mem_ctrl.flist index 55f171303..17a877842 100644 --- a/piton/verif/env/common/fake_mem_ctrl.flist +++ b/piton/verif/env/common/fake_mem_ctrl.flist @@ -24,3 +24,5 @@ // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. fake_mem_ctrl.v +hbm_delay_pck.sv +hbm_delay.sv diff --git a/piton/verif/env/common/fake_mem_ctrl.v b/piton/verif/env/common/fake_mem_ctrl.v index 652850a80..71772ff1c 100644 --- a/piton/verif/env/common/fake_mem_ctrl.v +++ b/piton/verif/env/common/fake_mem_ctrl.v @@ -43,7 +43,9 @@ `define MEM_ADDR_WIDTH 64 -module fake_mem_ctrl( +module fake_mem_ctrl #( + parameter HMB_CHAN_NUM=0 +)( input wire clk, input wire rst_n, @@ -53,12 +55,19 @@ module fake_mem_ctrl( output reg noc_ready_in, - output reg noc_valid_out, - output reg [`NOC_DATA_WIDTH-1:0] noc_data_out, + output noc_valid_out, + output [`NOC_DATA_WIDTH-1:0] noc_data_out, input wire noc_ready_out ); + + reg noc_valid_out_tmp; + reg [`NOC_DATA_WIDTH-1:0] noc_data_out_tmp; + wire noc_ready_out_tmp; + + + reg mem_valid_in; reg [3*`NOC_DATA_WIDTH-1:0] mem_header_in; reg mem_ready_in; @@ -189,6 +198,7 @@ reg [`NOC_DATA_WIDTH-1:0] msg_send_data [7:0]; reg [`NOC_DATA_WIDTH-1:0] mem_temp; wire [`NOC_DATA_WIDTH*3-1:0] msg_send_header; +reg [`PHY_ADDR_WIDTH-1:0] msg_addr_o,msg_addr_o_next; @@ -583,6 +593,8 @@ l2_encoder encoder( .msg_src_chipid ({`NOC_CHIPID_WIDTH{1'b0}}), .msg_src_x ({`NOC_X_WIDTH{1'b0}}), .msg_src_y ({`NOC_Y_WIDTH{1'b0}}), + .msg_ini_x ({`NOC_X_WIDTH{1'b0}}), + .msg_ini_y ({`NOC_Y_WIDTH{1'b0}}), .msg_src_fbits ({`NOC_FBITS_WIDTH{1'b0}}), .msg_sdid ({`MSG_SDID_WIDTH{1'b0}}), .msg_lsid ({`MSG_LSID_WIDTH{1'b0}}), @@ -602,7 +614,7 @@ reg [3:0] buf_out_rd_ptr_next; always @ * begin - noc_valid_out = (buf_out_counter_f != 0); + noc_valid_out_tmp = (buf_out_counter_f != 0); end always @ * @@ -613,7 +625,7 @@ end always @ * begin - if (noc_valid_out && noc_ready_out) + if (noc_valid_out_tmp && noc_ready_out_tmp) begin buf_out_counter_next = buf_out_counter_f - 1; end @@ -646,7 +658,7 @@ begin begin buf_out_rd_ptr_next = 0; end - else if (noc_valid_out && noc_ready_out) + else if (noc_valid_out_tmp && noc_ready_out_tmp) begin buf_out_rd_ptr_next = buf_out_rd_ptr_f + 1; end @@ -683,6 +695,7 @@ begin buf_out_mem_next[6] = msg_send_data[5]; buf_out_mem_next[7] = msg_send_data[6]; buf_out_mem_next[8] = msg_send_data[7]; + msg_addr_o_next= msg_addr; end else begin @@ -695,6 +708,7 @@ begin buf_out_mem_next[6] = buf_out_mem_f[6]; buf_out_mem_next[7] = buf_out_mem_f[7]; buf_out_mem_next[8] = buf_out_mem_f[8]; + msg_addr_o_next = msg_addr_o; end end @@ -711,6 +725,7 @@ begin buf_out_mem_f[6] <= 0; buf_out_mem_f[7] <= 0; buf_out_mem_f[8] <= 0; + msg_addr_o <= {`PHY_ADDR_WIDTH{1'b0}}; end else begin @@ -723,21 +738,22 @@ begin buf_out_mem_f[6] <= buf_out_mem_next[6]; buf_out_mem_f[7] <= buf_out_mem_next[7]; buf_out_mem_f[8] <= buf_out_mem_next[8]; + msg_addr_o <= msg_addr_o_next; end end always @ * begin - noc_valid_out = (buf_out_counter_f != 0); + noc_valid_out_tmp = (buf_out_counter_f != 0); end always @ * begin // Tri: another quick fix for x - noc_data_out = 0; + noc_data_out_tmp = 0; if (buf_out_rd_ptr_f < 9) - noc_data_out = buf_out_mem_f[buf_out_rd_ptr_f]; + noc_data_out_tmp = buf_out_mem_f[buf_out_rd_ptr_f]; end `ifndef MINIMAL_MONITORING @@ -749,15 +765,70 @@ always @(posedge clk) begin $display("FakeMem: input: %h", noc_data_in, $time); `endif end - if (noc_valid_out & noc_ready_out) begin + if (noc_valid_out_tmp & noc_ready_out_tmp) begin `ifdef VERILATOR - $display("FakeMem: output %h", noc_data_out); + $display("FakeMem: output %h", noc_data_out_tmp); `else - $display("FakeMem: output %h", noc_data_out, $time); + $display("FakeMem: output %h", noc_data_out_tmp, $time); `endif end end `endif // endif MINIMAL_MONITORING + +//apply RD delay estimations +`ifdef PITON_HBM_LAT + +hbm_delay #( + .HMB_CHAN_NUM (HMB_CHAN_NUM ) + ) hbm_delay ( + .clk (clk ), + .rst_n (rst_n ), + .noc_valid_in (noc_valid_out_tmp ), + .noc_data_in (noc_data_out_tmp ), + .noc_ready_in (noc_ready_out_tmp ), + .msg_addr (msg_addr_o ), + .noc_valid_out (noc_valid_out ), + .noc_data_out (noc_data_out ), + .noc_ready_out (noc_ready_out )); + + `ifndef MINIMAL_MONITORING + always @(posedge clk) begin + if (noc_valid_out & noc_ready_out) begin + $display("Delay: output %h", noc_data_out, $time); + end + end + `endif + +/* + integer tmp1,tmp2; +initial begin + tmp1=$fopen("delay.txt","w"); + tmp2=$fopen("fake.txt","w"); +end + + always @(posedge clk) begin + if (noc_valid_out & noc_ready_out) begin + $fdisplay(tmp1,"%h", noc_data_out); + $fflush(tmp1); + end + + if (noc_valid_out_tmp & noc_ready_out_tmp) begin + $fdisplay(tmp2,"%h", noc_data_out_tmp); + $fflush(tmp2); + end +end +*/ + + +`else + + assign noc_valid_out = noc_valid_out_tmp; + assign noc_data_out = noc_data_out_tmp; + assign noc_ready_out_tmp = noc_ready_out; + +`endif + + endmodule diff --git a/piton/verif/env/common/hbm_delay.sv b/piton/verif/env/common/hbm_delay.sv new file mode 100644 index 000000000..15c47e617 --- /dev/null +++ b/piton/verif/env/common/hbm_delay.sv @@ -0,0 +1,885 @@ +/**************************************************************************** + * hbm_delay.sv + ****************************************************************************/ + +`include "define.tmp.h" + +module hbm_delay + import hbm_delay_pck::*; + #( + parameter HMB_CHAN_NUM=0 + )( + input wire clk, + input wire rst_n, + + input wire noc_valid_in, + input wire [`NOC_DATA_WIDTH-1:0] noc_data_in, + output noc_ready_in, + + input [`PHY_ADDR_WIDTH-1:0] msg_addr, + output reg noc_valid_out, + output reg [`NOC_DATA_WIDTH-1:0] noc_data_out, + input wire noc_ready_out + ); + + + + //calculate expected read delay based on HBM-Chanel number and message address + wire [DELAYw-1 : 0] rd_delay; + expected_delay #( + .HMB_CHAN_NUM(HMB_CHAN_NUM) + ) exp_delay ( + .msg_addr_i(msg_addr), + .rd_delay_o(rd_delay) + ); + + //get the incomming pck flit type + wire head_in,tail_in; + flit_type_detect type_detect ( + .clk (clk ), + .rst_n (rst_n ), + .noc_valid_in (noc_valid_in & noc_ready_in ), + .noc_data_in (noc_data_in ), + .flit_type_o ({head_in,tail_in} )); + + + // A global clock counter + reg [TIMERw-1:0] timer, expected_time_in, rd_delay_tmp,largest_delay_tmp; + always @(posedge clk) begin + if(~rst_n) timer<={TIMERw{1'b0}}; + else timer <= timer+1'b1; + end + + always @(*) begin + rd_delay_tmp = {TIMERw{1'b0}}; + rd_delay_tmp[DELAYw-1 : 0] = rd_delay; + largest_delay_tmp = {TIMERw{1'b0}}; + largest_delay_tmp[DELAYw-1 : 0]= MAX_LAT; + end + + //Expected packet inject time is current time + expected delay + assign expected_time_in = timer + rd_delay_tmp; + + + // save input flit in FIFOs according to delay time and FIFO num + // make sure the selcted fifo wont change until getting the entire packets + logic [DELAY_FIFO_NUM-1 : 0] fifo_wr,fifo_in_sel, fifo_in_sel1 , fifo_in_sel2 ; + assign fifo_in_sel = (head_in)? fifo_in_sel1 : fifo_in_sel2; + + + fifo_dat_t fifo_in; + assign fifo_in = '{ + flit: noc_data_in, + head:head_in, + tail:tail_in, + exp_time:expected_time_in + }; + + fifo_dat_t fifo_out [DELAY_FIFO_NUM-1 : 0]; + + + + wire [DELAY_FIFO_NUM-1 : 0] granted_queue,inject_rdy,full,not_empty; + logic [DELAY_FIFO_NUM-1 : 0] fifo_rd; + + wire any_grant; + + assign noc_ready_in = |(~full & fifo_in_sel); + + + + genvar i; + generate + for (i=0;i= MIN_LAT + (LAT_STEP*i)) && (rd_delay < MIN_LAT+(LAT_STEP*(i+1))); + else assign fifo_in_sel1[i] = (rd_delay >= MIN_LAT+(LAT_STEP*i)); + + assign fifo_wr[i]= noc_valid_in & fifo_in_sel[i] & noc_ready_in; + + /* + When should injecte the incomming packet: + 1- exp_time <= timer. Expected packet injection time is smaller than current time + 2- exp_time is larger than current time but its difference is larger than the largest + expected latency.Here a timer overfllow happend. + */ + + assign inject_rdy [i] = + (fifo_out[i].exp_time <= timer)? 1'b1 : + (fifo_out[i].exp_time -timer > largest_delay_tmp)? 1'b1 : 1'b0; + + + + + hbm_delay_fwft_fifo_bram #( + .DATA_WIDTH (FIFO_DW ), + .MAX_DEPTH (DELAY_FIFO_DEPTH ), + .IGNORE_SAME_LOC_RD_WR_WARNING ("NO" ) + ) fwft_fifo ( + .din (fifo_in), + .wr_en (fifo_wr[i] ), + .rd_en (fifo_rd[i] ), + .dout (fifo_out[i] ), + .full (full [i] ), + .nearly_full ( ), + .recieve_more_than_0 (not_empty[i] ), + .recieve_more_than_1 ( ), + .reset (~rst_n ), + .clk (clk ) + ); + end + endgenerate + + localparam SELw = $clog2(DELAY_FIFO_NUM); + wire [SELw-1 : 0] granted_bin; + + //If there are more than one FIFO ready to inject packets + //arbitrate between them + thermo_arbiter #( + .ARBITER_WIDTH(DELAY_FIFO_NUM) + ) + arbiter + ( + .request(inject_rdy & not_empty), + .grant(granted_queue), + .any_grant(any_grant), + .clk(clk), + .reset(~rst_n) + ); + + hbm_one_hot_to_bin #( + .ONE_HOT_WIDTH (DELAY_FIFO_NUM ), + .BIN_WIDTH (SELw ) + ) hbm_one_hot_to_bin ( + .one_hot_code (granted_queue ), + .bin_code (granted_bin ) + ); + + enum bit {IDEAL, LOCK} ps, ns; + reg [SELw-1 : 0] fifo_out_sel_next,fifo_out_sel; + + always @(*) begin + fifo_rd={DELAY_FIFO_NUM{1'b0}}; + fifo_out_sel_next= fifo_out_sel; + noc_valid_out=1'b0; + ns =ps; + noc_data_out=fifo_out[fifo_out_sel].flit; + + case(ps) + IDEAL: begin + if( any_grant)begin + if(noc_ready_out)begin + fifo_out_sel_next = granted_bin; + fifo_rd[granted_bin]=1'b1; + if(fifo_out[granted_bin].tail==1'b0) ns = LOCK; + end + noc_valid_out=1'b1; + noc_data_out=fifo_out[granted_bin].flit; + + end + end + LOCK: begin //lock to fifo until sending the entire packet + if(not_empty[fifo_out_sel]) begin + if(noc_ready_out)begin + fifo_rd[fifo_out_sel]=1'b1; + if(fifo_out[fifo_out_sel].tail) ns =IDEAL; + end + noc_valid_out=1'b1; + noc_data_out=fifo_out[fifo_out_sel].flit; + + end + end + endcase + + + assert ($onehot0(fifo_wr)) else begin + $error("Only one bit in fifo_wr (%b) should be asserted",fifo_wr); + $stop; + end + + assert (~(fifo_wr==0 && noc_valid_in===1'b1 && noc_ready_in===1'b1)) else begin + $error("No fifo_wr is selected when noc_valid_in is one"); + $stop; + end + end + + + always @(posedge clk ) begin + if(~rst_n) begin + ps<=IDEAL; + fifo_out_sel<= 0; + fifo_in_sel2<= 1; + end else begin + ps<=ns; + fifo_out_sel<= fifo_out_sel_next; + if (head_in) fifo_in_sel2 <= fifo_in_sel1; + end + + if((noc_valid_in & noc_ready_in)==1'b1 && ~$onehot(fifo_in_sel)) begin + $error("fifo_in_sel (%b) should be onehot coded when noc_valid_in (%b) is asserted",fifo_in_sel,noc_valid_in); + $stop; + end + + if (noc_valid_out==1'b1 && noc_ready_out==1'b0 && fifo_rd>0 )begin + $error("write to NoC when it was not ready"); + $stop; + end + end + +endmodule + + + +module flit_type_detect + import hbm_delay_pck::*; + + ( + input wire clk, + input wire rst_n, + input wire noc_valid_in, + input wire [`NOC_DATA_WIDTH-1:0] noc_data_in, + output [1:0] flit_type_o + ); + + flit_type_t flit_type,flit_type_next; + + + + wire [`MSG_LENGTH_WIDTH-1 :0] length = noc_data_in [ `MSG_LENGTH ]; + reg [`MSG_LENGTH_WIDTH-1 :0] counter, counter_next; + reg tail,head; + assign flit_type_o = {head,tail}; + + + always @ (*) begin + counter_next = counter; + flit_type_next =flit_type; + tail=1'b0; + head=1'b0; + if(noc_valid_in)begin + case(flit_type) + HEADER:begin + counter_next = length; + head=1'b1; + if(length == 0)begin + tail=1'b1; + end else if (length == 1) begin + flit_type_next = TAIL; + end else begin + flit_type_next = BODY; + end + end + BODY: begin + counter_next = counter -1'b1; + if(counter == 2) begin + flit_type_next = TAIL; + end + end + TAIL: begin + flit_type_next = HEADER; + tail=1'b1; + end + default: begin + + end + endcase + + end + end + + always @ (posedge clk) begin + if(~rst_n) begin + flit_type<=HEADER; + counter<=0; + end else begin + flit_type<=flit_type_next; + counter<=counter_next; + end + end + + + +endmodule + + + + +/**************************** + * expected_delay + * *************************/ + +module expected_delay + import hbm_delay_pck::*; + #( + parameter HMB_CHAN_NUM= 0 + )( + input [`PHY_ADDR_WIDTH-1:0] msg_addr_i, + output [DELAYw-1 : 0] rd_delay_o + ); + + /* verilator lint_off WIDTH */ + localparam [CHAN_GROUPw-1 : 0] HMB_CHAN_GROUP_NUM = HMB_CHAN_NUM/CHANNEL_WITH_SAME_DELAY; + /* verilator lint_on WIDTH */ + + logic [DELAYw-1 : 0] delays [CHAN_GROUP-1:0]; + + assign delays = HBM_CHAN_DELAYS; + + + wire [CHAN_GROUPw-1 : 0] input_chan_num = msg_addr_i[CHAN_BASE_ADDR+ CHAN_GROUPw-1 :CHAN_BASE_ADDR]; + wire [CHAN_GROUPw-1 : 0] channel_distance; + wire [DELAYw-1 : 0] diff; + + /* verilator lint_off CMPCONST */ + assign diff = (input_chan_num > HMB_CHAN_GROUP_NUM)? delays[input_chan_num]-delays[HMB_CHAN_GROUP_NUM] : delays[HMB_CHAN_GROUP_NUM]- delays[input_chan_num]; + /* verilator lint_on CMPCONST */ + + + assign rd_delay_o = delays[0] + diff; + +endmodule + + + +/*********************************** + + module bin_to_one_hot + + + ************************************/ + + +module hbm_bin_to_one_hot #( + parameter BIN_WIDTH = 2, + parameter ONE_HOT_WIDTH = 2**BIN_WIDTH + + ) + ( + input [BIN_WIDTH-1 : 0] bin_code, + output [ONE_HOT_WIDTH-1 : 0] one_hot_code + ); + + genvar i; + generate + for(i=0; i1)? log2(ONE_HOT_WIDTH):1 + ) + ( + input [ONE_HOT_WIDTH-1 : 0] one_hot_code, + output [BIN_WIDTH-1 : 0] bin_code + + ); + + + function integer log2; + input integer number; begin + log2=(number <=1) ? 1: 0; + while(2**log21)begin :if1 + for(i=0; i= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1; + assign empty = depth == {DEPTH_DATA_WIDTH{1'b0}}; + assign recieve_more_than_0 = ~ empty; + assign recieve_more_than_1 = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} || depth== 1 ); + + + + + //synthesis translate_off + //synopsys translate_off + always @(posedge clk) + begin + if (wr_en & ~rd_en & full) begin + $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH); + $finish; + end + /* verilator lint_off WIDTH */ + if (rd_en & !recieve_more_than_0 & IGNORE_SAME_LOC_RD_WR_WARNING == "NO") begin + $display("%t ERROR: Attempt to read an empty FIFO: %m", $time); + $finish; + end + if (rd_en & ~wr_en & !recieve_more_than_0 & (IGNORE_SAME_LOC_RD_WR_WARNING == "YES")) begin + $display("%t ERROR: Attempt to read an empty FIFO: %m", $time); + $finish; + end + /* verilator lint_on WIDTH */ + end // always @ (posedge clk) + + //synopsys translate_on + //synthesis translate_on + + + + +endmodule + + + +/********************************** + + bram_based_fifo + + *********************************/ + + +module hbm_delay_bram_based_fifo #( + parameter Dw = 72,//data_width + parameter B = 10// buffer num + )( + din, + wr_en, + rd_en, + dout, + full, + nearly_full, + empty, + reset, + clk + ); + + + function integer log2; + input integer number; begin + log2=(number <=1) ? 1: 0; + while(2**log2=Bint2; // B-1 + assign empty = depth == {DEPTHw{1'b0}}; + + //synthesis translate_off + //synopsys translate_off + always @(posedge clk) + begin + if(~reset)begin + if (wr_en && depth == B[DEPTHw-1 : 0] && !rd_en) begin + $display(" %t: ERROR: Attempt to write to full FIFO: %m",$time); + $finish; + end + if (rd_en && depth == {DEPTHw{1'b0}}) begin + $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time); + $finish; + end + end//~reset + end + //synopsys translate_on + //synthesis translate_on + +endmodule // fifo + + + +module hbm_delay_register + #( + parameter W=1, + parameter RESET_TO={W{1'b0}} + + )( + input [W-1:0] in, + input reset, + input clk, + output [W-1:0] out + ); + + hbm_register_reset_init #( + .W(W) + )reg1( + .in(in), + .reset(reset), + .clk(clk), + .out(out), + .reset_to(RESET_TO[W-1 : 0]) + ); +endmodule + + + + + +module hbm_register_reset_init + #( + parameter W=1 + )( + input [W-1:0] in, + input reset, + input clk, + output reg [W-1:0] out, + input [W-1 : 0] reset_to + ); + + + always @ (posedge clk )begin + if(reset) out<=reset_to; + else out<=in; + end + +endmodule + + + + + + + + + diff --git a/piton/verif/env/common/hbm_delay_pck.sv b/piton/verif/env/common/hbm_delay_pck.sv new file mode 100644 index 000000000..8ccaa8c80 --- /dev/null +++ b/piton/verif/env/common/hbm_delay_pck.sv @@ -0,0 +1,65 @@ +/**************************************************************************** + * hbm_delay_pck.sv + ****************************************************************************/ + +package hbm_delay_pck; + + `include "define.tmp.h" + + /* + * Design Write Latency (clock cycles) Read Latency (clock cycles) Write Throughput (GB/s) Read Throughput (GB/s) Bandwidth (GB/s) +HBM in AXI 0 accessing PSCH0 14 48 0.58 4.65 +HBM in AXI 0 accessing PSCH4 16 50 0.52 4.65 +HBM in AXI 0 accessing PSCH8 18 52 0.46 4.65 +HBM in AXI 0 accessing PSCH12 20 54 0.42 4.65 +HBM in AXI 0 accessing PSCH16 31 67 0.28 4.65 +HBM in AXI 0 accessing PSCH20 33 69 0.27 4.65 +HBM in AXI 0 accessing PSCH24 35 71 0.25 4.65 +HBM in AXI 0 accessing PSCH28 37 73 0.24 4.65 + */ + + typedef enum bit [1:0] {HEADER, BODY,TAIL} flit_type_t; + + + localparam TOTAL_CHAN_NUM = 32; + localparam CHANNEL_WITH_SAME_DELAY=4; + localparam TIMERw=10; + + localparam INTERLEAVE_ADDR_RANGE= 'h1000_0000; // + /* + 'h1000_0000; //256 M (default no interlevaing) + 'h100_000; //1 M + + */ + + + + + localparam CHAN_GROUP= TOTAL_CHAN_NUM/CHANNEL_WITH_SAME_DELAY; + localparam MAX_RD_DELAY = 73; // maximum RD pipeline stage delay + localparam DELAYw = $clog2(MAX_RD_DELAY); + localparam CHAN_GROUPw= $clog2(CHAN_GROUP); + localparam CHAN_BASE_ADDR = $clog2(INTERLEAVE_ADDR_RANGE*4); //Each four phy chan has same lat + + localparam [DELAYw-1 : 0] HBM_CHAN_DELAYS [CHAN_GROUP-1 : 0]='{73,71,69,67,54,52,50,48}; + localparam DELAY_FIFO_NUM = 2; + localparam DELAY_FIFO_DEPTH = 200; // 200/9 = 22 packets + + localparam MIN_LAT = HBM_CHAN_DELAYS [0]; + localparam MAX_LAT = HBM_CHAN_DELAYS [CHAN_GROUP-1]; + localparam LAT_STEP= (MAX_LAT - MIN_LAT)/DELAY_FIFO_NUM; + + + + typedef struct packed { + logic [`NOC_DATA_WIDTH-1:0] flit; + bit head; + bit tail; + logic [TIMERw-1:0] exp_time; + } fifo_dat_t ; + localparam FIFO_DW = $bits(fifo_dat_t); + + + + +endpackage diff --git a/piton/verif/env/manycore/cross_module.h.pyv b/piton/verif/env/manycore/cross_module.h.pyv index a893b0956..b374b7955 100644 --- a/piton/verif/env/manycore/cross_module.h.pyv +++ b/piton/verif/env/manycore/cross_module.h.pyv @@ -31,7 +31,7 @@ #MAX_THREAD = 128; MAX_TILE = 64; - PITON_NUM_TILES = int(os.environ.get('PTON_NUM_TILES', '-1')) + PITON_NUM_TILES = int(os.environ.get('PITON_NUM_TILES', '-1')) #print "//num_tiles:", num_tiles if PITON_NUM_TILES == -1: @@ -99,7 +99,7 @@ for i in range(PITON_NUM_TILES): printstring = """ `define TILE%d `CHIP.tile%d - `define ARIANE_CORE%d `TILE%d.g_ariane_core.core.ariane.i_cva6 + `define ARIANE_CORE%d `TILE%d.g_ariane_core.core.ariane `define SPARC_CORE%d `TILE%d.g_sparc_core.core `define PICO_CORE%d `TILE%d.g_picorv32_core.core `define CCX_TRANSDUCER%d `TILE%d.g_sparc_core.ccx_l15_transducer diff --git a/piton/verif/env/manycore/manycore_top.v.pyv b/piton/verif/env/manycore/manycore_top.v.pyv index b5dd22500..406a9db9e 100644 --- a/piton/verif/env/manycore/manycore_top.v.pyv +++ b/piton/verif/env/manycore/manycore_top.v.pyv @@ -305,7 +305,11 @@ system system( `endif // endif PITON_CHIPSET_DIFF_CLK `else // ifndef PITON_CHIPSET_CLKS_GEN `ifndef VERILATOR +`ifdef PITON_EXTRA_MEMS + .chipset_clk(core_ref_clk), +`else .chipset_clk(chipset_clk), +`endif `else .chipset_clk(core_ref_clk), `endif @@ -408,7 +412,15 @@ system system( `ifdef PITON_NOC_POWER_CHIPSET_TEST .sw({4'bz, 4'd`PITON_NOC_POWER_CHIPSET_TEST_HOP_COUNT}), `else // ifndef PITON_NOC_POWER_CHIPSET_TEST - .sw(), + .sw( +`ifdef PITONSYS_IOCTRL + `ifdef PITONSYS_UART + `ifdef PITONSYS_UART_BOOT + {1'b1, 7'bz} // applying uart_boot_en signal + `endif // endif PITONSYS_UART_BOOT + `endif // endif PITONSYS_UART +`endif // endif PITONSYS_IOCTRL + ), `endif // endif PITON_NOC_POWER_CHIPSET_TEST // Do not provide any functionality @@ -516,9 +528,11 @@ system system( .clk (jtag_clk) ); + `ifndef PITONSYS_IOCTRL iob_mon iob_mon( .clk (chipset_clk) ); + `endif // sas, more debug info // turn on sas interface after a delay diff --git a/piton/verif/env/manycore/monitor.v.pyv b/piton/verif/env/manycore/monitor.v.pyv index 72fb15637..788262f9b 100644 --- a/piton/verif/env/manycore/monitor.v.pyv +++ b/piton/verif/env/manycore/monitor.v.pyv @@ -52,7 +52,7 @@ module monitor(/*AUTOARG*/ err_f = 1; bad = 0; `ifndef VERILATOR - max_cycle = 30000; + max_cycle = 6000000; `else // ifndef VERILATOR max_cycle = 1500000; `endif // ifndef VERILATOR