diff --git a/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp b/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
index 51860f195cce7..2357c986b92c5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
@@ -478,7 +478,8 @@ class AMDGPUWaitSGPRHazards {
       };
 
       for (MachineInstr &MI : MBB) {
-        if (MI.isMetaInstruction())
+        if (MI.isMetaInstruction() &&
+            MI.getOpcode() != AMDGPU::SI_WAVE_CF_EDGE)
           continue;
 
         if (MI.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR &&
@@ -500,8 +501,9 @@ class AMDGPUWaitSGPRHazards {
           continue;
         }
 
-        // Do not optimize over branches
-        if (PrevWait && (MI.isCall() || MI.isReturn() || MI.isBranch())) {
+        // Do not optimize over branches or control-flow edge markers.
+        if (PrevWait && (MI.isCall() || MI.isReturn() || MI.isBranch() ||
+                         MI.getOpcode() == AMDGPU::SI_WAVE_CF_EDGE)) {
           PrevWait->moveBefore(&MI);
           PrevWait = nullptr;
           Changed = true;
diff --git a/llvm/test/CodeGen/AMDGPU/WaveTransform/divergence-divergent-i1-used-outside-loop.ll b/llvm/test/CodeGen/AMDGPU/WaveTransform/divergence-divergent-i1-used-outside-loop.ll
index 48b3e29e0d488..d77e4686c082c 100644
--- a/llvm/test/CodeGen/AMDGPU/WaveTransform/divergence-divergent-i1-used-outside-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/WaveTransform/divergence-divergent-i1-used-outside-loop.ll
@@ -1,4 +1,3 @@
-; XFAIL: *
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX1100-W64 %s
 ; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX1100-W32 %s
@@ -306,60 +305,57 @@ define void @divergent_i1_xor_used_outside_loop_larger_loop_body(i32 %num.elts,
 ; GFX1100-W64-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-W64-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v0
 ; GFX1100-W64-NEXT:    s_mov_b32 s6, 0
-; GFX1100-W64-NEXT:    s_mov_b64 s[8:9], -1
+; GFX1100-W64-NEXT:    s_mov_b64 s[12:13], -1
 ; GFX1100-W64-NEXT:    s_mov_b64 s[4:5], 0
-; GFX1100-W64-NEXT:    s_xor_b64 s[10:11], s[0:1], exec
+; GFX1100-W64-NEXT:    s_xor_b64 s[8:9], s[0:1], exec
 ; GFX1100-W64-NEXT:    s_mov_b64 s[2:3], s[0:1]
-; GFX1100-W64-NEXT:    s_mov_b64 exec, s[10:11]
+; GFX1100-W64-NEXT:    s_mov_b64 exec, s[8:9]
 ; GFX1100-W64-NEXT:    ; divergent control-flow edge
 ; GFX1100-W64-NEXT:    s_cbranch_execz .LBB3_5
 ; GFX1100-W64-NEXT:  .LBB3_1: ; %loop.start.preheader
-; GFX1100-W64-NEXT:    s_mov_b64 s[10:11], -1
-; GFX1100-W64-NEXT:    s_and_b64 s[8:9], s[8:9], exec
-; GFX1100-W64-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[10:11]
+; GFX1100-W64-NEXT:    s_mov_b64 s[8:9], -1
 ; GFX1100-W64-NEXT:    s_mov_b64 s[10:11], 0
-; GFX1100-W64-NEXT:    s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1100-W64-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[10:11]
+; GFX1100-W64-NEXT:    s_and_b64 s[12:13], s[12:13], exec
 ; GFX1100-W64-NEXT:    .p2align 6
 ; GFX1100-W64-NEXT:  .LBB3_2: ; %loop.start
 ; GFX1100-W64-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX1100-W64-NEXT:    s_ashr_i32 s7, s6, 31
 ; GFX1100-W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1100-W64-NEXT:    s_lshl_b64 s[8:9], s[6:7], 2
-; GFX1100-W64-NEXT:    v_add_co_u32 v7, vcc, v1, s8
+; GFX1100-W64-NEXT:    s_lshl_b64 s[12:13], s[6:7], 2
+; GFX1100-W64-NEXT:    v_add_co_u32 v5, vcc, v1, s12
 ; GFX1100-W64-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-W64-NEXT:    v_add_co_ci_u32_e64 v8, null, s9, v2, vcc
-; GFX1100-W64-NEXT:    global_load_b32 v7, v[7:8], off
+; GFX1100-W64-NEXT:    v_add_co_ci_u32_e64 v6, null, s13, v2, vcc
+; GFX1100-W64-NEXT:    global_load_b32 v5, v[5:6], off
 ; GFX1100-W64-NEXT:    s_waitcnt vmcnt(0)
-; GFX1100-W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1100-W64-NEXT:    v_mov_b32_e32 v7, v5
+; GFX1100-W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
+; GFX1100-W64-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[8:9]
 ; GFX1100-W64-NEXT:    s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1100-W64-NEXT:    s_xor_b64 s[8:9], vcc, exec
-; GFX1100-W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1100-W64-NEXT:    s_xor_b64 s[10:11], exec, s[8:9]
-; GFX1100-W64-NEXT:    s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1100-W64-NEXT:    s_and_b64 s[10:11], s[10:11], exec
-; GFX1100-W64-NEXT:    s_or_b64 s[4:5], s[4:5], s[10:11]
-; GFX1100-W64-NEXT:    s_mov_b64 exec, s[8:9]
+; GFX1100-W64-NEXT:    s_xor_b64 s[12:13], vcc, exec
+; GFX1100-W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1100-W64-NEXT:    s_xor_b64 s[14:15], exec, s[12:13]
+; GFX1100-W64-NEXT:    s_and_b64 s[14:15], s[14:15], exec
+; GFX1100-W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-W64-NEXT:    s_or_b64 s[4:5], s[4:5], s[14:15]
+; GFX1100-W64-NEXT:    s_mov_b64 exec, s[12:13]
 ; GFX1100-W64-NEXT:    ; divergent control-flow edge
 ; GFX1100-W64-NEXT:    s_cbranch_execz .LBB3_4
 ; GFX1100-W64-NEXT:  .LBB3_3: ; %loop.cond
 ; GFX1100-W64-NEXT:    ; in Loop: Header=BB3_2 Depth=1
 ; GFX1100-W64-NEXT:    v_cmp_lt_i32_e32 vcc, s6, v0
-; GFX1100-W64-NEXT:    s_add_i32 s12, s6, 1
-; GFX1100-W64-NEXT:    v_mov_b32_e32 v7, v6
-; GFX1100-W64-NEXT:    s_xor_b64 s[8:9], vcc, exec
+; GFX1100-W64-NEXT:    s_add_i32 s16, s6, 1
+; GFX1100-W64-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[10:11]
+; GFX1100-W64-NEXT:    s_xor_b64 s[12:13], vcc, exec
 ; GFX1100-W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1100-W64-NEXT:    s_xor_b64 s[6:7], exec, s[8:9]
-; GFX1100-W64-NEXT:    s_and_b64 s[10:11], s[6:7], exec
-; GFX1100-W64-NEXT:    s_mov_b32 s6, s12
-; GFX1100-W64-NEXT:    s_or_b64 s[4:5], s[4:5], s[10:11]
-; GFX1100-W64-NEXT:    s_mov_b64 exec, s[8:9]
+; GFX1100-W64-NEXT:    s_xor_b64 s[6:7], exec, s[12:13]
+; GFX1100-W64-NEXT:    s_and_b64 s[14:15], s[6:7], exec
+; GFX1100-W64-NEXT:    s_mov_b32 s6, s16
+; GFX1100-W64-NEXT:    s_or_b64 s[4:5], s[4:5], s[14:15]
+; GFX1100-W64-NEXT:    s_mov_b64 exec, s[12:13]
 ; GFX1100-W64-NEXT:    ; divergent control-flow edge
 ; GFX1100-W64-NEXT:    s_cbranch_execnz .LBB3_2
 ; GFX1100-W64-NEXT:  .LBB3_4: ; %loop.exit.guard
 ; GFX1100-W64-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX1100-W64-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX1100-W64-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GFX1100-W64-NEXT:    s_xor_b64 s[4:5], vcc, exec
 ; GFX1100-W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX1100-W64-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
@@ -382,38 +378,37 @@ define void @divergent_i1_xor_used_outside_loop_larger_loop_body(i32 %num.elts,
 ; GFX1100-W32:       ; %bb.0: ; %entry
 ; GFX1100-W32-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-W32-NEXT:    v_cmp_ne_u32_e64 s2, 0, v0
-; GFX1100-W32-NEXT:    s_mov_b32 s0, 0
-; GFX1100-W32-NEXT:    s_mov_b32 s1, -1
 ; GFX1100-W32-NEXT:    s_mov_b32 s4, 0
-; GFX1100-W32-NEXT:    s_xor_b32 s5, s2, exec_lo
+; GFX1100-W32-NEXT:    s_mov_b32 s1, -1
+; GFX1100-W32-NEXT:    s_mov_b32 s5, 0
+; GFX1100-W32-NEXT:    s_xor_b32 s0, s2, exec_lo
 ; GFX1100-W32-NEXT:    s_mov_b32 s3, s2
-; GFX1100-W32-NEXT:    s_mov_b32 exec_lo, s5
+; GFX1100-W32-NEXT:    s_mov_b32 exec_lo, s0
 ; GFX1100-W32-NEXT:    ; divergent control-flow edge
 ; GFX1100-W32-NEXT:    s_cbranch_execz .LBB3_5
 ; GFX1100-W32-NEXT:  .LBB3_1: ; %loop.start.preheader
-; GFX1100-W32-NEXT:    s_mov_b32 s5, -1
-; GFX1100-W32-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s0
-; GFX1100-W32-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s5
+; GFX1100-W32-NEXT:    s_mov_b32 s6, -1
+; GFX1100-W32-NEXT:    s_mov_b32 s0, 0
 ; GFX1100-W32-NEXT:    s_and_b32 s1, s1, exec_lo
 ; GFX1100-W32-NEXT:    .p2align 6
 ; GFX1100-W32-NEXT:  .LBB3_2: ; %loop.start
 ; GFX1100-W32-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX1100-W32-NEXT:    s_ashr_i32 s1, s0, 31
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1100-W32-NEXT:    s_lshl_b64 s[6:7], s[0:1], 2
-; GFX1100-W32-NEXT:    v_add_co_u32 v7, vcc_lo, v1, s6
+; GFX1100-W32-NEXT:    s_lshl_b64 s[8:9], s[0:1], 2
+; GFX1100-W32-NEXT:    v_add_co_u32 v5, vcc_lo, v1, s8
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-W32-NEXT:    v_add_co_ci_u32_e64 v8, null, s7, v2, vcc_lo
-; GFX1100-W32-NEXT:    global_load_b32 v7, v[7:8], off
+; GFX1100-W32-NEXT:    v_add_co_ci_u32_e64 v6, null, s9, v2, vcc_lo
+; GFX1100-W32-NEXT:    global_load_b32 v5, v[5:6], off
 ; GFX1100-W32-NEXT:    s_waitcnt vmcnt(0)
-; GFX1100-W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v7
-; GFX1100-W32-NEXT:    v_mov_b32_e32 v7, v5
+; GFX1100-W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v5
+; GFX1100-W32-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s6
 ; GFX1100-W32-NEXT:    s_xor_b32 s1, vcc_lo, exec_lo
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1100-W32-NEXT:    s_xor_b32 s5, exec_lo, s1
-; GFX1100-W32-NEXT:    s_and_b32 s5, s5, exec_lo
+; GFX1100-W32-NEXT:    s_xor_b32 s7, exec_lo, s1
+; GFX1100-W32-NEXT:    s_and_b32 s7, s7, exec_lo
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-W32-NEXT:    s_or_b32 s4, s4, s5
+; GFX1100-W32-NEXT:    s_or_b32 s5, s5, s7
 ; GFX1100-W32-NEXT:    s_mov_b32 exec_lo, s1
 ; GFX1100-W32-NEXT:    ; divergent control-flow edge
 ; GFX1100-W32-NEXT:    s_cbranch_execz .LBB3_4
@@ -421,19 +416,19 @@ define void @divergent_i1_xor_used_outside_loop_larger_loop_body(i32 %num.elts,
 ; GFX1100-W32-NEXT:    ; in Loop: Header=BB3_2 Depth=1
 ; GFX1100-W32-NEXT:    v_cmp_lt_i32_e32 vcc_lo, s0, v0
 ; GFX1100-W32-NEXT:    s_add_i32 s0, s0, 1
-; GFX1100-W32-NEXT:    v_mov_b32_e32 v7, v6
+; GFX1100-W32-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s4
 ; GFX1100-W32-NEXT:    s_xor_b32 s1, vcc_lo, exec_lo
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1100-W32-NEXT:    s_xor_b32 s5, exec_lo, s1
-; GFX1100-W32-NEXT:    s_and_b32 s5, s5, exec_lo
+; GFX1100-W32-NEXT:    s_xor_b32 s7, exec_lo, s1
+; GFX1100-W32-NEXT:    s_and_b32 s7, s7, exec_lo
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-W32-NEXT:    s_or_b32 s4, s4, s5
+; GFX1100-W32-NEXT:    s_or_b32 s5, s5, s7
 ; GFX1100-W32-NEXT:    s_mov_b32 exec_lo, s1
 ; GFX1100-W32-NEXT:    ; divergent control-flow edge
 ; GFX1100-W32-NEXT:    s_cbranch_execnz .LBB3_2
 ; GFX1100-W32-NEXT:  .LBB3_4: ; %loop.exit.guard
-; GFX1100-W32-NEXT:    s_or_b32 exec_lo, exec_lo, s4
-; GFX1100-W32-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX1100-W32-NEXT:    s_or_b32 exec_lo, exec_lo, s5
+; GFX1100-W32-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v5
 ; GFX1100-W32-NEXT:    s_xor_b32 s0, vcc_lo, exec_lo
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX1100-W32-NEXT:    s_or_b32 s3, s3, s0
@@ -794,53 +789,52 @@ exit:
 define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, ptr addrspace(1) %a, ptr addrspace(1) %a.break) {
 ; GFX1100-W64-LABEL: loop_with_1break:
 ; GFX1100-W64:       ; %bb.0: ; %entry
-; GFX1100-W64-NEXT:    s_mov_b64 s[0:1], -1
-; GFX1100-W64-NEXT:    s_mov_b32 s2, -1
-; GFX1100-W64-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
+; GFX1100-W64-NEXT:    s_mov_b32 s6, -1
+; GFX1100-W64-NEXT:    s_mov_b64 s[4:5], -1
 ; GFX1100-W64-NEXT:    s_mov_b64 s[0:1], 0
-; GFX1100-W64-NEXT:    s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1100-W64-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
+; GFX1100-W64-NEXT:    s_mov_b64 s[2:3], 0
 ; GFX1100-W64-NEXT:    .p2align 6
 ; GFX1100-W64-NEXT:  .LBB6_1: ; %A
 ; GFX1100-W64-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1100-W64-NEXT:    global_load_b32 v8, v[2:3], off
+; GFX1100-W64-NEXT:    global_load_b32 v6, v[2:3], off
 ; GFX1100-W64-NEXT:    s_waitcnt vmcnt(0)
-; GFX1100-W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v8
+; GFX1100-W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
+; GFX1100-W64-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; GFX1100-W64-NEXT:    s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1100-W64-NEXT:    s_xor_b64 s[4:5], vcc, exec
+; GFX1100-W64-NEXT:    s_xor_b64 s[8:9], vcc, exec
 ; GFX1100-W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1100-W64-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
-; GFX1100-W64-NEXT:    s_and_b64 s[6:7], s[6:7], exec
+; GFX1100-W64-NEXT:    s_xor_b64 s[10:11], exec, s[8:9]
+; GFX1100-W64-NEXT:    s_and_b64 s[10:11], s[10:11], exec
 ; GFX1100-W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-W64-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
-; GFX1100-W64-NEXT:    s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1100-W64-NEXT:    s_mov_b64 exec, s[4:5]
+; GFX1100-W64-NEXT:    s_or_b64 s[2:3], s[2:3], s[10:11]
+; GFX1100-W64-NEXT:    s_mov_b64 exec, s[8:9]
 ; GFX1100-W64-NEXT:    ; divergent control-flow edge
 ; GFX1100-W64-NEXT:    s_cbranch_execz .LBB6_4
 ; GFX1100-W64-NEXT:  .LBB6_2: ; %loop.body
 ; GFX1100-W64-NEXT:    ; in Loop: Header=BB6_1 Depth=1
-; GFX1100-W64-NEXT:    global_load_b32 v8, v[0:1], off
+; GFX1100-W64-NEXT:    global_load_b32 v6, v[0:1], off
 ; GFX1100-W64-NEXT:    v_add_co_u32 v2, vcc, v2, 4
-; GFX1100-W64-NEXT:    s_add_i32 s2, s2, 1
+; GFX1100-W64-NEXT:    s_add_i32 s6, s6, 1
 ; GFX1100-W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-W64-NEXT:    s_cmpk_lt_u32 s2, 0x64
+; GFX1100-W64-NEXT:    s_cmpk_lt_u32 s6, 0x64
 ; GFX1100-W64-NEXT:    v_add_co_ci_u32_e64 v3, null, 0, v3, vcc
 ; GFX1100-W64-NEXT:    s_waitcnt vmcnt(0)
-; GFX1100-W64-NEXT:    v_add_nc_u32_e32 v8, 1, v8
-; GFX1100-W64-NEXT:    global_store_b32 v[0:1], v8, off
+; GFX1100-W64-NEXT:    v_add_nc_u32_e32 v6, 1, v6
+; GFX1100-W64-NEXT:    global_store_b32 v[0:1], v6, off
 ; GFX1100-W64-NEXT:    v_add_co_u32 v0, vcc, v0, 4
 ; GFX1100-W64-NEXT:    s_waitcnt_depctr depctr_va_vcc(0)
 ; GFX1100-W64-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc
 ; GFX1100-W64-NEXT:    s_cbranch_scc0 .LBB6_1
 ; GFX1100-W64-NEXT:  ; %bb.3:
-; GFX1100-W64-NEXT:    v_mov_b32_e32 v6, v7
+; GFX1100-W64-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
 ; GFX1100-W64-NEXT:  .LBB6_4: ; %loop.exit.guard
-; GFX1100-W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX1100-W64-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX1100-W64-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX1100-W64-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; GFX1100-W64-NEXT:    s_waitcnt_depctr depctr_va_vcc(0)
 ; GFX1100-W64-NEXT:    s_xor_b64 s[0:1], exec, vcc
 ; GFX1100-W64-NEXT:    s_mov_b64 exec, vcc
+; GFX1100-W64-NEXT:    s_waitcnt_depctr depctr_sa_sdst(0)
 ; GFX1100-W64-NEXT:    ; divergent control-flow edge
 ; GFX1100-W64-NEXT:    s_cbranch_execz .LBB6_6
 ; GFX1100-W64-NEXT:  .LBB6_5: ; %break.body
@@ -853,42 +847,43 @@ define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, ptr addrspace(1) %a
 ; GFX1100-W32:       ; %bb.0: ; %entry
 ; GFX1100-W32-NEXT:    s_mov_b32 s0, -1
 ; GFX1100-W32-NEXT:    s_mov_b32 s1, 0
-; GFX1100-W32-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s0
-; GFX1100-W32-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s1
+; GFX1100-W32-NEXT:    s_mov_b32 s3, -1
+; GFX1100-W32-NEXT:    s_mov_b32 s2, 0
 ; GFX1100-W32-NEXT:    .p2align 6
 ; GFX1100-W32-NEXT:  .LBB6_1: ; %A
 ; GFX1100-W32-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1100-W32-NEXT:    global_load_b32 v8, v[2:3], off
+; GFX1100-W32-NEXT:    global_load_b32 v6, v[2:3], off
 ; GFX1100-W32-NEXT:    s_waitcnt vmcnt(0)
-; GFX1100-W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v8
-; GFX1100-W32-NEXT:    s_xor_b32 s2, vcc_lo, exec_lo
+; GFX1100-W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v6
+; GFX1100-W32-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s0
+; GFX1100-W32-NEXT:    s_xor_b32 s4, vcc_lo, exec_lo
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1100-W32-NEXT:    s_xor_b32 s3, exec_lo, s2
-; GFX1100-W32-NEXT:    s_and_b32 s3, s3, exec_lo
+; GFX1100-W32-NEXT:    s_xor_b32 s5, exec_lo, s4
+; GFX1100-W32-NEXT:    s_and_b32 s5, s5, exec_lo
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-W32-NEXT:    s_or_b32 s1, s1, s3
-; GFX1100-W32-NEXT:    s_mov_b32 exec_lo, s2
+; GFX1100-W32-NEXT:    s_or_b32 s2, s2, s5
+; GFX1100-W32-NEXT:    s_mov_b32 exec_lo, s4
 ; GFX1100-W32-NEXT:    ; divergent control-flow edge
 ; GFX1100-W32-NEXT:    s_cbranch_execz .LBB6_4
 ; GFX1100-W32-NEXT:  .LBB6_2: ; %loop.body
 ; GFX1100-W32-NEXT:    ; in Loop: Header=BB6_1 Depth=1
-; GFX1100-W32-NEXT:    global_load_b32 v8, v[0:1], off
+; GFX1100-W32-NEXT:    global_load_b32 v6, v[0:1], off
 ; GFX1100-W32-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 4
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
 ; GFX1100-W32-NEXT:    v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
-; GFX1100-W32-NEXT:    s_add_i32 s0, s0, 1
-; GFX1100-W32-NEXT:    s_cmpk_lt_u32 s0, 0x64
+; GFX1100-W32-NEXT:    s_add_i32 s3, s3, 1
+; GFX1100-W32-NEXT:    s_cmpk_lt_u32 s3, 0x64
 ; GFX1100-W32-NEXT:    s_waitcnt vmcnt(0)
-; GFX1100-W32-NEXT:    v_add_nc_u32_e32 v8, 1, v8
-; GFX1100-W32-NEXT:    global_store_b32 v[0:1], v8, off
+; GFX1100-W32-NEXT:    v_add_nc_u32_e32 v6, 1, v6
+; GFX1100-W32-NEXT:    global_store_b32 v[0:1], v6, off
 ; GFX1100-W32-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 4
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX1100-W32-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
 ; GFX1100-W32-NEXT:    s_cbranch_scc0 .LBB6_1
 ; GFX1100-W32-NEXT:  ; %bb.3:
-; GFX1100-W32-NEXT:    v_mov_b32_e32 v6, v7
+; GFX1100-W32-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s1
 ; GFX1100-W32-NEXT:  .LBB6_4: ; %loop.exit.guard
-; GFX1100-W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX1100-W32-NEXT:    s_or_b32 exec_lo, exec_lo, s2
 ; GFX1100-W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX1100-W32-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v6
 ; GFX1100-W32-NEXT:    s_xor_b32 s0, exec_lo, vcc_lo